| /Zephyr-Core-3.5.0/drivers/gpio/ |
| D | gpio_kscan_ite_it8xxx2.c | 4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
42 const struct gpio_kscan_cfg *const config = dev->config; in gpio_kscan_it8xxx2_configure()
43 volatile uint8_t *reg_ksi_kso_gctrl = config->reg_ksi_kso_gctrl; in gpio_kscan_it8xxx2_configure()
44 volatile uint8_t *reg_ksi_kso_goen = config->reg_ksi_kso_goen; in gpio_kscan_it8xxx2_configure()
45 volatile uint8_t *reg_ksi_kso_gdat = config->reg_ksi_kso_gdat; in gpio_kscan_it8xxx2_configure()
46 volatile uint8_t *reg_ksi_kso_gpod = config->reg_ksi_kso_gpod; in gpio_kscan_it8xxx2_configure()
47 uint8_t mask = BIT(pin); in gpio_kscan_it8xxx2_configure() local
53 return -ENOTSUP; in gpio_kscan_it8xxx2_configure()
57 *reg_ksi_kso_gctrl |= mask; in gpio_kscan_it8xxx2_configure()
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| D | gpio_mcux.c | 5 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/gpio/nxp-kinetis-gpio.h>
38 const struct gpio_mcux_config *config = dev->config; in gpio_mcux_configure()
39 GPIO_Type *gpio_base = config->gpio_base; in gpio_mcux_configure()
40 PORT_Type *port_base = config->port_base; in gpio_mcux_configure()
41 uint32_t mask = 0U; in gpio_mcux_configure() local
45 if (pin >= ARRAY_SIZE(port_base->PCR)) { in gpio_mcux_configure()
46 return -EINVAL; in gpio_mcux_configure()
50 return -ENOTSUP; in gpio_mcux_configure()
54 return -ENOTSUP; in gpio_mcux_configure()
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| D | gpio_rv32m1.c | 6 * SPDX-License-Identifier: Apache-2.0
77 const struct gpio_rv32m1_config *config = dev->config; in gpio_rv32m1_configure()
78 GPIO_Type *gpio_base = config->gpio_base; in gpio_rv32m1_configure()
79 PORT_Type *port_base = config->port_base; in gpio_rv32m1_configure()
80 uint32_t mask = 0U; in gpio_rv32m1_configure() local
84 if (pin >= ARRAY_SIZE(port_base->PCR)) { in gpio_rv32m1_configure()
85 return -EINVAL; in gpio_rv32m1_configure()
90 return -EINVAL; in gpio_rv32m1_configure()
94 return -ENOTSUP; in gpio_rv32m1_configure()
98 return -ENOTSUP; in gpio_rv32m1_configure()
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| D | gpio_ite_it8xxx2_v2.c | 4 * SPDX-License-Identifier: Apache-2.0
17 #include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
18 #include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
45 /* Wake up control mask */
69 const struct gpio_ite_cfg *gpio_config = dev->config; in gpio_ite_configure()
70 volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr; in gpio_ite_configure()
71 volatile uint8_t *reg_gpotr = (uint8_t *)gpio_config->reg_gpotr; in gpio_ite_configure()
72 volatile uint8_t *reg_p18scr = (uint8_t *)gpio_config->reg_p18scr; in gpio_ite_configure()
73 volatile uint8_t *reg_gpcr = (uint8_t *)gpio_config->reg_gpcr + pin; in gpio_ite_configure()
74 struct gpio_ite_data *data = dev->data; in gpio_ite_configure()
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| D | gpio_mchp_xec.c | 4 * SPDX-License-Identifier: Apache-2.0
21 ((__IO uint32_t *)(GPIO_PARIN_BASE + (config->port_num << 2)))
24 ((__IO uint32_t *)(GPIO_PAROUT_BASE + (config->port_num << 2)))
52 * notes: The GPIO parallel output bits are read-only until the
53 * Alternate-Output-Disable (AOD) bit is set in the pin's control
65 const struct gpio_xec_config *config = dev->config; in gpio_xec_configure()
68 uint32_t mask = 0U; in gpio_xec_configure() local
72 if ((valid_ctrl_masks[config->port_num] & BIT(pin)) == 0U) { in gpio_xec_configure()
73 return -EINVAL; in gpio_xec_configure()
79 return -ENOTSUP; in gpio_xec_configure()
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| D | gpio_esp32.c | 5 * SPDX-License-Identifier: Apache-2.0
10 /* Include esp-idf headers first to avoid redefining BIT() macro */
22 #include <zephyr/dt-bindings/gpio/espressif-esp32-gpio.h>
46 #define CPU_ID() arch_curr_cpu()->id
91 const struct gpio_esp32_config *const cfg = dev->config; in gpio_esp32_config()
92 struct gpio_esp32_data *data = dev->data; in gpio_esp32_config()
93 uint32_t io_pin = (uint32_t) pin + ((cfg->gpio_port == 1 && pin < 32) ? 32 : 0); in gpio_esp32_config()
99 return -EINVAL; in gpio_esp32_config()
112 ret = -EINVAL; in gpio_esp32_config()
126 if (rtc_io_desc[rtcio_num].pullup) { in gpio_esp32_config()
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| D | gpio_mcux_igpio.c | 4 * SPDX-License-Identifier: Apache-2.0
46 const struct mcux_igpio_config *config = dev->config; in mcux_igpio_configure()
47 GPIO_Type *base = config->base; in mcux_igpio_configure()
52 /* Some SOCs have non-contiguous gpio pin layouts, account for this */ in mcux_igpio_configure()
53 for (i = 0; i < config->gap_count; i++) { in mcux_igpio_configure()
54 if (pin >= config->pin_gaps[i].start) { in mcux_igpio_configure()
55 if (pin < (config->pin_gaps[i].start + in mcux_igpio_configure()
56 config->pin_gaps[i].len)) { in mcux_igpio_configure()
58 return -ENOTSUP; in mcux_igpio_configure()
60 cfg_idx -= config->pin_gaps[i].len; in mcux_igpio_configure()
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| D | gpio_ite_it8xxx2.c | 4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
12 #include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
57 ((struct gpio_ite_data *)(dev)->data)
60 ((const struct gpio_ite_cfg *)(dev)->config)
63 * Convert wake-up controller (WUC) group to the corresponding wake-up edge
73 * From WUESR1-WUESR4, the address increases by ones. From WUESR5 on in wuesr()
77 (volatile uint8_t *)(IT8XXX2_WUC_WUESR1 + grp-1) : in wuesr()
78 (volatile uint8_t *)(IT8XXX2_WUC_WUESR5 + 4*(grp-5)); in wuesr()
82 * Convert wake-up controller (WUC) group to the corresponding wake-up edge
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| /Zephyr-Core-3.5.0/dts/bindings/pinctrl/ |
| D | ite,it8xxx2-pinctrl-func.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "ite,it8xxx2-pinctrl-func"
11 func3-gcr:
14 func3-en-mask:
17 func3-ext:
21 the setting of func3-gcr, some pins require external setting.
23 func3-ext-mask:
26 func4-gcr:
29 func4-en-mask:
32 volt-sel:
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| /Zephyr-Core-3.5.0/dts/riscv/ite/ |
| D | it81xx2.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
11 gpiogcr: gpio-gcr@f01600 {
12 compatible = "ite,it8xxx2-gpiogcr";
17 compatible = "ite,it8xxx2-gpiokscan";
23 reg-names = "goen", "gctrl", "gdat", "gdmr", "gpod";
25 gpio-controller;
26 #gpio-cells = <2>;
30 compatible = "ite,it8xxx2-gpiokscan";
36 reg-names = "goen", "gctrl", "gdat", "gdmr", "gpod";
38 gpio-controller;
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| D | it82xx2.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
12 compatible = "mmio-sram";
16 intc: interrupt-controller@f03f00 {
17 compatible = "ite,it8xxx2-intc-v2";
18 #address-cells = <0>;
19 #interrupt-cells = <2>;
20 interrupt-controller;
25 compatible = "ite,it8xxx2-watchdog";
29 interrupt-parent = <&intc>;
32 gpiogcr: gpio-gcr@f03e00 {
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| /Zephyr-Core-3.5.0/drivers/pinctrl/ |
| D | pinctrl_ite_it8xxx2.c | 4 * SPDX-License-Identifier: Apache-2.0
25 /* function 3 enable mask */
29 /* function 3 external mask */
33 /* function 4 enable mask */
37 /* Input voltage selection mask */
50 * KSO push-pull/open-drain bit of KSO[15:0] control register
55 * KSI/KSO pullup bit of KSI[7:0]/KSO[15:0] control register
71 const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config; in pinctrl_it8xxx2_set()
72 const struct pinctrl_it8xxx2_gpio *gpio = &(pinctrl_config->gpio); in pinctrl_it8xxx2_set()
73 uint32_t pincfg = pins->pincfg; in pinctrl_it8xxx2_set()
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| /Zephyr-Core-3.5.0/drivers/sdhc/ |
| D | imx_usdhc.c | 4 * SPDX-License-Identifier: Apache-2.0
96 struct usdhc_data *data = dev->data; in transfer_complete_cb()
99 data->transfer_status |= TRANSFER_DATA_FAILED; in transfer_complete_cb()
101 data->transfer_status |= TRANSFER_DATA_COMPLETE; in transfer_complete_cb()
103 data->transfer_status |= TRANSFER_CMD_FAILED; in transfer_complete_cb()
105 data->transfer_status |= TRANSFER_CMD_COMPLETE; in transfer_complete_cb()
107 k_sem_give(&data->transfer_sem); in transfer_complete_cb()
110 static int imx_usdhc_dat3_pull(const struct usdhc_config *cfg, bool pullup) in imx_usdhc_dat3_pull() argument
114 ret = pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_NOPULL); in imx_usdhc_dat3_pull()
120 if (!pullup) { in imx_usdhc_dat3_pull()
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| /Zephyr-Core-3.5.0/soc/riscv/riscv-ite/common/ |
| D | chip_chipregs.h | 3 * SPDX-License-Identifier: Apache-2.0
25 * MASK operation macros
44 /* --- General Control (GCTRL) --- */
226 /* 0x049: PWM Output Open-Drain Enable */
241 /* --- Wake-Up Control (WUC) --- */
244 /* TODO: should a defined interface for configuring wake-up interrupts */
398 * 24-bit timers: external timer 3, 5, and 7
399 * 32-bit timers: external timer 4, 6, and 8
548 /* From BXh to BDh are EP FIFO 1-3 Control 0/1 Registers, and their
581 /* 0xB8 ~ 0xBD EP FIFO 1-3 Control 0/1 Registers */
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| /Zephyr-Core-3.5.0/doc/releases/ |
| D | release-notes-3.3.rst | 14 * Introduced :ref:`USB-C <usbc_api>` device stack with PD (power delivery)
17 CMSIS-DSP as the default backend.
30 * CVE-2023-0359: Under embargo until 2023-04-20
32 * CVE-2023-0779: Under embargo until 2023-04-22
66 removed in favor of new :dtcompatible:`zephyr,flash-disk` devicetree binding.
71 * Starting from this release ``zephyr-`` prefixed tags won't be created
82 image states). Use of a truncated hash or non-sha256 hash will still work
88 registration function at boot-up. If applications register this then
93 application code, these will now automatically be registered at boot-up (this
129 This may cause out-of-tree scripts or commands to fail if they have relied
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