4  * SPDX-License-Identifier: Apache-2.0
96 	struct usdhc_data *data = dev->data;  in transfer_complete_cb()
99 		data->transfer_status |= TRANSFER_DATA_FAILED;  in transfer_complete_cb()
101 		data->transfer_status |= TRANSFER_DATA_COMPLETE;  in transfer_complete_cb()
103 		data->transfer_status |= TRANSFER_CMD_FAILED;  in transfer_complete_cb()
105 		data->transfer_status |= TRANSFER_CMD_COMPLETE;  in transfer_complete_cb()
107 	k_sem_give(&data->transfer_sem);  in transfer_complete_cb()
110 static int imx_usdhc_dat3_pull(const struct usdhc_config *cfg, bool pullup)  in imx_usdhc_dat3_pull()  argument
114 	ret = pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_NOPULL);  in imx_usdhc_dat3_pull()
120 	if (!pullup) {  in imx_usdhc_dat3_pull()
122 		if (cfg->pwr_gpio.port) {  in imx_usdhc_dat3_pull()
123 			ret = gpio_pin_set_dt(&cfg->pwr_gpio, 0);  in imx_usdhc_dat3_pull()
129 			ret = gpio_pin_set_dt(&cfg->pwr_gpio, 1);  in imx_usdhc_dat3_pull()
146 	const struct usdhc_config *cfg = dev->config;  in imx_usdhc_error_recovery()
147 	uint32_t status = USDHC_GetPresentStatusFlags(cfg->base);  in imx_usdhc_error_recovery()
151 		USDHC_Reset(cfg->base, kUSDHC_ResetCommand, 100U);  in imx_usdhc_error_recovery()
154 		(USDHC_GetAdmaErrorStatusFlags(cfg->base) != 0U)) {  in imx_usdhc_error_recovery()
156 		USDHC_Reset(cfg->base, kUSDHC_DataInhibitFlag, 100U);  in imx_usdhc_error_recovery()
165 	const struct usdhc_config *cfg = dev->config;  in imx_usdhc_init_host_props()
166 	struct usdhc_data *data = dev->data;  in imx_usdhc_init_host_props()
168 	struct sdhc_host_props *props = &data->props;  in imx_usdhc_init_host_props()
171 	props->f_max = cfg->max_bus_freq;  in imx_usdhc_init_host_props()
172 	props->f_min = cfg->min_bus_freq;  in imx_usdhc_init_host_props()
173 	props->max_current_330 = cfg->max_current_330;  in imx_usdhc_init_host_props()
174 	props->max_current_180 = cfg->max_current_180;  in imx_usdhc_init_host_props()
175 	props->power_delay = cfg->power_delay_ms;  in imx_usdhc_init_host_props()
177 	USDHC_GetCapability(cfg->base, &caps);  in imx_usdhc_init_host_props()
178 	if (cfg->no_180_vol) {  in imx_usdhc_init_host_props()
179 		props->host_caps.vol_180_support = false;  in imx_usdhc_init_host_props()
181 		props->host_caps.vol_180_support = (bool)(caps.flags & kUSDHC_SupportV180Flag);  in imx_usdhc_init_host_props()
183 	props->host_caps.vol_300_support = (bool)(caps.flags & kUSDHC_SupportV300Flag);  in imx_usdhc_init_host_props()
184 	props->host_caps.vol_330_support = (bool)(caps.flags & kUSDHC_SupportV330Flag);  in imx_usdhc_init_host_props()
185 	props->host_caps.suspend_res_support = (bool)(caps.flags & kUSDHC_SupportSuspendResumeFlag);  in imx_usdhc_init_host_props()
186 	props->host_caps.sdma_support = (bool)(caps.flags & kUSDHC_SupportDmaFlag);  in imx_usdhc_init_host_props()
187 	props->host_caps.high_spd_support = (bool)(caps.flags & kUSDHC_SupportHighSpeedFlag);  in imx_usdhc_init_host_props()
188 	props->host_caps.adma_2_support = (bool)(caps.flags & kUSDHC_SupportAdmaFlag);  in imx_usdhc_init_host_props()
189 	props->host_caps.max_blk_len = (bool)(caps.maxBlockLength);  in imx_usdhc_init_host_props()
190 	props->host_caps.ddr50_support = (bool)(caps.flags & kUSDHC_SupportDDR50Flag);  in imx_usdhc_init_host_props()
191 	props->host_caps.sdr104_support = (bool)(caps.flags & kUSDHC_SupportSDR104Flag);  in imx_usdhc_init_host_props()
192 	props->host_caps.sdr50_support = (bool)(caps.flags & kUSDHC_SupportSDR50Flag);  in imx_usdhc_init_host_props()
193 	props->host_caps.bus_8_bit_support = (bool)(caps.flags & kUSDHC_Support8BitFlag);  in imx_usdhc_init_host_props()
194 	props->host_caps.bus_4_bit_support = (bool)(caps.flags & kUSDHC_Support4BitFlag);  in imx_usdhc_init_host_props()
195 	props->host_caps.hs200_support = (bool)(cfg->mmc_hs200_1_8v);  in imx_usdhc_init_host_props()
196 	props->host_caps.hs400_support = (bool)(cfg->mmc_hs400_1_8v);  in imx_usdhc_init_host_props()
204 	const struct usdhc_config *cfg = dev->config;  in imx_usdhc_reset()
206 	UDSHC_SelectVoltage(cfg->base, false);  in imx_usdhc_reset()
207 	USDHC_EnableDDRMode(cfg->base, false, 0U);  in imx_usdhc_reset()
209 	USDHC_EnableStandardTuning(cfg->base, 0, 0, false);  in imx_usdhc_reset()
210 	USDHC_EnableAutoTuning(cfg->base, false);  in imx_usdhc_reset()
215 	USDHC_EnableHS400Mode(cfg->base, false);  in imx_usdhc_reset()
217 	USDHC_EnableStrobeDLL(cfg->base, false);  in imx_usdhc_reset()
221 	return USDHC_Reset(cfg->base, kUSDHC_ResetAll, 100U) == true ? 0 : -ETIMEDOUT;  in imx_usdhc_reset()
229 	while (timeout--) {  in imx_usdhc_wait_clock_gate()
230 		if (base->PRES_STATE & USDHC_PRES_STATE_SDOFF_MASK) {  in imx_usdhc_wait_clock_gate()
244 	const struct usdhc_config *cfg = dev->config;  in imx_usdhc_set_io()
245 	struct usdhc_data *data = dev->data;  in imx_usdhc_set_io()
247 	struct sdhc_io *host_io = &data->host_io;  in imx_usdhc_set_io()
250 		ios->bus_width,  in imx_usdhc_set_io()
251 		ios->clock,  in imx_usdhc_set_io()
252 		ios->power_mode == SDHC_POWER_ON ? "ON" : "OFF",  in imx_usdhc_set_io()
253 		ios->signal_voltage == SD_VOL_1_8_V ? "1.8V" : "3.3V"  in imx_usdhc_set_io()
256 	if (clock_control_get_rate(cfg->clock_dev,  in imx_usdhc_set_io()
257 				cfg->clock_subsys,  in imx_usdhc_set_io()
259 		return -EINVAL;  in imx_usdhc_set_io()
262 	if (ios->clock && (ios->clock > data->props.f_max || ios->clock < data->props.f_min)) {  in imx_usdhc_set_io()
263 		return -EINVAL;  in imx_usdhc_set_io()
267 	if (host_io->clock != ios->clock) {  in imx_usdhc_set_io()
268 		if (ios->clock != 0) {  in imx_usdhc_set_io()
270 			bus_clk = USDHC_SetSdClock(cfg->base, src_clk_hz, ios->clock);  in imx_usdhc_set_io()
273 				return -ENOTSUP;  in imx_usdhc_set_io()
276 		host_io->clock = ios->clock;  in imx_usdhc_set_io()
281 	if (host_io->bus_width != ios->bus_width) {  in imx_usdhc_set_io()
282 		switch (ios->bus_width) {  in imx_usdhc_set_io()
284 			USDHC_SetDataBusWidth(cfg->base, kUSDHC_DataBusWidth1Bit);  in imx_usdhc_set_io()
287 			USDHC_SetDataBusWidth(cfg->base, kUSDHC_DataBusWidth4Bit);  in imx_usdhc_set_io()
290 			USDHC_SetDataBusWidth(cfg->base, kUSDHC_DataBusWidth8Bit);  in imx_usdhc_set_io()
293 			return -ENOTSUP;  in imx_usdhc_set_io()
295 		host_io->bus_width = ios->bus_width;  in imx_usdhc_set_io()
299 	if (ios->signal_voltage != host_io->signal_voltage) {  in imx_usdhc_set_io()
300 		switch (ios->signal_voltage) {  in imx_usdhc_set_io()
303 			UDSHC_SelectVoltage(cfg->base, false);  in imx_usdhc_set_io()
317 			UDSHC_SelectVoltage(cfg->base, true);  in imx_usdhc_set_io()
318 			/* Wait 10 ms- clock will be gated during this period */  in imx_usdhc_set_io()
321 			USDHC_ForceClockOn(cfg->base, true);  in imx_usdhc_set_io()
325 			USDHC_ForceClockOn(cfg->base, false);  in imx_usdhc_set_io()
328 			return -ENOTSUP;  in imx_usdhc_set_io()
331 		host_io->signal_voltage = ios->signal_voltage;  in imx_usdhc_set_io()
335 	if ((host_io->power_mode != ios->power_mode) && (cfg->pwr_gpio.port)) {  in imx_usdhc_set_io()
336 		if (host_io->power_mode == SDHC_POWER_ON) {  in imx_usdhc_set_io()
338 			USDHC_SetCardActive(cfg->base, 0xFFFF);  in imx_usdhc_set_io()
340 		if (cfg->pwr_gpio.port) {  in imx_usdhc_set_io()
341 			if (ios->power_mode == SDHC_POWER_OFF) {  in imx_usdhc_set_io()
342 				gpio_pin_set_dt(&cfg->pwr_gpio, 0);  in imx_usdhc_set_io()
343 			} else if (ios->power_mode == SDHC_POWER_ON) {  in imx_usdhc_set_io()
344 				gpio_pin_set_dt(&cfg->pwr_gpio, 1);  in imx_usdhc_set_io()
347 		host_io->power_mode = ios->power_mode;  in imx_usdhc_set_io()
351 	if (host_io->timing != ios->timing) {  in imx_usdhc_set_io()
352 		switch (ios->timing) {  in imx_usdhc_set_io()
358 			pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_SLOW);  in imx_usdhc_set_io()
361 			pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_MED);  in imx_usdhc_set_io()
365 			USDHC_EnableHS400Mode(cfg->base, true);  in imx_usdhc_set_io()
366 			USDHC_EnableDDRMode(cfg->base, true, 0U);  in imx_usdhc_set_io()
367 			USDHC_ConfigStrobeDLL(cfg->base, 7U, 4U);  in imx_usdhc_set_io()
368 			USDHC_EnableStrobeDLL(cfg->base, true);  in imx_usdhc_set_io()
371 			return -ENOTSUP;  in imx_usdhc_set_io()
377 			pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_FAST);  in imx_usdhc_set_io()
380 			return -ENOTSUP;  in imx_usdhc_set_io()
382 		host_io->timing = ios->timing;  in imx_usdhc_set_io()
394 	const struct usdhc_config *cfg = dev->config;  in imx_usdhc_transfer()
395 	struct usdhc_data *dev_data = dev->data;  in imx_usdhc_transfer()
401 	dma_config.admaTable = dev_data->usdhc_dma_descriptor;  in imx_usdhc_transfer()
402 	dma_config.admaTableWords = dev_data->dma_descriptor_len;  in imx_usdhc_transfer()
410 	dev_data->transfer_status = 0U;  in imx_usdhc_transfer()
412 	k_sem_reset(&dev_data->transfer_sem);  in imx_usdhc_transfer()
414 	error = USDHC_TransferNonBlocking(cfg->base, &dev_data->transfer_handle,  in imx_usdhc_transfer()
415 			&dma_config, request->transfer);  in imx_usdhc_transfer()
417 	error = USDHC_TransferNonBlocking(cfg->base, &dev_data->transfer_handle,  in imx_usdhc_transfer()
418 			NULL, request->transfer);  in imx_usdhc_transfer()
421 		return -EAGAIN;  in imx_usdhc_transfer()
423 		return -EIO;  in imx_usdhc_transfer()
426 	while ((dev_data->transfer_status & (TRANSFER_CMD_FLAGS | TRANSFER_DATA_FLAGS)) == 0) {  in imx_usdhc_transfer()
427 		if (k_sem_take(&dev_data->transfer_sem, request->command_timeout)) {  in imx_usdhc_transfer()
428 			return -ETIMEDOUT;  in imx_usdhc_transfer()
431 	if (dev_data->transfer_status & TRANSFER_CMD_FAILED) {  in imx_usdhc_transfer()
432 		return -EIO;  in imx_usdhc_transfer()
435 	if (request->transfer->data) {  in imx_usdhc_transfer()
436 		while ((dev_data->transfer_status & TRANSFER_DATA_FLAGS) == 0) {  in imx_usdhc_transfer()
437 			if (k_sem_take(&dev_data->transfer_sem, request->data_timeout)) {  in imx_usdhc_transfer()
438 				return -ETIMEDOUT;  in imx_usdhc_transfer()
441 		if (dev_data->transfer_status & TRANSFER_DATA_FAILED) {  in imx_usdhc_transfer()
442 			return -EIO;  in imx_usdhc_transfer()
475 	const struct usdhc_config *cfg = dev->config;  in imx_usdhc_card_busy()
477 	return (USDHC_GetPresentStatusFlags(cfg->base)  in imx_usdhc_card_busy()
490 	const struct usdhc_config *cfg = dev->config;  in imx_usdhc_execute_tuning()
491 	struct usdhc_data *dev_data = dev->data;  in imx_usdhc_execute_tuning()
499 	if ((dev_data->host_io.timing == SDHC_TIMING_HS200) ||  in imx_usdhc_execute_tuning()
500 		       (dev_data->host_io.timing == SDHC_TIMING_HS400)) {  in imx_usdhc_execute_tuning()
509 	if (dev_data->host_io.bus_width == SDHC_BUS_WIDTH8BIT) {  in imx_usdhc_execute_tuning()
510 		data.blockSize = sizeof(dev_data->usdhc_rx_dummy);  in imx_usdhc_execute_tuning()
512 		data.blockSize = sizeof(dev_data->usdhc_rx_dummy) / 2;  in imx_usdhc_execute_tuning()
515 	data.rxData = (uint32_t *)dev_data->usdhc_rx_dummy;  in imx_usdhc_execute_tuning()
522 	USDHC_Reset(cfg->base, kUSDHC_ResetTuning, 100U);  in imx_usdhc_execute_tuning()
524 	USDHC_EnableStandardTuning(cfg->base, IMX_USDHC_STANDARD_TUNING_START,  in imx_usdhc_execute_tuning()
526 	USDHC_ForceClockOn(cfg->base, true);  in imx_usdhc_execute_tuning()
532 	USDHC_SetStandardTuningCounter(cfg->base, IMX_USDHC_STANDARD_TUNING_COUNTER);  in imx_usdhc_execute_tuning()
534 	USDHC_EnableStandardTuning(cfg->base, IMX_USDHC_STANDARD_TUNING_START,  in imx_usdhc_execute_tuning()
550 		if (USDHC_GetExecuteStdTuningStatus(cfg->base) != 0) {  in imx_usdhc_execute_tuning()
554 		if ((USDHC_CheckTuningError(cfg->base) != 0U) && retry_tuning) {  in imx_usdhc_execute_tuning()
557 			USDHC_EnableStandardTuning(cfg->base,  in imx_usdhc_execute_tuning()
560 			USDHC_SetTuningDelay(cfg->base,  in imx_usdhc_execute_tuning()
568 	if (USDHC_CheckStdTuningResult(cfg->base) == 0) {  in imx_usdhc_execute_tuning()
569 		return -EIO;  in imx_usdhc_execute_tuning()
571 	USDHC_ForceClockOn(cfg->base, false);  in imx_usdhc_execute_tuning()
574 	USDHC_EnableAutoTuning(cfg->base, true);  in imx_usdhc_execute_tuning()
584 	const struct usdhc_config *cfg = dev->config;  in imx_usdhc_request()
585 	struct usdhc_data *dev_data = dev->data;  in imx_usdhc_request()
592 	int retries = (int)cmd->retries;  in imx_usdhc_request()
594 	host_cmd.index = cmd->opcode;  in imx_usdhc_request()
595 	host_cmd.argument = cmd->arg;  in imx_usdhc_request()
596 	/* Mask out part of response type field used for SPI commands */  in imx_usdhc_request()
597 	host_cmd.responseType = (cmd->response_type & SDHC_NATIVE_RESPONSE_MASK);  in imx_usdhc_request()
599 	if (cmd->timeout_ms == SDHC_TIMEOUT_FOREVER) {  in imx_usdhc_request()
602 		request.command_timeout = K_MSEC(cmd->timeout_ms);  in imx_usdhc_request()
606 		host_data.blockSize = data->block_size;  in imx_usdhc_request()
607 		host_data.blockCount = data->blocks;  in imx_usdhc_request()
612 		switch (cmd->opcode) {  in imx_usdhc_request()
615 			host_data.txData = data->data;  in imx_usdhc_request()
618 			if (dev_data->host_io.timing == SDHC_TIMING_SDR104) {  in imx_usdhc_request()
625 			host_data.txData = data->data;  in imx_usdhc_request()
629 			host_data.rxData = data->data;  in imx_usdhc_request()
632 			if (dev_data->host_io.timing == SDHC_TIMING_SDR104) {  in imx_usdhc_request()
639 			host_data.rxData = data->data;  in imx_usdhc_request()
646 			host_data.rxData = data->data;  in imx_usdhc_request()
649 			return -ENOTSUP;  in imx_usdhc_request()
653 		if (data->timeout_ms == SDHC_TIMEOUT_FOREVER) {  in imx_usdhc_request()
656 			request.data_timeout = K_MSEC(data->timeout_ms);  in imx_usdhc_request()
665 	if (k_mutex_lock(&dev_data->access_mutex, request.command_timeout) != 0) {  in imx_usdhc_request()
666 		return -EBUSY;  in imx_usdhc_request()
677 			USDHC_DisableInterruptSignal(cfg->base, kUSDHC_CommandFlag |  in imx_usdhc_request()
679 			USDHC_ClearInterruptStatusFlags(cfg->base, kUSDHC_CommandFlag |  in imx_usdhc_request()
690 				busy_timeout -= 125;  in imx_usdhc_request()
694 				k_mutex_unlock(&dev_data->access_mutex);  in imx_usdhc_request()
695 				return -ETIMEDOUT;  in imx_usdhc_request()
698 		if (ret == -EAGAIN) {  in imx_usdhc_request()
700 			if (dev_data->host_io.timing == SDHC_TIMING_SDR50 ||  in imx_usdhc_request()
701 				dev_data->host_io.timing == SDHC_TIMING_SDR104 ||  in imx_usdhc_request()
702 				dev_data->host_io.timing == SDHC_TIMING_HS200 ||  in imx_usdhc_request()
703 				dev_data->host_io.timing == SDHC_TIMING_HS400) {  in imx_usdhc_request()
709 					k_mutex_unlock(&dev_data->access_mutex);  in imx_usdhc_request()
716 			retries--;  in imx_usdhc_request()
723 	k_mutex_unlock(&dev_data->access_mutex);  in imx_usdhc_request()
725 	memcpy(cmd->response, host_cmd.response, sizeof(cmd->response));  in imx_usdhc_request()
728 		data->bytes_xfered = dev_data->transfer_handle.transferredWords;  in imx_usdhc_request()
738 	const struct usdhc_config *cfg = dev->config;  in imx_usdhc_get_card_present()
739 	struct usdhc_data *data = dev->data;  in imx_usdhc_get_card_present()
741 	if (cfg->detect_dat3) {  in imx_usdhc_get_card_present()
746 		if (!data->card_present) {  in imx_usdhc_get_card_present()
749 			USDHC_CardDetectByData3(cfg->base, true);  in imx_usdhc_get_card_present()
752 			data->card_present = USDHC_DetectCardInsert(cfg->base);  in imx_usdhc_get_card_present()
755 			USDHC_CardDetectByData3(cfg->base, false);  in imx_usdhc_get_card_present()
757 	} else if (cfg->detect_gpio.port) {  in imx_usdhc_get_card_present()
758 		data->card_present = gpio_pin_get_dt(&cfg->detect_gpio) > 0;  in imx_usdhc_get_card_present()
761 		data->card_present = true;  in imx_usdhc_get_card_present()
763 	return ((int)data->card_present);  in imx_usdhc_get_card_present()
772 	struct usdhc_data *data = dev->data;  in imx_usdhc_get_host_props()
774 	memcpy(props, &data->props, sizeof(struct sdhc_host_props));  in imx_usdhc_get_host_props()
780 	const struct usdhc_config *cfg = dev->config;  in imx_usdhc_isr()
781 	struct usdhc_data *data = dev->data;  in imx_usdhc_isr()
783 	USDHC_TransferHandleIRQ(cfg->base, &data->transfer_handle);  in imx_usdhc_isr()
792 	const struct usdhc_config *cfg = dev->config;  in imx_usdhc_init()
793 	struct usdhc_data *data = dev->data;  in imx_usdhc_init()
800 	if (!device_is_ready(cfg->clock_dev)) {  in imx_usdhc_init()
802 		return -ENODEV;  in imx_usdhc_init()
805 	ret = pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_DEFAULT);  in imx_usdhc_init()
809 	USDHC_TransferCreateHandle(cfg->base, &data->transfer_handle,  in imx_usdhc_init()
811 	cfg->irq_config_func(dev);  in imx_usdhc_init()
814 	host_config.dataTimeout = cfg->data_timeout;  in imx_usdhc_init()
816 	host_config.readWatermarkLevel = cfg->read_watermark;  in imx_usdhc_init()
817 	host_config.writeWatermarkLevel = cfg->write_watermark;  in imx_usdhc_init()
818 	USDHC_Init(cfg->base, &host_config);  in imx_usdhc_init()
822 	if (cfg->pwr_gpio.port) {  in imx_usdhc_init()
823 		ret = gpio_pin_configure_dt(&cfg->pwr_gpio, GPIO_OUTPUT_INACTIVE);  in imx_usdhc_init()
831 	if (cfg->detect_gpio.port) {  in imx_usdhc_init()
832 		ret = gpio_pin_configure_dt(&cfg->detect_gpio, GPIO_INPUT);  in imx_usdhc_init()
837 	k_mutex_init(&data->access_mutex);  in imx_usdhc_init()
838 	memset(&data->host_io, 0, sizeof(data->host_io));  in imx_usdhc_init()
839 	return k_sem_init(&data->transfer_sem, 0, 1);  in imx_usdhc_init()