1/* 2 * Copyright (c) 2023 ITE Corporation. All Rights Reserved. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <ite/it8xxx2.dtsi> 8 9/ { 10 soc { 11 sram0: memory@80100000 { 12 compatible = "mmio-sram"; 13 reg = <0x80100000 DT_SIZE_K(256)>; 14 }; 15 16 intc: interrupt-controller@f03f00 { 17 compatible = "ite,it8xxx2-intc-v2"; 18 #address-cells = <0>; 19 #interrupt-cells = <2>; 20 interrupt-controller; 21 reg = <0x00f03f00 0x0100>; 22 }; 23 24 twd0: watchdog@f01f80 { 25 compatible = "ite,it8xxx2-watchdog"; 26 reg = <0x00f01f80 0x000f>; 27 interrupts = <IT8XXX2_IRQ_TIMER1 IRQ_TYPE_EDGE_RISING /* Warning timer */ 28 IT8XXX2_IRQ_TIMER2 IRQ_TYPE_EDGE_RISING>; /* One shot timer */ 29 interrupt-parent = <&intc>; 30 }; 31 32 gpiogcr: gpio-gcr@f03e00 { 33 compatible = "ite,it8xxx2-gpiogcr"; 34 reg = <0x00f03e00 0x2f>; 35 }; 36 37 gpioa: gpio@f01601 { 38 compatible = "ite,it8xxx2-gpio-v2"; 39 reg = <0x00f01601 1 /* GPDR (set) */ 40 0x00f01618 1 /* GPDMR (get) */ 41 0x00f01630 1 /* GPOTR */ 42 0x00f01648 1 /* P18SCR */ 43 0x00f01660 8>; /* GPCR */ 44 ngpios = <8>; 45 gpio-controller; 46 interrupts = <IT8XXX2_IRQ_WU91 IRQ_TYPE_LEVEL_HIGH 47 IT8XXX2_IRQ_WU92 IRQ_TYPE_LEVEL_HIGH 48 IT8XXX2_IRQ_WU93 IRQ_TYPE_LEVEL_HIGH 49 IT8XXX2_IRQ_WU80 IRQ_TYPE_LEVEL_HIGH 50 IT8XXX2_IRQ_WU81 IRQ_TYPE_LEVEL_HIGH 51 IT8XXX2_IRQ_WU82 IRQ_TYPE_LEVEL_HIGH 52 IT8XXX2_IRQ_WU83 IRQ_TYPE_LEVEL_HIGH 53 IT8XXX2_IRQ_WU100 IRQ_TYPE_LEVEL_HIGH>; 54 interrupt-parent = <&intc>; 55 wuc-base = <0xf01b20 0xf01b20 0xf01b20 0xf01b1c 56 0xf01b1c 0xf01b1c 0xf01b1c 0xf01b24>; 57 wuc-mask = <BIT(3) BIT(4) BIT(5) BIT(0) 58 BIT(1) BIT(2) BIT(3) BIT(4) >; 59 has-volt-sel = <1 1 1 1 1 1 1 1>; 60 #gpio-cells = <2>; 61 }; 62 63 gpiob: gpio@f01602 { 64 compatible = "ite,it8xxx2-gpio-v2"; 65 reg = <0x00f01602 1 /* GPDR (set) */ 66 0x00f01619 1 /* GPDMR (get) */ 67 0x00f01631 1 /* GPOTR */ 68 0x00f01649 1 /* P18SCR */ 69 0x00f01668 8>; /* GPCR */ 70 ngpios = <7>; 71 gpio-controller; 72 interrupts = <IT8XXX2_IRQ_WU101 IRQ_TYPE_LEVEL_HIGH 73 IT8XXX2_IRQ_WU102 IRQ_TYPE_LEVEL_HIGH 74 IT8XXX2_IRQ_WU84 IRQ_TYPE_LEVEL_HIGH 75 IT8XXX2_IRQ_WU103 IRQ_TYPE_LEVEL_HIGH 76 IT8XXX2_IRQ_WU94 IRQ_TYPE_LEVEL_HIGH 77 IT8XXX2_IRQ_WU104 IRQ_TYPE_LEVEL_HIGH 78 IT8XXX2_IRQ_WU105 IRQ_TYPE_LEVEL_HIGH 79 NO_FUNC 0>; 80 interrupt-parent = <&intc>; 81 wuc-base = <0xf01b24 0xf01b24 0xf01b1c 0xf01b24 82 0xf01b20 0xf01b28 0xf01b28 NO_FUNC >; 83 wuc-mask = <BIT(5) BIT(6) BIT(4) BIT(7) 84 BIT(6) BIT(0) BIT(1) 0 >; 85 has-volt-sel = <1 1 1 1 1 1 1 0>; 86 #gpio-cells = <2>; 87 }; 88 89 gpioc: gpio@f01603 { 90 compatible = "ite,it8xxx2-gpio-v2"; 91 reg = <0x00f01603 1 /* GPDR (set) */ 92 0x00f0161a 1 /* GPDMR (get) */ 93 0x00f01632 1 /* GPOTR */ 94 0x00f0164a 1 /* P18SCR */ 95 0x00f01670 8>; /* GPCR */ 96 ngpios = <8>; 97 gpio-controller; 98 interrupts = <IT8XXX2_IRQ_WU85 IRQ_TYPE_LEVEL_HIGH 99 IT8XXX2_IRQ_WU107 IRQ_TYPE_LEVEL_HIGH 100 IT8XXX2_IRQ_WU95 IRQ_TYPE_LEVEL_HIGH 101 IT8XXX2_IRQ_WU108 IRQ_TYPE_LEVEL_HIGH 102 IT8XXX2_IRQ_WU22 IRQ_TYPE_LEVEL_HIGH 103 IT8XXX2_IRQ_WU109 IRQ_TYPE_LEVEL_HIGH 104 IT8XXX2_IRQ_WU23 IRQ_TYPE_LEVEL_HIGH 105 IT8XXX2_IRQ_WU86 IRQ_TYPE_LEVEL_HIGH>; 106 interrupt-parent = <&intc>; 107 wuc-base = <0xf01b1c 0xf01b28 0xf01b20 0xf01b28 108 0xf01b04 0xf01b28 0xf01b04 0xf01b1c>; 109 wuc-mask = <BIT(5) BIT(3) BIT(7) BIT(4) 110 BIT(2) BIT(5) BIT(3) BIT(6) >; 111 has-volt-sel = <1 1 1 1 1 1 1 1>; 112 #gpio-cells = <2>; 113 }; 114 115 gpiod: gpio@f01604 { 116 compatible = "ite,it8xxx2-gpio-v2"; 117 reg = <0x00f01604 1 /* GPDR (set) */ 118 0x00f0161b 1 /* GPDMR (get) */ 119 0x00f01633 1 /* GPOTR */ 120 0x00f0164b 1 /* P18SCR */ 121 0x00f01678 8>; /* GPCR */ 122 ngpios = <8>; 123 gpio-controller; 124 interrupts = <IT8XXX2_IRQ_WU20 IRQ_TYPE_LEVEL_HIGH 125 IT8XXX2_IRQ_WU21 IRQ_TYPE_LEVEL_HIGH 126 IT8XXX2_IRQ_WU24 IRQ_TYPE_LEVEL_HIGH 127 IT8XXX2_IRQ_WU110 IRQ_TYPE_LEVEL_HIGH 128 IT8XXX2_IRQ_WU111 IRQ_TYPE_LEVEL_HIGH 129 IT8XXX2_IRQ_WU112 IRQ_TYPE_LEVEL_HIGH 130 IT8XXX2_IRQ_WU113 IRQ_TYPE_LEVEL_HIGH 131 IT8XXX2_IRQ_WU87 IRQ_TYPE_LEVEL_HIGH>; 132 interrupt-parent = <&intc>; 133 wuc-base = <0xf01b04 0xf01b04 0xf01b04 0xf01b28 134 0xf01b28 0xf01b2c 0xf01b2c 0xf01b1c>; 135 wuc-mask = <BIT(0) BIT(1) BIT(4) BIT(6) 136 BIT(7) BIT(0) BIT(1) BIT(7) >; 137 has-volt-sel = <1 1 1 1 1 1 1 1>; 138 #gpio-cells = <2>; 139 }; 140 141 gpioe: gpio@f01605 { 142 compatible = "ite,it8xxx2-gpio-v2"; 143 reg = <0x00f01605 1 /* GPDR (set) */ 144 0x00f0161c 1 /* GPDMR (get) */ 145 0x00f01634 1 /* GPOTR */ 146 0x00f0164c 1 /* P18SCR */ 147 0x00f01680 8>; /* GPCR */ 148 ngpios = <8>; 149 gpio-controller; 150 interrupts = <IT8XXX2_IRQ_WU70 IRQ_TYPE_LEVEL_HIGH 151 IT8XXX2_IRQ_WU71 IRQ_TYPE_LEVEL_HIGH 152 IT8XXX2_IRQ_WU72 IRQ_TYPE_LEVEL_HIGH 153 IT8XXX2_IRQ_WU73 IRQ_TYPE_LEVEL_HIGH 154 IT8XXX2_IRQ_WU114 IRQ_TYPE_LEVEL_HIGH 155 IT8XXX2_IRQ_WU40 IRQ_TYPE_LEVEL_HIGH 156 IT8XXX2_IRQ_WU45 IRQ_TYPE_LEVEL_HIGH 157 IT8XXX2_IRQ_WU46 IRQ_TYPE_LEVEL_HIGH>; 158 interrupt-parent = <&intc>; 159 wuc-base = <0xf01b18 0xf01b18 0xf01b18 0xf01b18 160 0xf01b2c 0xf01b0c 0xf01b0c 0xf01b0c>; 161 wuc-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 162 BIT(2) BIT(0) BIT(5) BIT(6) >; 163 has-volt-sel = <1 1 1 1 1 1 1 1>; 164 #gpio-cells = <2>; 165 }; 166 167 gpiof: gpio@f01606 { 168 compatible = "ite,it8xxx2-gpio-v2"; 169 reg = <0x00f01606 1 /* GPDR (set) */ 170 0x00f0161d 1 /* GPDMR (get) */ 171 0x00f01635 1 /* GPOTR */ 172 0x00f0164d 1 /* P18SCR */ 173 0x00f01688 8>; /* GPCR */ 174 ngpios = <8>; 175 gpio-controller; 176 interrupts = <IT8XXX2_IRQ_WU96 IRQ_TYPE_LEVEL_HIGH 177 IT8XXX2_IRQ_WU97 IRQ_TYPE_LEVEL_HIGH 178 IT8XXX2_IRQ_WU98 IRQ_TYPE_LEVEL_HIGH 179 IT8XXX2_IRQ_WU99 IRQ_TYPE_LEVEL_HIGH 180 IT8XXX2_IRQ_WU64 IRQ_TYPE_LEVEL_HIGH 181 IT8XXX2_IRQ_WU65 IRQ_TYPE_LEVEL_HIGH 182 IT8XXX2_IRQ_WU66 IRQ_TYPE_LEVEL_HIGH 183 IT8XXX2_IRQ_WU67 IRQ_TYPE_LEVEL_HIGH>; 184 interrupt-parent = <&intc>; 185 wuc-base = <0xf01b24 0xf01b24 0xf01b24 0xf01b24 186 0xf01b14 0xf01b14 0xf01b14 0xf01b14>; 187 wuc-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 188 BIT(4) BIT(5) BIT(6) BIT(7) >; 189 has-volt-sel = <1 1 1 1 1 1 1 1>; 190 #gpio-cells = <2>; 191 }; 192 193 gpiog: gpio@f01607 { 194 compatible = "ite,it8xxx2-gpio-v2"; 195 reg = <0x00f01607 1 /* GPDR (set) */ 196 0x00f0161e 1 /* GPDMR (get) */ 197 0x00f01636 1 /* GPOTR */ 198 0x00f0164e 1 /* P18SCR */ 199 0x00f01690 8>; /* GPCR */ 200 ngpios = <8>; 201 gpio-controller; 202 interrupts = <IT8XXX2_IRQ_WU115 IRQ_TYPE_LEVEL_HIGH 203 IT8XXX2_IRQ_WU116 IRQ_TYPE_LEVEL_HIGH 204 IT8XXX2_IRQ_WU117 IRQ_TYPE_LEVEL_HIGH 205 IT8XXX2_IRQ_WU123 IRQ_TYPE_LEVEL_HIGH 206 IT8XXX2_IRQ_WU124 IRQ_TYPE_LEVEL_HIGH 207 IT8XXX2_IRQ_WU125 IRQ_TYPE_LEVEL_HIGH 208 IT8XXX2_IRQ_WU118 IRQ_TYPE_LEVEL_HIGH 209 IT8XXX2_IRQ_WU126 IRQ_TYPE_LEVEL_HIGH>; 210 interrupt-parent = <&intc>; 211 wuc-base = <0xf01b2c 0xf01b2c 0xf01b2c 0xf01b30 212 0xf01b30 0xf01b30 0xf01b2c 0xf01b30>; 213 wuc-mask = <BIT(3) BIT(4) BIT(5) BIT(3) 214 BIT(4) BIT(5) BIT(6) BIT(6) >; 215 has-volt-sel = <1 1 1 0 0 0 1 0>; 216 #gpio-cells = <2>; 217 }; 218 219 gpioh: gpio@f01608 { 220 compatible = "ite,it8xxx2-gpio-v2"; 221 reg = <0x00f01608 1 /* GPDR (set) */ 222 0x00f0161f 1 /* GPDMR (get) */ 223 0x00f01637 1 /* GPOTR */ 224 0x00f0164f 1 /* P18SCR */ 225 0x00f01698 8>; /* GPCR */ 226 ngpios = <7>; 227 gpio-controller; 228 interrupts = <IT8XXX2_IRQ_WU60 IRQ_TYPE_LEVEL_HIGH 229 IT8XXX2_IRQ_WU61 IRQ_TYPE_LEVEL_HIGH 230 IT8XXX2_IRQ_WU62 IRQ_TYPE_LEVEL_HIGH 231 IT8XXX2_IRQ_WU63 IRQ_TYPE_LEVEL_HIGH 232 IT8XXX2_IRQ_WU88 IRQ_TYPE_LEVEL_HIGH 233 IT8XXX2_IRQ_WU89 IRQ_TYPE_LEVEL_HIGH 234 IT8XXX2_IRQ_WU90 IRQ_TYPE_LEVEL_HIGH 235 NO_FUNC 0>; 236 interrupt-parent = <&intc>; 237 wuc-base = <0xf01b14 0xf01b14 0xf01b14 0xf01b14 238 0xf01b20 0xf01b20 0xf01b20 NO_FUNC >; 239 wuc-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 240 BIT(0) BIT(1) BIT(2) 0 >; 241 has-volt-sel = <1 1 1 1 1 1 1 0>; 242 #gpio-cells = <2>; 243 }; 244 245 gpioi: gpio@f01609 { 246 compatible = "ite,it8xxx2-gpio-v2"; 247 reg = <0x00f01609 1 /* GPDR (set) */ 248 0x00f01620 1 /* GPDMR (get) */ 249 0x00f01638 1 /* GPOTR */ 250 0x00f01650 1 /* P18SCR */ 251 0x00f016a0 8>; /* GPCR */ 252 ngpios = <8>; 253 gpio-controller; 254 interrupts = <IT8XXX2_IRQ_WU119 IRQ_TYPE_LEVEL_HIGH 255 IT8XXX2_IRQ_WU120 IRQ_TYPE_LEVEL_HIGH 256 IT8XXX2_IRQ_WU121 IRQ_TYPE_LEVEL_HIGH 257 IT8XXX2_IRQ_WU122 IRQ_TYPE_LEVEL_HIGH 258 IT8XXX2_IRQ_WU74 IRQ_TYPE_LEVEL_HIGH 259 IT8XXX2_IRQ_WU75 IRQ_TYPE_LEVEL_HIGH 260 IT8XXX2_IRQ_WU76 IRQ_TYPE_LEVEL_HIGH 261 IT8XXX2_IRQ_WU77 IRQ_TYPE_LEVEL_HIGH>; 262 interrupt-parent = <&intc>; 263 wuc-base = <0xf01b2c 0xf01b30 0xf01b30 0xf01b30 264 0xf01b18 0xf01b18 0xf01b18 0xf01b18>; 265 wuc-mask = <BIT(7) BIT(0) BIT(1) BIT(2) 266 BIT(4) BIT(5) BIT(6) BIT(7) >; 267 has-volt-sel = <1 1 1 1 1 1 1 1>; 268 #gpio-cells = <2>; 269 }; 270 271 gpioj: gpio@f0160a { 272 compatible = "ite,it8xxx2-gpio-v2"; 273 reg = <0x00f0160a 1 /* GPDR (set) */ 274 0x00f01621 1 /* GPDMR (get) */ 275 0x00f01639 1 /* GPOTR */ 276 0x00f01651 1 /* P18SCR */ 277 0x00f016a8 8>; /* GPCR */ 278 ngpios = <6>; 279 gpio-controller; 280 interrupts = <IT8XXX2_IRQ_WU128 IRQ_TYPE_LEVEL_HIGH 281 IT8XXX2_IRQ_WU129 IRQ_TYPE_LEVEL_HIGH 282 IT8XXX2_IRQ_WU130 IRQ_TYPE_LEVEL_HIGH 283 IT8XXX2_IRQ_WU131 IRQ_TYPE_LEVEL_HIGH 284 IT8XXX2_IRQ_WU132 IRQ_TYPE_LEVEL_HIGH 285 IT8XXX2_IRQ_WU133 IRQ_TYPE_LEVEL_HIGH 286 NO_FUNC 0 287 NO_FUNC 0>; 288 interrupt-parent = <&intc>; 289 wuc-base = <0xf01b34 0xf01b34 0xf01b34 0xf01b34 290 0xf01b34 0xf01b34 NO_FUNC NO_FUNC >; 291 wuc-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 292 BIT(4) BIT(5) 0 0 >; 293 has-volt-sel = <1 1 1 1 1 1 0 0>; 294 #gpio-cells = <2>; 295 }; 296 297 gpiok: gpio@f0160b { 298 compatible = "ite,it8xxx2-gpio-v2"; 299 reg = <0x00f0160b 1 /* GPDR (set) */ 300 0x00f01622 1 /* GPDMR (get) */ 301 0x00f0163a 1 /* GPOTR */ 302 0x00f01652 1 /* P18SCR */ 303 0x00f016b0 8>; /* GPCR */ 304 ngpios = <8>; 305 gpio-controller; 306 interrupts = <IT8XXX2_IRQ_WU50 IRQ_TYPE_LEVEL_HIGH 307 IT8XXX2_IRQ_WU51 IRQ_TYPE_LEVEL_HIGH 308 IT8XXX2_IRQ_WU52 IRQ_TYPE_LEVEL_HIGH 309 IT8XXX2_IRQ_WU53 IRQ_TYPE_LEVEL_HIGH 310 IT8XXX2_IRQ_WU54 IRQ_TYPE_LEVEL_HIGH 311 IT8XXX2_IRQ_WU55 IRQ_TYPE_LEVEL_HIGH 312 IT8XXX2_IRQ_WU56 IRQ_TYPE_LEVEL_HIGH 313 IT8XXX2_IRQ_WU57 IRQ_TYPE_LEVEL_HIGH>; 314 interrupt-parent = <&intc>; 315 wuc-base = <0xf01b10 0xf01b10 0xf01b10 0xf01b10 316 0xf01b10 0xf01b10 0xf01b10 0xf01b10>; 317 wuc-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 318 BIT(4) BIT(5) BIT(6) BIT(7) >; 319 has-volt-sel = <1 1 1 1 1 1 1 1>; 320 #gpio-cells = <2>; 321 }; 322 323 gpiol: gpio@f0160c { 324 compatible = "ite,it8xxx2-gpio-v2"; 325 reg = <0x00f0160c 1 /* GPDR (set) */ 326 0x00f01623 1 /* GPDMR (get) */ 327 0x00f0163b 1 /* GPOTR */ 328 0x00f01653 1 /* P18SCR */ 329 0x00f016b8 8>; /* GPCR */ 330 ngpios = <8>; 331 gpio-controller; 332 interrupts = <IT8XXX2_IRQ_WU136 IRQ_TYPE_LEVEL_HIGH 333 IT8XXX2_IRQ_WU137 IRQ_TYPE_LEVEL_HIGH 334 IT8XXX2_IRQ_WU138 IRQ_TYPE_LEVEL_HIGH 335 IT8XXX2_IRQ_WU139 IRQ_TYPE_LEVEL_HIGH 336 IT8XXX2_IRQ_WU140 IRQ_TYPE_LEVEL_HIGH 337 IT8XXX2_IRQ_WU141 IRQ_TYPE_LEVEL_HIGH 338 IT8XXX2_IRQ_WU142 IRQ_TYPE_LEVEL_HIGH 339 IT8XXX2_IRQ_WU143 IRQ_TYPE_LEVEL_HIGH>; 340 interrupt-parent = <&intc>; 341 wuc-base = <0xf01b38 0xf01b38 0xf01b38 0xf01b38 342 0xf01b38 0xf01b38 0xf01b38 0xf01b38>; 343 wuc-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 344 BIT(4) BIT(5) BIT(6) BIT(7) >; 345 has-volt-sel = <1 1 1 1 1 1 1 1>; 346 #gpio-cells = <2>; 347 }; 348 349 gpiom: gpio@f0160d { 350 compatible = "ite,it8xxx2-gpio-v2"; 351 reg = <0x00f0160d 1 /* GPDR (set) */ 352 0x00f01624 1 /* GPDMR (get) */ 353 0x00f0163c 1 /* GPOTR */ 354 0x00f01654 1 /* P18SCR */ 355 0x00f016c0 8>; /* GPCR */ 356 ngpios = <7>; 357 gpio-controller; 358 interrupts = <IT8XXX2_IRQ_WU144 IRQ_TYPE_LEVEL_HIGH 359 IT8XXX2_IRQ_WU145 IRQ_TYPE_LEVEL_HIGH 360 IT8XXX2_IRQ_WU146 IRQ_TYPE_LEVEL_HIGH 361 IT8XXX2_IRQ_WU147 IRQ_TYPE_LEVEL_HIGH 362 IT8XXX2_IRQ_WU148 IRQ_TYPE_LEVEL_HIGH 363 IT8XXX2_IRQ_WU149 IRQ_TYPE_LEVEL_HIGH 364 IT8XXX2_IRQ_WU150 IRQ_TYPE_LEVEL_HIGH 365 NO_FUNC 0>; 366 interrupt-parent = <&intc>; 367 wuc-base = <0xf01b3c 0xf01b3c 0xf01b3c 0xf01b3c 368 0xf01b3c 0xf01b3c 0xf01b3c NO_FUNC >; 369 wuc-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 370 BIT(4) BIT(5) BIT(6) 0 >; 371 has-volt-sel = <1 1 1 1 1 1 1 0>; 372 #gpio-cells = <2>; 373 }; 374 375 gpioksi: gpio@f01d08 { 376 compatible = "ite,it8xxx2-gpio-v2"; 377 reg = <0x00f01d08 1 /* GPDR (set) */ 378 0x00f01d09 1 /* GPDMR (get) */ 379 0x00f01d2c 1 /* GPOTR */ 380 NO_FUNC 1 /* P18SCR */ 381 0x00f01d40 8>; /* GPCR */ 382 ngpios = <8>; 383 gpio-controller; 384 interrupts = <NO_FUNC 0 385 NO_FUNC 0 386 NO_FUNC 0 387 NO_FUNC 0 388 NO_FUNC 0 389 NO_FUNC 0 390 NO_FUNC 0 391 NO_FUNC 0>; 392 interrupt-parent = <&intc>; 393 #gpio-cells = <2>; 394 }; 395 396 gpioksoh: gpio@f01d01 { 397 compatible = "ite,it8xxx2-gpio-v2"; 398 reg = <0x00f01d01 1 /* GPDR (set) */ 399 0x00f01d0c 1 /* GPDMR (get) */ 400 0x00f01d2d 1 /* GPOTR */ 401 NO_FUNC 1 /* P18SCR */ 402 0x00f01d50 8>; /* GPCR */ 403 ngpios = <8>; 404 gpio-controller; 405 interrupts = <NO_FUNC 0 406 NO_FUNC 0 407 NO_FUNC 0 408 NO_FUNC 0 409 NO_FUNC 0 410 NO_FUNC 0 411 NO_FUNC 0 412 NO_FUNC 0>; 413 interrupt-parent = <&intc>; 414 #gpio-cells = <2>; 415 }; 416 417 gpioksol: gpio@f01d00 { 418 compatible = "ite,it8xxx2-gpio-v2"; 419 reg = <0x00f01d00 1 /* GPDR (set) */ 420 0x00f01d0f 1 /* GPDMR (get) */ 421 0x00f01d2e 1 /* GPOTR */ 422 NO_FUNC 1 /* P18SCR */ 423 0x00f01d48 8>; /* GPCR */ 424 ngpios = <8>; 425 gpio-controller; 426 interrupts = <NO_FUNC 0 427 NO_FUNC 0 428 NO_FUNC 0 429 NO_FUNC 0 430 NO_FUNC 0 431 NO_FUNC 0 432 NO_FUNC 0 433 NO_FUNC 0>; 434 interrupt-parent = <&intc>; 435 #gpio-cells = <2>; 436 }; 437 438 pinctrl: pin-controller { 439 compatible = "ite,it8xxx2-pinctrl"; 440 #address-cells = <1>; 441 #size-cells = <1>; 442 status = "okay"; 443 444 pinctrla: pinctrl@f01660 { 445 compatible = "ite,it8xxx2-pinctrl-func"; 446 reg = <0x00f01660 8>; /* GPCR */ 447 func3-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 448 0xf02032 0xf02032 0xf03e10 0xf03e10>; 449 func3-en-mask = <0 0 0 0 450 0x02 0x02 0x10 0x0C >; 451 func4-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 452 NO_FUNC NO_FUNC NO_FUNC NO_FUNC >; 453 func4-en-mask = <0 0 0 0 454 0 0 0 0 >; 455 volt-sel = <0xf01648 0xf01648 0xf01648 0xf01648 456 0xf01648 0xf01648 0xf01648 0xf01648>; 457 volt-sel-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 458 BIT(4) BIT(5) BIT(6) BIT(7) >; 459 #pinmux-cells = <2>; 460 gpio-group; 461 }; 462 463 pinctrlb: pinctrl@f01668 { 464 compatible = "ite,it8xxx2-pinctrl-func"; 465 reg = <0x00f01668 8>; /* GPCR */ 466 func3-gcr = <0xf03e15 0xf03e15 0xf03e16 NO_FUNC 467 NO_FUNC 0xf03e16 NO_FUNC NO_FUNC>; 468 func3-en-mask = <0x01 0x02 0x40 0 469 0 0x40 0 0 >; 470 func4-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 471 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; 472 func4-en-mask = <0 0 0 0 473 0 0 0 0 >; 474 volt-sel = <0xf01649 0xf01649 0xf01649 0xf01649 475 0xf01649 0xf01649 0xf01649 NO_FUNC>; 476 volt-sel-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 477 BIT(4) BIT(5) BIT(6) 0 >; 478 #pinmux-cells = <2>; 479 gpio-group; 480 }; 481 482 pinctrlc: pinctrl@f01670 { 483 compatible = "ite,it8xxx2-pinctrl-func"; 484 reg = <0x00f01670 8>; /* GPCR */ 485 func3-gcr = <NO_FUNC NO_FUNC NO_FUNC 0xf03e10 486 NO_FUNC 0xf03e10 NO_FUNC 0xf03e13>; 487 func3-en-mask = <0 0 0 0x10 488 0 0x10 0 0x02 >; 489 func4-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 490 NO_FUNC NO_FUNC NO_FUNC 0xf03e16>; 491 func4-en-mask = <0 0 0 0 492 0 0 0 0x80 >; 493 volt-sel = <0xf0164a 0xf0164a 0xf0164a 0xf0164a 494 0xf0164a 0xf0164a 0xf0164a 0xf0164a>; 495 volt-sel-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 496 BIT(4) BIT(5) BIT(6) BIT(7) >; 497 #pinmux-cells = <2>; 498 gpio-group; 499 }; 500 501 pinctrld: pinctrl@f01678 { 502 compatible = "ite,it8xxx2-pinctrl-func"; 503 reg = <0x00f01678 8>; /* GPCR */ 504 func3-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 505 NO_FUNC 0xf03e10 NO_FUNC NO_FUNC>; 506 func3-en-mask = <0 0 0 0 507 0 0x02 0 0 >; 508 func4-gcr = <0xf03e16 NO_FUNC NO_FUNC NO_FUNC 509 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; 510 func4-en-mask = <0x80 0 0 0 511 0 0 0 0 >; 512 volt-sel = <0xf0164b 0xf0164b 0xf0164b 0xf0164b 513 0xf0164b 0xf0164b 0xf0164b 0xf0164b>; 514 volt-sel-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 515 BIT(4) BIT(5) BIT(6) BIT(7) >; 516 #pinmux-cells = <2>; 517 gpio-group; 518 }; 519 520 pinctrle: pinctrl@f01680 { 521 compatible = "ite,it8xxx2-pinctrl-func"; 522 reg = <0x00f01680 8>; /* GPCR */ 523 func3-gcr = <0xf02032 0xf03e16 0xf03e16 NO_FUNC 524 NO_FUNC 0xf03e10 NO_FUNC 0xf02032>; 525 func3-en-mask = <0x01 0x20 0x20 0 526 0 0x08 0 0x01 >; 527 func4-gcr = <0xf03e13 NO_FUNC NO_FUNC NO_FUNC 528 NO_FUNC NO_FUNC NO_FUNC NO_FUNC >; 529 func4-en-mask = <0x01 0 0 0 530 0 0 0 0 >; 531 volt-sel = <0xf0164c 0xf0164c 0xf0164c 0xf0164c 532 0xf0164c 0xf0164c 0xf0164c 0xf0164c>; 533 volt-sel-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 534 BIT(4) BIT(5) BIT(6) BIT(7) >; 535 #pinmux-cells = <2>; 536 gpio-group; 537 }; 538 539 pinctrlf: pinctrl@f01688 { 540 compatible = "ite,it8xxx2-pinctrl-func"; 541 reg = <0x00f01688 8>; /* GPCR */ 542 func3-gcr = <0xf03e15 0xf03e15 0xf03e10 0xf03e10 543 NO_FUNC NO_FUNC 0xf03e11 NO_FUNC>; 544 func3-en-mask = <0x04 0x08 0x02 0x02 545 0 0 0x10 0 >; 546 func4-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 547 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; 548 func4-en-mask = <0 0 0 0 549 0 0 0 0 >; 550 volt-sel = <0xf0164d 0xf0164d 0xf0164d 0xf0164d 551 0xf0164d 0xf0164d 0xf0164d 0xf0164d>; 552 volt-sel-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 553 BIT(4) BIT(5) BIT(6) BIT(7) >; 554 #pinmux-cells = <2>; 555 gpio-group; 556 }; 557 558 pinctrlg: pinctrl@f01690 { 559 compatible = "ite,it8xxx2-pinctrl-func"; 560 reg = <0x00f01690 8>; /* GPCR */ 561 func3-gcr = <0xf03e10 0xf03e10 0xf03e10 NO_FUNC 562 NO_FUNC NO_FUNC 0xf03e10 NO_FUNC>; 563 func3-en-mask = <0x20 0x08 0x10 0 564 0 0 0x02 0 >; 565 func4-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 566 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; 567 func4-en-mask = <0 0 0 0 568 0 0 0 0 >; 569 volt-sel = <0xf0164e 0xf0164e 0xf0164e NO_FUNC 570 NO_FUNC NO_FUNC 0xf0164e NO_FUNC >; 571 volt-sel-mask = <BIT(0) BIT(1) BIT(2) 0 572 0 0 BIT(6) 0 >; 573 #pinmux-cells = <2>; 574 gpio-group; 575 }; 576 577 pinctrlh: pinctrl@f01698 { 578 compatible = "ite,it8xxx2-pinctrl-func"; 579 reg = <0x00f01698 8>; /* GPCR */ 580 func3-gcr = <NO_FUNC 0xf03e11 0xf03e11 NO_FUNC 581 NO_FUNC 0 0 NO_FUNC>; 582 func3-en-mask = <0 0x20 0x20 0 583 0 0 0 0 >; 584 func4-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 585 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; 586 func4-en-mask = <0 0 0 0 587 0 0 0 0 >; 588 volt-sel = <0xf0164f 0xf0164f 0xf0164f 0xf0164f 589 0xf0164f 0xf0164f 0xf0164f NO_FUNC>; 590 volt-sel-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 591 BIT(4) BIT(5) BIT(6) 0 >; 592 #pinmux-cells = <2>; 593 gpio-group; 594 }; 595 596 pinctrli: pinctrl@f016a0 { 597 compatible = "ite,it8xxx2-pinctrl-func"; 598 reg = <0x00f016a0 8>; /* GPCR */ 599 func3-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 600 NO_FUNC 0xf03e10 0xf03e10 0xf03e10>; 601 func3-en-mask = <0 0 0 0 602 0 0x08 0x08 0x08 >; 603 func4-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 604 NO_FUNC NO_FUNC NO_FUNC NO_FUNC >; 605 func4-en-mask = <0 0 0 0 606 0 0 0 0 >; 607 volt-sel = <0xf01650 0xf01650 0xf01650 0xf01650 608 0xf01650 0xf01650 0xf01650 0xf01650>; 609 volt-sel-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 610 BIT(4) BIT(5) BIT(6) BIT(7) >; 611 #pinmux-cells = <2>; 612 gpio-group; 613 }; 614 615 pinctrlj: pinctrl@f016a8 { 616 compatible = "ite,it8xxx2-pinctrl-func"; 617 reg = <0x00f016a8 8>; /* GPCR */ 618 func3-gcr = <0xf03e14 NO_FUNC 0xf03e14 0xf03e14 619 0xf03e10 0xf03e10 NO_FUNC NO_FUNC>; 620 func3-en-mask = <0x01 0 0x01 0x02 621 0x02 0x03 0 0 >; 622 func4-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 623 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; 624 func4-en-mask = <0 0 0 0 625 0 0 0 0 >; 626 volt-sel = <0xf01651 0xf01651 0xf01651 0xf01651 627 0xf01651 0xf01651 NO_FUNC NO_FUNC >; 628 volt-sel-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 629 BIT(4) BIT(5) 0 0 >; 630 #pinmux-cells = <2>; 631 gpio-group; 632 }; 633 634 pinctrlk: pinctrl@f016b0 { 635 compatible = "ite,it8xxx2-pinctrl-func"; 636 reg = <0x00f016b0 8>; /* GPCR */ 637 func3-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 638 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; 639 func3-en-mask = <0 0 0 0 640 0 0 0 0 >; 641 func4-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 642 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; 643 func4-en-mask = <0 0 0 0 644 0 0 0 0 >; 645 volt-sel = <0xf01652 0xf01652 0xf01652 0xf01652 646 0xf01652 0xf01652 0xf01652 0xf01652>; 647 volt-sel-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 648 BIT(4) BIT(5) BIT(6) BIT(7) >; 649 #pinmux-cells = <2>; 650 gpio-group; 651 }; 652 653 pinctrll: pinctrl@f016b8 { 654 compatible = "ite,it8xxx2-pinctrl-func"; 655 reg = <0x00f016b8 8>; /* GPCR */ 656 func3-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 657 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; 658 func3-en-mask = <0 0 0 0 659 0 0 0 0 >; 660 func4-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 661 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; 662 func4-en-mask = <0 0 0 0 663 0 0 0 0 >; 664 volt-sel = <0xf01653 0xf01653 0xf01653 0xf01653 665 0xf01653 0xf01653 0xf01653 0xf01653>; 666 volt-sel-mask = <BIT(0) BIT(1) BIT(2) BIT(3) 667 BIT(4) BIT(5) BIT(6) BIT(7) >; 668 #pinmux-cells = <2>; 669 gpio-group; 670 }; 671 672 pinctrlm: pinctrl@f016c0 { 673 compatible = "ite,it8xxx2-pinctrl-func"; 674 reg = <0x00f016c0 8>; /* GPCR */ 675 func3-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 676 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; 677 func3-en-mask = <0 0 0 0 678 0 0 0 0 >; 679 func4-gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 680 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; 681 func4-en-mask = <0 0 0 0 682 0 0 0 0 >; 683 volt-sel = <0xf03e2d 0xf03e2d 0xf03e2d 0xf03e2d 684 0xf03e2d 0xf03e2d 0xf03e2d NO_FUNC >; 685 volt-sel-mask = <BIT(4) BIT(4) BIT(4) BIT(4) 686 BIT(4) BIT(4) BIT(4) 0 >; 687 #pinmux-cells = <2>; 688 gpio-group; 689 }; 690 691 pinctrlksi: pinctrl@f01d40 { 692 compatible = "ite,it8xxx2-pinctrl-func"; 693 reg = <0x00f01d40 8 /* KSIGCTRL */ 694 0x00f01d05 1>; /* KSICTRL */ 695 pp-od-mask = <NO_FUNC>; 696 pullup-mask = <BIT(2)>; 697 #pinmux-cells = <2>; 698 }; 699 700 pinctrlksol: pinctrl@f01d48 { 701 compatible = "ite,it8xxx2-pinctrl-func"; 702 reg = <0x00f01d48 8 /* KSOLGCTRL */ 703 0x00f01d02 1>; /* KSOCTRL */ 704 pp-od-mask = <BIT(0)>; 705 pullup-mask = <BIT(2)>; 706 #pinmux-cells = <2>; 707 }; 708 709 pinctrlksoh: pinctrl@f01d50 { 710 compatible = "ite,it8xxx2-pinctrl-func"; 711 reg = <0x00f01d50 8 /* KSOHGCTRL */ 712 0x00f01d02 1>; /* KSOCTRL */ 713 pp-od-mask = <BIT(0)>; 714 pullup-mask = <BIT(2)>; 715 #pinmux-cells = <2>; 716 }; 717 }; 718 719 wuc1: wakeup-controller@f01b00 { 720 compatible = "ite,it8xxx2-wuc"; 721 reg = <0x00f01b00 1 /* WUEMR1 */ 722 0x00f01b01 1 /* WUESR1 */ 723 0x00f01b02 1 /* WUENR1 */ 724 0x00f01b03 1>; /* WUBEMR1 */ 725 wakeup-controller; 726 #wuc-cells = <1>; 727 }; 728 729 wuc2: wakeup-controller@f01b04 { 730 compatible = "ite,it8xxx2-wuc"; 731 reg = <0x00f01b04 1 /* WUEMR2 */ 732 0x00f01b05 1 /* WUESR2 */ 733 IT8XXX2_WUC_UNUSED_REG 1 /* WUENR2 */ 734 0x00f01b07 1>; /* WUBEMR2 */ 735 wakeup-controller; 736 #wuc-cells = <1>; 737 }; 738 739 wuc3: wakeup-controller@f01b08 { 740 compatible = "ite,it8xxx2-wuc"; 741 reg = <0x00f01b08 1 /* WUEMR3 */ 742 0x00f01b09 1 /* WUESR3 */ 743 0x00f01b0a 1 /* WUENR3 */ 744 0x00f01b0b 1>; /* WUBEMR3 */ 745 wakeup-controller; 746 #wuc-cells = <1>; 747 }; 748 749 wuc4: wakeup-controller@f01b0c { 750 compatible = "ite,it8xxx2-wuc"; 751 reg = <0x00f01b0c 1 /* WUEMR4 */ 752 0x00f01b0d 1 /* WUESR4 */ 753 0x00f01b0e 1 /* WUENR4 */ 754 0x00f01b0f 1>; /* WUBEMR4 */ 755 wakeup-controller; 756 #wuc-cells = <1>; 757 }; 758 759 wuc5: wakeup-controller@f01b10 { 760 compatible = "ite,it8xxx2-wuc"; 761 reg = <0x00f01b10 1 /* WUEMR5 */ 762 0x00f01b11 1 /* WUESR5 */ 763 IT8XXX2_WUC_UNUSED_REG 1 /* WUENR5 */ 764 0x00f01b13 1>; /* WUBEMR5 */ 765 wakeup-controller; 766 #wuc-cells = <1>; 767 }; 768 769 wuc6: wakeup-controller@f01b14 { 770 compatible = "ite,it8xxx2-wuc"; 771 reg = <0x00f01b14 1 /* WUEMR6 */ 772 0x00f01b15 1 /* WUESR6 */ 773 IT8XXX2_WUC_UNUSED_REG 1 /* WUENR6 */ 774 0x00f01b17 1>; /* WUBEMR6 */ 775 wakeup-controller; 776 #wuc-cells = <1>; 777 }; 778 779 wuc7: wakeup-controller@f01b18 { 780 compatible = "ite,it8xxx2-wuc"; 781 reg = <0x00f01b18 1 /* WUEMR7 */ 782 0x00f01b19 1 /* WUESR7 */ 783 IT8XXX2_WUC_UNUSED_REG 1 /* WUENR7 */ 784 0x00f01b1b 1>; /* WUBEMR7 */ 785 wakeup-controller; 786 #wuc-cells = <1>; 787 }; 788 789 wuc8: wakeup-controller@f01b1c { 790 compatible = "ite,it8xxx2-wuc"; 791 reg = <0x00f01b1c 1 /* WUEMR8 */ 792 0x00f01b1d 1 /* WUESR8 */ 793 IT8XXX2_WUC_UNUSED_REG 1 /* WUENR8 */ 794 0x00f01b1f 1>; /* WUBEMR8 */ 795 wakeup-controller; 796 #wuc-cells = <1>; 797 }; 798 799 wuc9: wakeup-controller@f01b20 { 800 compatible = "ite,it8xxx2-wuc"; 801 reg = <0x00f01b20 1 /* WUEMR9 */ 802 0x00f01b21 1 /* WUESR9 */ 803 IT8XXX2_WUC_UNUSED_REG 1 /* WUENR9 */ 804 0x00f01b23 1>; /* WUBEMR9 */ 805 wakeup-controller; 806 #wuc-cells = <1>; 807 }; 808 809 wuc10: wakeup-controller@f01b24 { 810 compatible = "ite,it8xxx2-wuc"; 811 reg = <0x00f01b24 1 /* WUEMR10 */ 812 0x00f01b25 1 /* WUESR10 */ 813 IT8XXX2_WUC_UNUSED_REG 1 /* WUENR10 */ 814 0x00f01b27 1>; /* WUBEMR10 */ 815 wakeup-controller; 816 #wuc-cells = <1>; 817 }; 818 819 wuc11: wakeup-controller@f01b28 { 820 compatible = "ite,it8xxx2-wuc"; 821 reg = <0x00f01b28 1 /* WUEMR11 */ 822 0x00f01b29 1 /* WUESR11 */ 823 IT8XXX2_WUC_UNUSED_REG 1 /* WUENR11 */ 824 0x00f01b2b 1>; /* WUBEMR11 */ 825 wakeup-controller; 826 #wuc-cells = <1>; 827 }; 828 829 wuc12: wakeup-controller@f01b2c { 830 compatible = "ite,it8xxx2-wuc"; 831 reg = <0x00f01b2c 1 /* WUEMR12 */ 832 0x00f01b2d 1 /* WUESR12 */ 833 IT8XXX2_WUC_UNUSED_REG 1 /* WUENR12 */ 834 0x00f01b2f 1>; /* WUBEMR12 */ 835 wakeup-controller; 836 #wuc-cells = <1>; 837 }; 838 839 wuc13: wakeup-controller@f01b30 { 840 compatible = "ite,it8xxx2-wuc"; 841 reg = <0x00f01b30 1 /* WUEMR13 */ 842 0x00f01b31 1 /* WUESR13 */ 843 IT8XXX2_WUC_UNUSED_REG 1 /* WUENR13 */ 844 0x00f01b33 1>; /* WUBEMR13 */ 845 wakeup-controller; 846 #wuc-cells = <1>; 847 }; 848 849 wuc14: wakeup-controller@f01b34 { 850 compatible = "ite,it8xxx2-wuc"; 851 reg = <0x00f01b34 1 /* WUEMR14 */ 852 0x00f01b35 1 /* WUESR14 */ 853 IT8XXX2_WUC_UNUSED_REG 1 /* WUENR14 */ 854 0x00f01b37 1>; /* WUBEMR14 */ 855 wakeup-controller; 856 #wuc-cells = <1>; 857 }; 858 859 wuc15: wakeup-controller@f01b38 { 860 compatible = "ite,it8xxx2-wuc"; 861 reg = <0x00f01b38 1 /* WUEMR15 */ 862 0x00f01b39 1 /* WUESR15 */ 863 IT8XXX2_WUC_UNUSED_REG 1 /* WUENR15 */ 864 0x00f01b3b 1>; /* WUBEMR15 */ 865 wakeup-controller; 866 #wuc-cells = <1>; 867 }; 868 869 wuc16: wakeup-controller@f01b3c { 870 compatible = "ite,it8xxx2-wuc"; 871 reg = <0x00f01b3c 1 /* WUEMR16 */ 872 0x00f01b3d 1 /* WUESR16 */ 873 IT8XXX2_WUC_UNUSED_REG 1 /* WUENR16 */ 874 0x00f01b3f 1>; /* WUBEMR16 */ 875 wakeup-controller; 876 #wuc-cells = <1>; 877 }; 878 879 i2c0: i2c@f04300 { 880 compatible = "ite,enhance-i2c"; 881 #address-cells = <1>; 882 #size-cells = <0>; 883 reg = <0x00f04300 0x0080>; 884 interrupts = <IT8XXX2_IRQ_SMB_A IRQ_TYPE_LEVEL_HIGH>; 885 interrupt-parent = <&intc>; 886 status = "disabled"; 887 port-num = <SMB_CHANNEL_A>; 888 scl-gpios = <&gpiob 3 0>; 889 sda-gpios = <&gpiob 4 0>; 890 clock-gate-offset = <CGC_OFFSET_SMBA>; 891 }; 892 893 i2c1: i2c@f04380 { 894 compatible = "ite,enhance-i2c"; 895 #address-cells = <1>; 896 #size-cells = <0>; 897 reg = <0x00f04380 0x0080>; 898 interrupts = <IT8XXX2_IRQ_SMB_B IRQ_TYPE_LEVEL_HIGH>; 899 interrupt-parent = <&intc>; 900 status = "disabled"; 901 port-num = <SMB_CHANNEL_B>; 902 scl-gpios = <&gpioc 1 0>; 903 sda-gpios = <&gpioc 2 0>; 904 clock-gate-offset = <CGC_OFFSET_SMBB>; 905 }; 906 907 i2c2: i2c@f04400 { 908 compatible = "ite,enhance-i2c"; 909 #address-cells = <1>; 910 #size-cells = <0>; 911 reg = <0x00f04400 0x0080>; 912 interrupts = <IT8XXX2_IRQ_SMB_C IRQ_TYPE_LEVEL_HIGH>; 913 interrupt-parent = <&intc>; 914 status = "disabled"; 915 port-num = <SMB_CHANNEL_C>; 916 scl-gpios = <&gpiof 6 0>; 917 sda-gpios = <&gpiof 7 0>; 918 clock-gate-offset = <CGC_OFFSET_SMBC>; 919 }; 920 921 i2c3: i2c@f04480 { 922 compatible = "ite,enhance-i2c"; 923 #address-cells = <1>; 924 #size-cells = <0>; 925 reg = <0x00f04480 0x0080>; 926 interrupts = <IT8XXX2_IRQ_SMB_D IRQ_TYPE_LEVEL_HIGH>; 927 interrupt-parent = <&intc>; 928 status = "disabled"; 929 port-num = <I2C_CHANNEL_D>; 930 scl-gpios = <&gpioh 1 0>; 931 sda-gpios = <&gpioh 2 0>; 932 clock-gate-offset = <CGC_OFFSET_SMBD>; 933 }; 934 935 i2c4: i2c@f04500 { 936 compatible = "ite,enhance-i2c"; 937 #address-cells = <1>; 938 #size-cells = <0>; 939 reg = <0x00f04500 0x0080>; 940 interrupts = <IT8XXX2_IRQ_SMB_E IRQ_TYPE_LEVEL_HIGH>; 941 interrupt-parent = <&intc>; 942 status = "disabled"; 943 port-num = <I2C_CHANNEL_E>; 944 scl-gpios = <&gpioe 0 0>; 945 sda-gpios = <&gpioe 7 0>; 946 clock-gate-offset = <CGC_OFFSET_SMBE>; 947 }; 948 949 i2c5: i2c@f04580 { 950 compatible = "ite,enhance-i2c"; 951 #address-cells = <1>; 952 #size-cells = <0>; 953 reg = <0x00f04580 0x0080>; 954 interrupts = <IT8XXX2_IRQ_SMB_F IRQ_TYPE_LEVEL_HIGH>; 955 interrupt-parent = <&intc>; 956 status = "disabled"; 957 port-num = <I2C_CHANNEL_F>; 958 scl-gpios = <&gpioa 4 0>; 959 sda-gpios = <&gpioa 5 0>; 960 clock-gate-offset = <CGC_OFFSET_SMBF>; 961 }; 962 963 ite_uart2_wrapper: uartwrapper@f02820 { 964 compatible = "ite,it8xxx2-uart"; 965 reg = <0x00f02820 0x0020>; 966 status = "disabled"; 967 port-num = <2>; 968 gpios = <&gpiof 0 0>; 969 uart-dev = <&uart2>; 970 }; 971 972 usb0: usbd@f02f00 { 973 compatible = "ite,it82xx2-usb"; 974 interrupts = <IT8XXX2_IRQ_USB IRQ_TYPE_LEVEL_HIGH 975 IT8XXX2_IRQ_WU90 IRQ_TYPE_LEVEL_HIGH>; 976 interrupt-parent = <&intc>; 977 wucctrl = <&wuc_wu90>; 978 reg = <0x00f02f00 256>; 979 status = "disabled"; 980 num-bidir-endpoints = <1>; 981 num-in-endpoints = <10>; 982 num-out-endpoints = <5>; 983 }; 984 }; 985}; 986 987
