| /Zephyr-Core-3.5.0/drivers/clock_control/ |
| D | Kconfig.lpc11u6x | 4 # SPDX-License-Identifier: Apache-2.0
11 Enable driver for reset and clock control used in
19 Enable SRAM1
24 Enable USB RAM
27 prompt "LPC11U6X PLL Clock source"
32 Use the internal oscillator as the clock source for the PLL
37 Use the system oscillator as the clock source for the PLL
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| D | Kconfig.beetle | 4 # SPDX-License-Identifier: Apache-2.0
13 Enable driver for Reset & Clock Control subsystem found
19 bool "PLL on Beetle"
22 Enable PLL on Beetle.
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| D | clock_stm32f0_f3.c | 5 * SPDX-License-Identifier: Apache-2.0
43 * @brief Set up pll configuration
51 * PLL MUL in config_pll_sysclock()
52 * 2 -> LL_RCC_PLL_MUL_2 -> 0x00000000 in config_pll_sysclock()
53 * 3 -> LL_RCC_PLL_MUL_3 -> 0x00040000 in config_pll_sysclock()
54 * 4 -> LL_RCC_PLL_MUL_4 -> 0x00080000 in config_pll_sysclock()
56 * 16 -> LL_RCC_PLL_MUL_16 -> 0x00380000 in config_pll_sysclock()
58 pll_mul = ((STM32_PLL_MULTIPLIER - 2) << RCC_CFGR_PLLMUL_Pos); in config_pll_sysclock()
61 * PLL PREDIV in config_pll_sysclock()
62 * 1 -> LL_RCC_PREDIV_DIV_1 -> 0x00000000 in config_pll_sysclock()
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| D | clock_stm32_ll_wba.c | 4 * SPDX-License-Identifier: Apache-2.0
58 return -ENOTSUP; in enabled_clock()
68 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_on()
70 return -ENOTSUP; in stm32_clock_control_on()
73 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_on()
74 pclken->enr); in stm32_clock_control_on()
85 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_off()
87 return -ENOTSUP; in stm32_clock_control_off()
90 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_off()
91 pclken->enr); in stm32_clock_control_off()
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| D | clock_stm32l4_l5_wb_wl.c | 5 * SPDX-License-Identifier: Apache-2.0
30 * @brief Return PLL source
35 /* Configure PLL source */ in get_pll_source()
49 * @brief get the pll source frequency
69 * @brief Set up pll configuration
96 /* Enable the power interface clock */ in config_enable_default_clocks()
100 /* HW semaphore Clock enable */ in config_enable_default_clocks()
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| D | clock_stm32g0.c | 6 * SPDX-License-Identifier: Apache-2.0
22 * @brief Return PLL source
27 /* Configure PLL source */ in get_pll_source()
39 * @brief get the pll source frequency
55 * @brief Set up pll configuration
75 /* Enable the power interface clock */ in config_enable_default_clocks()
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| D | clock_stm32f2_f4_f7.c | 5 * SPDX-License-Identifier: Apache-2.0
22 * @brief Return PLL source
38 * @brief get the pll source frequency
54 * @brief Set up pll configuration
67 /* Enable the PLL (PLLON) before setting overdrive. Skipping the PLL in config_pll_sysclock()
69 * (ODSW) but the PLL clock system will be running during the locking in config_pll_sysclock()
71 * Sub section: Entering Over-drive mode. in config_pll_sysclock()
85 /* The PLL could still not be locked when returning to the caller in config_pll_sysclock()
86 * function. But the caller doesn't know we've turned on the PLL in config_pll_sysclock()
87 * for the overdrive function. The caller will try to turn on the PLL in config_pll_sysclock()
[all …]
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| D | clock_stm32g4.c | 4 * SPDX-License-Identifier: Apache-2.0
22 * @brief Return PLL source
27 /* Configure PLL source */ in get_pll_source()
39 * @brief get the pll source frequency
55 * @brief Set up pll configuration
80 /* Enable the power interface clock */ in config_enable_default_clocks()
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| D | clock_stm32_ll_u5.c | 6 * SPDX-License-Identifier: Apache-2.0
52 /** @brief returns the pll source frequency of given pll_id */
70 __ASSERT(0, "No PLL Source configured"); in get_pllsrc_frequency()
145 return -ENOTSUP; in enabled_clock()
155 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_on()
157 return -ENOTSUP; in stm32_clock_control_on()
160 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_on()
161 pclken->enr); in stm32_clock_control_on()
173 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_off()
175 return -ENOTSUP; in stm32_clock_control_off()
[all …]
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| D | clock_stm32l0_l1.c | 5 * SPDX-License-Identifier: Apache-2.0
28 * @brief Return PLL source
33 /* Configure PLL source */ in get_pll_source()
45 * @brief get the pll source frequency
61 * @brief Set up pll configuration
92 /* Enable System Configuration Controller clock. */ in config_enable_default_clocks()
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| D | clock_stm32_ll_h5.c | 7 * SPDX-License-Identifier: Apache-2.0
49 /** @brief returns the pll source frequency of given pll_id */
67 __ASSERT(0, "No PLL Source configured"); in get_pllsrc_frequency()
141 return -ENOTSUP; in enabled_clock()
151 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_on()
153 return -ENOTSUP; in stm32_clock_control_on()
156 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_on()
157 pclken->enr); in stm32_clock_control_on()
169 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_off()
171 return -ENOTSUP; in stm32_clock_control_off()
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| D | clock_stm32_ll_common.c | 2 * Copyright (c) 2017-2022 Linaro Limited.
5 * SPDX-License-Identifier: Apache-2.0
50 #define RCC_PLLP_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN)
55 #define RCC_PLLQ_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)
61 * @brief Return frequency for pll with 2 dividers and a multiplier
111 r = -ENOTSUP; in enabled_clock()
118 r = -ENOTSUP; in enabled_clock()
125 r = -ENOTSUP; in enabled_clock()
132 r = -ENOTSUP; in enabled_clock()
139 r = -ENOTSUP; in enabled_clock()
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| /Zephyr-Core-3.5.0/dts/bindings/mipi-dsi/ |
| D | st,stm32-mipi-dsi.yaml | 4 # SPDX-License-Identifier: Apache-2.0
9 compatible: "st,stm32-mipi-dsi"
11 include: [mipi-dsi-host.yaml, reset-device.yaml]
17 clock-names:
20 "dsiclk" DSI clock enable.
28 hs-active-high:
33 vs-active-high:
38 de-active-high:
41 DSI host data enable is active high.
43 non-continuous:
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| /Zephyr-Core-3.5.0/soc/riscv/riscv-ite/it8xxx2/ |
| D | soc.c | 4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
48 return -ERANGE; in chip_get_pll_freq()
61 * This load operation will ensure PLL setting is taken into in chip_pll_ctrl()
82 * PLL frequency setting = 4 (48MHz)
83 * FND div = 0 (PLL / 1 = 48 mhz)
84 * UART div = 1 (PLL / 2 = 24 mhz)
85 * SMB div = 1 (PLL / 2 = 24 mhz)
86 * SSPI div = 1 (PLL / 2 = 24 mhz)
88 * JTAG div = 1 (PLL / 2 = 24 mhz)
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| D | Kconfig.soc | 2 # SPDX-License-Identifier: Apache-2.0
16 # https://www.ite.com.tw/uploads/product_download/it81202-bx-chip-errata.pdf
75 Change frequency of PLL, CPU, and flash to 48MHz during initialization.
78 (PLL and CPU run at 48MHz, flash frequency is 16MHz)
84 On IT81202 (128-pins package), the pins of GPIO group K and L aren't
85 bonding with pad. So we configure these pins as internal pull-down
93 floating internally. We need to enable internal pull-down for the pin
96 so we enable output low for it at initialization to prevent leakage.
106 prompt "Clock source for PLL reference clock"
109 bool "Use the +/-2.3% internal clock generator"
[all …]
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| /Zephyr-Core-3.5.0/soc/arm/nxp_imx/mimx8ml8_m7/ |
| D | soc.c | 4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/dt-bindings/rdc/imx_rdc.h>
17 /* OSC/PLL is already initialized by ROM and Cortex-A53 (u-boot) */
32 * The M7 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in SOC_RdcInit()
46 /* Enable the CCGR gate for SysPLL1 in Domain 1 */ in SOC_RdcInit()
48 /* Enable the CCGR gate for SysPLL2 in Domain 1 */ in SOC_RdcInit()
50 /* Enable the CCGR gate for SysPLL3 in Domain 1 */ in SOC_RdcInit()
53 /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ in SOC_RdcInit()
61 .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
69 .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
[all …]
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| /Zephyr-Core-3.5.0/dts/bindings/clock/ |
| D | st,stm32-msi-clock.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "st,stm32-msi-clock"
8 include: [clock-controller.yaml, base.yaml]
11 msi-range:
18 - 0 # range 0 around 100 kHz
19 - 1 # range 1 around 200 kHz
20 - 2 # range 2 around 400 kHz
21 - 3 # range 3 around 800 kHz
22 - 4 # range 4 around 1M Hz
23 - 5 # range 5 around 2 MHz
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| D | microchip,xec-pcr.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "microchip,xec-pcr"
8 include: [clock-controller.yaml, pinctrl-device.yaml, base.yaml]
14 core-clock-div:
17 description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock
19 slow-clock-div:
25 pll-32k-src:
28 description: 32 KHz clock source for PLL
30 periph-32k-src:
35 xtal-single-ended:
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| /Zephyr-Core-3.5.0/soc/arm/nxp_imx/mimx8mm6_m4/ |
| D | soc.c | 4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/dt-bindings/rdc/imx_rdc.h>
17 /* OSC/PLL is already initialized by ROM and Cortex-A53 (u-boot) */
27 * The M4 core is running at domain 1, enable clock gate for in SOC_RdcInit()
39 * The M4 core is running at domain 1, enable the PLL clock sources in SOC_RdcInit()
42 /* Enable SysPLL1 to Domain 1 */ in SOC_RdcInit()
44 /* Enable SysPLL2 to Domain 1 */ in SOC_RdcInit()
46 /* Enable SysPLL3 to Domain 1 */ in SOC_RdcInit()
48 /* Enable AudioPLL1 to Domain 1 */ in SOC_RdcInit()
50 /* Enable AudioPLL2 to Domain 1 */ in SOC_RdcInit()
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| /Zephyr-Core-3.5.0/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/src/ |
| D | test_stm32_clock_configuration.c | 4 * SPDX-License-Identifier: Apache-2.0
40 "Expected sysclk src: PLL (0x%x). Actual: 0x%x", in ZTEST()
71 "Expected PLL src: HSE (%d). Actual PLL src: %d", in ZTEST()
76 "Expected PLL src: HSI (%d). Actual PLL src: %d", in ZTEST()
80 "Expected PLL src: HSI (%d). Actual PLL src: %d", in ZTEST()
85 "Expected PLL src: MSI (%d). Actual PLL src: %d", in ZTEST()
87 #else /* --> RCC_PLLSOURCE_NONE */ in ZTEST()
93 /* check RCC_CR_PLLON bit to enable/disable the PLL, but no status function exist */ in ZTEST()
94 if (READ_BIT(RCC->CR, RCC_CR_PLLON) == RCC_CR_PLLON) { in ZTEST()
95 /* should not happen : PLL must be disabled when not used */ in ZTEST()
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| /Zephyr-Core-3.5.0/soc/arm/microchip_mec/mec172x/ |
| D | power.c | 5 * SPDX-License-Identifier: Apache-2.0
27 * Lower power dissipation, 48MHz PLL is off
30 * between 16 to 25 MHz. Minimum 3ms until PLL reaches lock
34 * We touch the Cortex-M's primary mask and base priority registers
43 * PLL. Firmware should not disable JTAG/SWD in the EC subsystem
45 * TAP controller in a state of requesting clocks preventing the PLL
67 * Enable deep sleep mode in CM4 and MEC172x. in z_power_soc_deep_sleep()
68 * Enable CM4 deep sleep and sleep signals assertion on WFI. in z_power_soc_deep_sleep()
69 * Set MCHP Heavy sleep (PLL OFF when all CLK_REQ clear) and SLEEP_ALL in z_power_soc_deep_sleep()
74 SCB->SCR |= BIT(2); in z_power_soc_deep_sleep()
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| /Zephyr-Core-3.5.0/soc/arm/nxp_imx/rt/ |
| D | lpm_rt1064.c | 4 * SPDX-License-Identifier: Apache-2.0
66 while ((CCM->CDHIPR & ((1UL << busy_shift))) != 0UL) { in clock_set_mux()
88 while ((CCM->CDHIPR & ((uint32_t)(1UL << busy_shift))) != 0UL) { in clock_set_div()
101 /* Bypass PLL first */ in clock_init_usb1_pll()
102 CCM_ANALOG->PLL_USB1 = (CCM_ANALOG->PLL_USB1 & (~CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)) | in clock_init_usb1_pll()
103 CCM_ANALOG_PLL_USB1_BYPASS_MASK | CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(config->src); in clock_init_usb1_pll()
105 CCM_ANALOG->PLL_USB1 = (CCM_ANALOG->PLL_USB1 & (~CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)) | in clock_init_usb1_pll()
108 CCM_ANALOG_PLL_USB1_DIV_SELECT(config->loopDivider); in clock_init_usb1_pll()
110 while ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_LOCK_MASK) == 0UL) { in clock_init_usb1_pll()
115 CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_BYPASS_MASK; in clock_init_usb1_pll()
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| /Zephyr-Core-3.5.0/soc/arm/nxp_imx/rt5xx/ |
| D | soc.c | 2 * Copyright 2022-2023, NXP
4 * SPDX-License-Identifier: Apache-2.0
11 * This module provides routines to initialize and support board-level
59 /* Numerator of the Audio PLL fractional loop divider is 0 */
61 /* Denominator of the Audio PLL fractional loop divider is 1 */
160 /* enable usb ip clock */ in usb_device_clock_init()
165 /* enable usb ram clock */ in usb_device_clock_init()
167 /* enable USB PHY PLL clock, the phy bus clock (480MHz) source is same with USB IP */ in usb_device_clock_init()
182 /* enable usb1 host clock */ in usb_device_clock_init()
184 /* Wait until host_needclk de-asserts */ in usb_device_clock_init()
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| /Zephyr-Core-3.5.0/dts/bindings/pwm/ |
| D | microchip,xec-pwmbbled.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 include: [pwm-controller.yaml, base.yaml, pinctrl-device.yaml]
8 compatible: "microchip,xec-pwmbbled"
27 clock-select:
32 - PWM_BBLED_CLK_AHB: Clock source is the PLL based AHB clock
33 - PWM_BBLED_CLK_SLOW: Clock source is the PLL based PCR slow clock
34 - PWM_BBLED_CLK_32K: Clock source is the 32KHz domain
36 - "PWM_BBLED_CLK_32K"
37 - "PWM_BBLED_CLK_SLOW"
38 - "PWM_BBLED_CLK_48M"
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| /Zephyr-Core-3.5.0/dts/bindings/can/ |
| D | microchip,mcp251xfd.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 Microchip MCP251XFD SPI CAN-FD controller
11 cs-gpios = <&mikrobus_header 2 GPIO_ACTIVE_LOW>;
17 spi-max-frequency = <18000000>;
18 int-gpios = <&mikrobus_header 7 GPIO_ACTIVE_LOW>;
20 osc-freq = <40000000>;
22 bus-speed = <125000>;
23 sample-point = <875>;
24 bus-speed-data = <1000000>;
25 sample-point-data = <875>;
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