Lines Matching +full:pll +full:- +full:enable

2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "microchip,xec-pcr"
8 include: [clock-controller.yaml, pinctrl-device.yaml, base.yaml]
14   core-clock-div:
17     description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock
19   slow-clock-div:
25   pll-32k-src:
28     description: 32 KHz clock source for PLL
30   periph-32k-src:
35   xtal-single-ended:
39   clk32kmon-period-min:
45   clk32kmon-period-max:
51   clk32kmon-duty-cycle-var-max:
58   clk32kmon-valid-min:
64   xtal-enable-delay-ms:
72   pll-lock-timeout-ms:
77       Timeout in milliseconds waiting for PLL to lock to new clock source.
79   clkmon-bypass:
81     description: Bypass clkmon check of crystal or XTAL2 single-ended clock.
83   internal-osc-disable:
87       for PLL and Periheral devices then disable the internal 32KHz
90   pinctrl-0:
93   pinctrl-names:
96   "#clock-cells":
99 clock-cells:
100   - regidx
101   - bitpos
102   - domain