1# Copyright (c) 2020 ITE Corporation. All Rights Reserved.
2# SPDX-License-Identifier: Apache-2.0
3
4choice
5prompt "ITE IT8XXX2 system implementation"
6depends on SOC_SERIES_RISCV32_IT8XXX2
7
8config SOC_IT8XXX2
9	bool "ITE IT8XXX2 system implementation"
10	select RISCV
11	select ATOMIC_OPERATIONS_BUILTIN
12	select RISCV_ISA_RV32I
13	select RISCV_ISA_EXT_ZICSR
14	select RISCV_ISA_EXT_ZIFENCEI
15	# Workaround mul instruction bug, see:
16	# https://www.ite.com.tw/uploads/product_download/it81202-bx-chip-errata.pdf
17	select RISCV_ISA_EXT_M if !(SOC_IT81302_BX || SOC_IT81202_BX)
18	select RISCV_ISA_EXT_A
19	select RISCV_ISA_EXT_C
20	select FLASH
21	select FLASH_HAS_PAGE_LAYOUT
22	select FLASH_HAS_DRIVER_ENABLED
23	select HAS_FLASH_LOAD_OFFSET
24
25endchoice
26
27config SOC_IT8XXX2_REG_SET_V1
28	bool
29	help
30	  This option is selected by a variable of which soc, and will
31	  determine the register for the IT81xx2 specification.
32
33config SOC_IT8XXX2_REG_SET_V2
34	bool
35	help
36	  This option is selected by a variable of which soc, and will
37	  determine the register for the IT82xx2 specification.
38
39if SOC_IT8XXX2
40
41choice IT8XXX2_SERIES
42	prompt "IT8XXX2 Series"
43	default SOC_IT81302_BX
44
45config SOC_IT81302_BX
46	bool "IT81302 BX version"
47	select SOC_IT8XXX2_REG_SET_V1
48
49config SOC_IT81202_BX
50	bool "IT81202 BX version"
51	select SOC_IT8XXX2_REG_SET_V1
52
53config SOC_IT81302_CX
54	bool "IT81302 CX version"
55	select SOC_IT8XXX2_REG_SET_V1
56
57config SOC_IT81202_CX
58	bool "IT81202 CX version"
59	select SOC_IT8XXX2_REG_SET_V1
60
61config SOC_IT82202_AX
62	bool "IT82202 AX version"
63	select SOC_IT8XXX2_REG_SET_V2
64
65config SOC_IT82302_AX
66	bool "IT82302 AX version"
67	select SOC_IT8XXX2_REG_SET_V2
68
69endchoice
70
71config SOC_IT8XXX2_PLL_FLASH_48M
72	bool "Flash frequency is 48MHz"
73	default y
74	help
75	  Change frequency of PLL, CPU, and flash to 48MHz during initialization.
76
77	  Set n to use the default settings.
78	  (PLL and CPU run at 48MHz, flash frequency is 16MHz)
79
80config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN
81	bool "The pins of GPIO group K and L aren't bonding with pad"
82	default y
83	help
84	  On IT81202 (128-pins package), the pins of GPIO group K and L aren't
85	  bonding with pad. So we configure these pins as internal pull-down
86	  at default to prevent leakage current due to floating.
87
88config SOC_IT8XXX2_GPIO_H7_DEFAULT_OUTPUT_LOW
89	bool "The GPIOH7 isn't bonding with pad and is left floating internally"
90	default y
91	help
92	  On IT81202/IT81302, the GPIOH7 isn't bonding with pad and is left
93	  floating internally. We need to enable internal pull-down for the pin
94	  to prevent leakage current, but IT81202/IT81302 doesn't have the
95	  capability to pull it down. We can only set it as output low,
96	  so we enable output low for it at initialization to prevent leakage.
97
98config SOC_IT8XXX2_CPU_IDLE_GATING
99	bool
100	help
101	  This option determines whether the entering CPU idle mode can be
102	  gated by individual drivers. When this option is disabled, CPU idle
103	  mode is always permitted.
104
105choice
106	prompt "Clock source for PLL reference clock"
107
108config SOC_IT8XXX2_INT_32K
109	bool "Use the +/-2.3% internal clock generator"
110
111config SOC_IT8XXX2_EXT_32K
112	bool "Use external 32.768 kHz clock source"
113
114endchoice
115
116config SOC_IT8XXX2_USE_ILM
117	bool
118	default y
119	help
120	  If enabled, Instruction Local Memory (ILM) will be configured to execute
121	  code placed in the .__ram_code section out of RAM. This consumes RAM in
122	  blocks of 4 kilobytes, but performance of code in ILM is much more
123	  predictable than executing from Flash directly, and some code (such as code
124	  that writes to the internal Flash) must execute out of RAM.
125
126config SOC_IT8XXX2_EXCEPTIONS_IN_RAM
127	bool "Place exception handling code in RAM"
128	default y
129	select SOC_IT8XXX2_USE_ILM
130	help
131	  Place exception handling (ISR entry/exit and related) code in ILM, which
132	  has more reliable performance characteristics than executing directly from
133	  Flash. This can significantly improve performance when under I-cache
134	  pressure.
135
136config SOC_IT8XXX2_SHA256_HW_ACCELERATE
137	bool "HW SHA256 calculation"
138	help
139	  IT8XXX2 HW support sha256 calculation, and its calculation is faster than FW.
140	  We place SHA256 message, hash and key data (total 512bytes) in RAM.
141	  If we enable this config, because HW limits, the sha256 data must place in
142	  first 4KB of RAM.
143
144DT_CHOSEN_ZEPHYR_FLASH := zephyr,flash
145
146config SOC_IT8XXX2_FLASH_SIZE_BYTES
147	hex
148	default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_ZEPHYR_FLASH))
149	help
150	  Total size of writable flash.
151
152config ILM_MAX_SIZE
153	int "ILM Size in kB"
154	default 60 if SOC_IT81202_CX || SOC_IT81302_CX
155	default SRAM_SIZE
156
157endif # SOC_IT8XXX2
158