Searched full:on (Results 1 – 25 of 1876) sorted by relevance
12345678910>>...76
| /hal_atmel-3.6.0/asf/sam0/include/samd51/pio/ |
| D | samd51n19a.h | 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
196 #define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */
200 #define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */
204 #define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */
208 #define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */
212 #define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */
216 #define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */
220 #define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */
224 #define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */
229 #define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */
[all …]
|
| D | samd51n20a.h | 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
196 #define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */
200 #define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */
204 #define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */
208 #define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */
212 #define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */
216 #define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */
220 #define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */
224 #define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */
229 #define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */
[all …]
|
| D | samd51p19a.h | 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
232 #define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */
236 #define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */
240 #define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */
244 #define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */
248 #define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */
252 #define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */
256 #define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */
260 #define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */
265 #define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */
[all …]
|
| D | samd51p20a.h | 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
232 #define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */
236 #define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */
240 #define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */
244 #define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */
248 #define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */
252 #define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */
256 #define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */
260 #define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */
265 #define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */
[all …]
|
| D | samd51j18a.h | 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
136 #define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */
140 #define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */
145 #define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */
149 #define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */
153 #define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */
158 #define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */
162 #define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */
166 #define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */
170 #define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */
[all …]
|
| D | samd51j19a.h | 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
136 #define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */
140 #define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */
145 #define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */
149 #define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */
153 #define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */
158 #define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */
162 #define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */
166 #define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */
170 #define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */
[all …]
|
| D | samd51j20a.h | 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
136 #define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */
140 #define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */
145 #define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */
149 #define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */
153 #define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */
158 #define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */
162 #define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */
166 #define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */
170 #define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */
[all …]
|
| /hal_atmel-3.6.0/asf/sam0/include/same51/pio/ |
| D | same51n19a.h | 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
196 #define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */
200 #define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */
204 #define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */
208 #define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */
212 #define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */
216 #define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */
220 #define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */
224 #define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */
229 #define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */
[all …]
|
| D | same51n20a.h | 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
196 #define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */
200 #define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */
204 #define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */
208 #define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */
212 #define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */
216 #define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */
220 #define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */
224 #define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */
229 #define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */
[all …]
|
| /hal_atmel-3.6.0/asf/sam/include/sam4l/pio/ |
| D | sam4lc2c.h | 20 * distributed under the License is distributed on an "AS IS" BASIS,
183 #define PIN_PA24B_TWIMS0_TWCK _L_(24) /**< \brief TWIMS0 signal: TWCK on PA24 mux B */
187 #define PIN_PA23B_TWIMS0_TWD _L_(23) /**< \brief TWIMS0 signal: TWD on PA23 mux B */
192 #define PIN_PB01A_TWIMS1_TWCK _L_(33) /**< \brief TWIMS1 signal: TWCK on PB01 mux A */
196 #define PIN_PB00A_TWIMS1_TWD _L_(32) /**< \brief TWIMS1 signal: TWD on PB00 mux A */
201 #define PIN_PA22E_TWIMS2_TWCK _L_(22) /**< \brief TWIMS2 signal: TWCK on PA22 mux E */
205 #define PIN_PA21E_TWIMS2_TWD _L_(21) /**< \brief TWIMS2 signal: TWD on PA21 mux E */
210 #define PIN_PB15C_TWIMS3_TWCK _L_(47) /**< \brief TWIMS3 signal: TWCK on PB15 mux C */
214 #define PIN_PB14C_TWIMS3_TWD _L_(46) /**< \brief TWIMS3 signal: TWD on PB14 mux C */
219 #define PIN_PB05D_IISC_IMCK _L_(37) /**< \brief IISC signal: IMCK on PB05 mux D */
[all …]
|
| D | sam4lc4c.h | 20 * distributed under the License is distributed on an "AS IS" BASIS,
183 #define PIN_PA24B_TWIMS0_TWCK _L_(24) /**< \brief TWIMS0 signal: TWCK on PA24 mux B */
187 #define PIN_PA23B_TWIMS0_TWD _L_(23) /**< \brief TWIMS0 signal: TWD on PA23 mux B */
192 #define PIN_PB01A_TWIMS1_TWCK _L_(33) /**< \brief TWIMS1 signal: TWCK on PB01 mux A */
196 #define PIN_PB00A_TWIMS1_TWD _L_(32) /**< \brief TWIMS1 signal: TWD on PB00 mux A */
201 #define PIN_PA22E_TWIMS2_TWCK _L_(22) /**< \brief TWIMS2 signal: TWCK on PA22 mux E */
205 #define PIN_PA21E_TWIMS2_TWD _L_(21) /**< \brief TWIMS2 signal: TWD on PA21 mux E */
210 #define PIN_PB15C_TWIMS3_TWCK _L_(47) /**< \brief TWIMS3 signal: TWCK on PB15 mux C */
214 #define PIN_PB14C_TWIMS3_TWD _L_(46) /**< \brief TWIMS3 signal: TWD on PB14 mux C */
219 #define PIN_PB05D_IISC_IMCK _L_(37) /**< \brief IISC signal: IMCK on PB05 mux D */
[all …]
|
| D | sam4lc8c.h | 20 * distributed under the License is distributed on an "AS IS" BASIS,
183 #define PIN_PA24B_TWIMS0_TWCK _L_(24) /**< \brief TWIMS0 signal: TWCK on PA24 mux B */
187 #define PIN_PA23B_TWIMS0_TWD _L_(23) /**< \brief TWIMS0 signal: TWD on PA23 mux B */
192 #define PIN_PB01A_TWIMS1_TWCK _L_(33) /**< \brief TWIMS1 signal: TWCK on PB01 mux A */
196 #define PIN_PB00A_TWIMS1_TWD _L_(32) /**< \brief TWIMS1 signal: TWD on PB00 mux A */
201 #define PIN_PA22E_TWIMS2_TWCK _L_(22) /**< \brief TWIMS2 signal: TWCK on PA22 mux E */
205 #define PIN_PA21E_TWIMS2_TWD _L_(21) /**< \brief TWIMS2 signal: TWD on PA21 mux E */
210 #define PIN_PB15C_TWIMS3_TWCK _L_(47) /**< \brief TWIMS3 signal: TWCK on PB15 mux C */
214 #define PIN_PB14C_TWIMS3_TWD _L_(46) /**< \brief TWIMS3 signal: TWD on PB14 mux C */
219 #define PIN_PB05D_IISC_IMCK _L_(37) /**< \brief IISC signal: IMCK on PB05 mux D */
[all …]
|
| D | sam4ls2c.h | 20 * distributed under the License is distributed on an "AS IS" BASIS,
193 #define PIN_PA24B_TWIMS0_TWCK _L_(24) /**< \brief TWIMS0 signal: TWCK on PA24 mux B */
197 #define PIN_PA23B_TWIMS0_TWD _L_(23) /**< \brief TWIMS0 signal: TWD on PA23 mux B */
202 #define PIN_PB01A_TWIMS1_TWCK _L_(33) /**< \brief TWIMS1 signal: TWCK on PB01 mux A */
206 #define PIN_PB00A_TWIMS1_TWD _L_(32) /**< \brief TWIMS1 signal: TWD on PB00 mux A */
211 #define PIN_PA22E_TWIMS2_TWCK _L_(22) /**< \brief TWIMS2 signal: TWCK on PA22 mux E */
215 #define PIN_PA21E_TWIMS2_TWD _L_(21) /**< \brief TWIMS2 signal: TWD on PA21 mux E */
220 #define PIN_PB15C_TWIMS3_TWCK _L_(47) /**< \brief TWIMS3 signal: TWCK on PB15 mux C */
224 #define PIN_PB14C_TWIMS3_TWD _L_(46) /**< \brief TWIMS3 signal: TWD on PB14 mux C */
229 #define PIN_PB05D_IISC_IMCK _L_(37) /**< \brief IISC signal: IMCK on PB05 mux D */
[all …]
|
| D | sam4ls4c.h | 20 * distributed under the License is distributed on an "AS IS" BASIS,
193 #define PIN_PA24B_TWIMS0_TWCK _L_(24) /**< \brief TWIMS0 signal: TWCK on PA24 mux B */
197 #define PIN_PA23B_TWIMS0_TWD _L_(23) /**< \brief TWIMS0 signal: TWD on PA23 mux B */
202 #define PIN_PB01A_TWIMS1_TWCK _L_(33) /**< \brief TWIMS1 signal: TWCK on PB01 mux A */
206 #define PIN_PB00A_TWIMS1_TWD _L_(32) /**< \brief TWIMS1 signal: TWD on PB00 mux A */
211 #define PIN_PA22E_TWIMS2_TWCK _L_(22) /**< \brief TWIMS2 signal: TWCK on PA22 mux E */
215 #define PIN_PA21E_TWIMS2_TWD _L_(21) /**< \brief TWIMS2 signal: TWD on PA21 mux E */
220 #define PIN_PB15C_TWIMS3_TWCK _L_(47) /**< \brief TWIMS3 signal: TWCK on PB15 mux C */
224 #define PIN_PB14C_TWIMS3_TWD _L_(46) /**< \brief TWIMS3 signal: TWD on PB14 mux C */
229 #define PIN_PB05D_IISC_IMCK _L_(37) /**< \brief IISC signal: IMCK on PB05 mux D */
[all …]
|
| D | sam4ls8c.h | 20 * distributed under the License is distributed on an "AS IS" BASIS,
193 #define PIN_PA24B_TWIMS0_TWCK _L_(24) /**< \brief TWIMS0 signal: TWCK on PA24 mux B */
197 #define PIN_PA23B_TWIMS0_TWD _L_(23) /**< \brief TWIMS0 signal: TWD on PA23 mux B */
202 #define PIN_PB01A_TWIMS1_TWCK _L_(33) /**< \brief TWIMS1 signal: TWCK on PB01 mux A */
206 #define PIN_PB00A_TWIMS1_TWD _L_(32) /**< \brief TWIMS1 signal: TWD on PB00 mux A */
211 #define PIN_PA22E_TWIMS2_TWCK _L_(22) /**< \brief TWIMS2 signal: TWCK on PA22 mux E */
215 #define PIN_PA21E_TWIMS2_TWD _L_(21) /**< \brief TWIMS2 signal: TWD on PA21 mux E */
220 #define PIN_PB15C_TWIMS3_TWCK _L_(47) /**< \brief TWIMS3 signal: TWCK on PB15 mux C */
224 #define PIN_PB14C_TWIMS3_TWD _L_(46) /**< \brief TWIMS3 signal: TWD on PB14 mux C */
229 #define PIN_PB05D_IISC_IMCK _L_(37) /**< \brief IISC signal: IMCK on PB05 mux D */
[all …]
|
| /hal_atmel-3.6.0/asf/sam0/include/same54/pio/ |
| D | same54p20a.h | 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
232 #define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */
236 #define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */
240 #define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */
244 #define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */
248 #define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */
252 #define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */
256 #define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */
260 #define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */
265 #define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */
[all …]
|
| D | same54p19a.h | 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
232 #define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */
236 #define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */
240 #define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */
244 #define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */
248 #define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */
252 #define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */
256 #define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */
260 #define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */
265 #define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */
[all …]
|
| D | same54n19a.h | 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
196 #define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */
200 #define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */
204 #define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */
208 #define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */
212 #define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */
216 #define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */
220 #define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */
224 #define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */
229 #define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */
[all …]
|
| D | same54n20a.h | 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
196 #define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */
200 #define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */
204 #define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */
208 #define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */
212 #define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */
216 #define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */
220 #define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */
224 #define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */
229 #define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */
[all …]
|
| /hal_atmel-3.6.0/asf/sam0/include/same53/pio/ |
| D | same53n19a.h | 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
196 #define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */
200 #define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */
204 #define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */
208 #define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */
212 #define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */
216 #define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */
220 #define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */
224 #define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */
229 #define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */
[all …]
|
| D | same53n20a.h | 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
196 #define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */
200 #define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */
204 #define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */
208 #define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */
212 #define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */
216 #define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */
220 #define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */
224 #define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */
229 #define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */
[all …]
|
| /hal_atmel-3.6.0/asf/sam/include/samv71/pio/ |
| D | samv71q19.h | 21 * distributed under the License is distributed on an "AS IS" BASIS,
385 #define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: ADTRG on PA8 mux…
389 #define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AD0 on PD30 mux …
392 #define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AD1 on PA21 mux …
395 #define PIN_PA21X1_AFEC0_PIODCEN2 _L_(21) /**< AFEC0 signal: PIODCEN2 on PA21…
398 #define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AD2 on PB3 mux X…
401 #define PIN_PB3X1_AFEC0_WKUP12 _L_(35) /**< AFEC0 signal: WKUP12 on PB3 mu…
404 #define PIN_PE5X1_AFEC0_AD3 _L_(133) /**< AFEC0 signal: AD3 on PE5 mux X…
407 #define PIN_PE4X1_AFEC0_AD4 _L_(132) /**< AFEC0 signal: AD4 on PE4 mux X…
410 #define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AD5 on PB2 mux X…
[all …]
|
| D | samv71q20.h | 21 * distributed under the License is distributed on an "AS IS" BASIS,
385 #define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: ADTRG on PA8 mux…
389 #define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AD0 on PD30 mux …
392 #define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AD1 on PA21 mux …
395 #define PIN_PA21X1_AFEC0_PIODCEN2 _L_(21) /**< AFEC0 signal: PIODCEN2 on PA21…
398 #define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AD2 on PB3 mux X…
401 #define PIN_PB3X1_AFEC0_WKUP12 _L_(35) /**< AFEC0 signal: WKUP12 on PB3 mu…
404 #define PIN_PE5X1_AFEC0_AD3 _L_(133) /**< AFEC0 signal: AD3 on PE5 mux X…
407 #define PIN_PE4X1_AFEC0_AD4 _L_(132) /**< AFEC0 signal: AD4 on PE4 mux X…
410 #define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AD5 on PB2 mux X…
[all …]
|
| D | samv71q21.h | 21 * distributed under the License is distributed on an "AS IS" BASIS,
385 #define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: ADTRG on PA8 mux…
389 #define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AD0 on PD30 mux …
392 #define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AD1 on PA21 mux …
395 #define PIN_PA21X1_AFEC0_PIODCEN2 _L_(21) /**< AFEC0 signal: PIODCEN2 on PA21…
398 #define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AD2 on PB3 mux X…
401 #define PIN_PB3X1_AFEC0_WKUP12 _L_(35) /**< AFEC0 signal: WKUP12 on PB3 mu…
404 #define PIN_PE5X1_AFEC0_AD3 _L_(133) /**< AFEC0 signal: AD3 on PE5 mux X…
407 #define PIN_PE4X1_AFEC0_AD4 _L_(132) /**< AFEC0 signal: AD4 on PE4 mux X…
410 #define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AD5 on PB2 mux X…
[all …]
|
| /hal_atmel-3.6.0/asf/sam/include/same70/pio/ |
| D | same70q19.h | 21 * distributed under the License is distributed on an "AS IS" BASIS,
385 #define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: ADTRG on PA8 mux…
389 #define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AD0 on PD30 mux …
392 #define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AD1 on PA21 mux …
395 #define PIN_PA21X1_AFEC0_PIODCEN2 _L_(21) /**< AFEC0 signal: PIODCEN2 on PA21…
398 #define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AD2 on PB3 mux X…
401 #define PIN_PB3X1_AFEC0_WKUP12 _L_(35) /**< AFEC0 signal: WKUP12 on PB3 mu…
404 #define PIN_PE5X1_AFEC0_AD3 _L_(133) /**< AFEC0 signal: AD3 on PE5 mux X…
407 #define PIN_PE4X1_AFEC0_AD4 _L_(132) /**< AFEC0 signal: AD4 on PE4 mux X…
410 #define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AD5 on PB2 mux X…
[all …]
|
12345678910>>...76
