1 /** 2 * \file 3 * 4 * \brief Peripheral I/O description for SAMD51J18A 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMD51J18A_PIO_ 31 #define _SAMD51J18A_PIO_ 32 33 #define PIN_PA00 0 /**< \brief Pin Number for PA00 */ 34 #define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ 35 #define PIN_PA01 1 /**< \brief Pin Number for PA01 */ 36 #define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ 37 #define PIN_PA02 2 /**< \brief Pin Number for PA02 */ 38 #define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ 39 #define PIN_PA03 3 /**< \brief Pin Number for PA03 */ 40 #define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ 41 #define PIN_PA04 4 /**< \brief Pin Number for PA04 */ 42 #define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ 43 #define PIN_PA05 5 /**< \brief Pin Number for PA05 */ 44 #define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ 45 #define PIN_PA06 6 /**< \brief Pin Number for PA06 */ 46 #define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ 47 #define PIN_PA07 7 /**< \brief Pin Number for PA07 */ 48 #define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ 49 #define PIN_PA08 8 /**< \brief Pin Number for PA08 */ 50 #define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ 51 #define PIN_PA09 9 /**< \brief Pin Number for PA09 */ 52 #define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ 53 #define PIN_PA10 10 /**< \brief Pin Number for PA10 */ 54 #define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ 55 #define PIN_PA11 11 /**< \brief Pin Number for PA11 */ 56 #define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ 57 #define PIN_PA12 12 /**< \brief Pin Number for PA12 */ 58 #define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ 59 #define PIN_PA13 13 /**< \brief Pin Number for PA13 */ 60 #define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ 61 #define PIN_PA14 14 /**< \brief Pin Number for PA14 */ 62 #define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ 63 #define PIN_PA15 15 /**< \brief Pin Number for PA15 */ 64 #define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ 65 #define PIN_PA16 16 /**< \brief Pin Number for PA16 */ 66 #define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ 67 #define PIN_PA17 17 /**< \brief Pin Number for PA17 */ 68 #define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ 69 #define PIN_PA18 18 /**< \brief Pin Number for PA18 */ 70 #define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ 71 #define PIN_PA19 19 /**< \brief Pin Number for PA19 */ 72 #define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ 73 #define PIN_PA20 20 /**< \brief Pin Number for PA20 */ 74 #define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ 75 #define PIN_PA21 21 /**< \brief Pin Number for PA21 */ 76 #define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ 77 #define PIN_PA22 22 /**< \brief Pin Number for PA22 */ 78 #define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ 79 #define PIN_PA23 23 /**< \brief Pin Number for PA23 */ 80 #define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ 81 #define PIN_PA24 24 /**< \brief Pin Number for PA24 */ 82 #define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ 83 #define PIN_PA25 25 /**< \brief Pin Number for PA25 */ 84 #define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ 85 #define PIN_PA27 27 /**< \brief Pin Number for PA27 */ 86 #define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ 87 #define PIN_PA30 30 /**< \brief Pin Number for PA30 */ 88 #define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ 89 #define PIN_PA31 31 /**< \brief Pin Number for PA31 */ 90 #define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ 91 #define PIN_PB00 32 /**< \brief Pin Number for PB00 */ 92 #define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ 93 #define PIN_PB01 33 /**< \brief Pin Number for PB01 */ 94 #define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ 95 #define PIN_PB02 34 /**< \brief Pin Number for PB02 */ 96 #define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ 97 #define PIN_PB03 35 /**< \brief Pin Number for PB03 */ 98 #define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ 99 #define PIN_PB04 36 /**< \brief Pin Number for PB04 */ 100 #define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ 101 #define PIN_PB05 37 /**< \brief Pin Number for PB05 */ 102 #define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ 103 #define PIN_PB06 38 /**< \brief Pin Number for PB06 */ 104 #define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ 105 #define PIN_PB07 39 /**< \brief Pin Number for PB07 */ 106 #define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ 107 #define PIN_PB08 40 /**< \brief Pin Number for PB08 */ 108 #define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ 109 #define PIN_PB09 41 /**< \brief Pin Number for PB09 */ 110 #define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ 111 #define PIN_PB10 42 /**< \brief Pin Number for PB10 */ 112 #define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ 113 #define PIN_PB11 43 /**< \brief Pin Number for PB11 */ 114 #define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ 115 #define PIN_PB12 44 /**< \brief Pin Number for PB12 */ 116 #define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ 117 #define PIN_PB13 45 /**< \brief Pin Number for PB13 */ 118 #define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ 119 #define PIN_PB14 46 /**< \brief Pin Number for PB14 */ 120 #define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ 121 #define PIN_PB15 47 /**< \brief Pin Number for PB15 */ 122 #define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ 123 #define PIN_PB16 48 /**< \brief Pin Number for PB16 */ 124 #define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ 125 #define PIN_PB17 49 /**< \brief Pin Number for PB17 */ 126 #define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ 127 #define PIN_PB22 54 /**< \brief Pin Number for PB22 */ 128 #define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ 129 #define PIN_PB23 55 /**< \brief Pin Number for PB23 */ 130 #define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ 131 #define PIN_PB30 62 /**< \brief Pin Number for PB30 */ 132 #define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ 133 #define PIN_PB31 63 /**< \brief Pin Number for PB31 */ 134 #define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ 135 /* ========== PORT definition for CM4 peripheral ========== */ 136 #define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ 137 #define MUX_PA30H_CM4_SWCLK _L_(7) 138 #define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) 139 #define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) 140 #define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ 141 #define MUX_PB30H_CM4_SWO _L_(7) 142 #define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) 143 #define PORT_PB30H_CM4_SWO (_UL_(1) << 30) 144 /* ========== PORT definition for ANAREF peripheral ========== */ 145 #define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ 146 #define MUX_PA03B_ANAREF_VREF0 _L_(1) 147 #define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) 148 #define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) 149 #define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ 150 #define MUX_PA04B_ANAREF_VREF1 _L_(1) 151 #define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) 152 #define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) 153 #define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ 154 #define MUX_PA06B_ANAREF_VREF2 _L_(1) 155 #define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) 156 #define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) 157 /* ========== PORT definition for GCLK peripheral ========== */ 158 #define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ 159 #define MUX_PA30M_GCLK_IO0 _L_(12) 160 #define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) 161 #define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) 162 #define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ 163 #define MUX_PB14M_GCLK_IO0 _L_(12) 164 #define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) 165 #define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) 166 #define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ 167 #define MUX_PA14M_GCLK_IO0 _L_(12) 168 #define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) 169 #define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) 170 #define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ 171 #define MUX_PB22M_GCLK_IO0 _L_(12) 172 #define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) 173 #define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) 174 #define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ 175 #define MUX_PB15M_GCLK_IO1 _L_(12) 176 #define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) 177 #define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) 178 #define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ 179 #define MUX_PA15M_GCLK_IO1 _L_(12) 180 #define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) 181 #define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) 182 #define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ 183 #define MUX_PB23M_GCLK_IO1 _L_(12) 184 #define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) 185 #define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) 186 #define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ 187 #define MUX_PA27M_GCLK_IO1 _L_(12) 188 #define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) 189 #define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) 190 #define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ 191 #define MUX_PA16M_GCLK_IO2 _L_(12) 192 #define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) 193 #define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) 194 #define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ 195 #define MUX_PB16M_GCLK_IO2 _L_(12) 196 #define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) 197 #define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) 198 #define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ 199 #define MUX_PA17M_GCLK_IO3 _L_(12) 200 #define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) 201 #define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) 202 #define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ 203 #define MUX_PB17M_GCLK_IO3 _L_(12) 204 #define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) 205 #define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) 206 #define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ 207 #define MUX_PA10M_GCLK_IO4 _L_(12) 208 #define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) 209 #define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) 210 #define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ 211 #define MUX_PB10M_GCLK_IO4 _L_(12) 212 #define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) 213 #define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) 214 #define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ 215 #define MUX_PA11M_GCLK_IO5 _L_(12) 216 #define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) 217 #define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) 218 #define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ 219 #define MUX_PB11M_GCLK_IO5 _L_(12) 220 #define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) 221 #define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) 222 #define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ 223 #define MUX_PB12M_GCLK_IO6 _L_(12) 224 #define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) 225 #define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) 226 #define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ 227 #define MUX_PB13M_GCLK_IO7 _L_(12) 228 #define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) 229 #define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) 230 /* ========== PORT definition for EIC peripheral ========== */ 231 #define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ 232 #define MUX_PA00A_EIC_EXTINT0 _L_(0) 233 #define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) 234 #define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) 235 #define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ 236 #define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ 237 #define MUX_PA16A_EIC_EXTINT0 _L_(0) 238 #define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) 239 #define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) 240 #define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ 241 #define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ 242 #define MUX_PB00A_EIC_EXTINT0 _L_(0) 243 #define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) 244 #define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) 245 #define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ 246 #define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ 247 #define MUX_PB16A_EIC_EXTINT0 _L_(0) 248 #define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) 249 #define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) 250 #define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ 251 #define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ 252 #define MUX_PA01A_EIC_EXTINT1 _L_(0) 253 #define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) 254 #define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) 255 #define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ 256 #define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ 257 #define MUX_PA17A_EIC_EXTINT1 _L_(0) 258 #define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) 259 #define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) 260 #define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ 261 #define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ 262 #define MUX_PB01A_EIC_EXTINT1 _L_(0) 263 #define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) 264 #define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) 265 #define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ 266 #define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ 267 #define MUX_PB17A_EIC_EXTINT1 _L_(0) 268 #define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) 269 #define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) 270 #define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ 271 #define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ 272 #define MUX_PA02A_EIC_EXTINT2 _L_(0) 273 #define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) 274 #define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) 275 #define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ 276 #define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ 277 #define MUX_PA18A_EIC_EXTINT2 _L_(0) 278 #define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) 279 #define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) 280 #define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ 281 #define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ 282 #define MUX_PB02A_EIC_EXTINT2 _L_(0) 283 #define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) 284 #define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) 285 #define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ 286 #define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ 287 #define MUX_PA03A_EIC_EXTINT3 _L_(0) 288 #define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) 289 #define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) 290 #define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ 291 #define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ 292 #define MUX_PA19A_EIC_EXTINT3 _L_(0) 293 #define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) 294 #define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) 295 #define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ 296 #define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ 297 #define MUX_PB03A_EIC_EXTINT3 _L_(0) 298 #define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) 299 #define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) 300 #define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ 301 #define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ 302 #define MUX_PA04A_EIC_EXTINT4 _L_(0) 303 #define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) 304 #define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) 305 #define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ 306 #define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ 307 #define MUX_PA20A_EIC_EXTINT4 _L_(0) 308 #define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) 309 #define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) 310 #define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ 311 #define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ 312 #define MUX_PB04A_EIC_EXTINT4 _L_(0) 313 #define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) 314 #define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) 315 #define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ 316 #define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ 317 #define MUX_PA05A_EIC_EXTINT5 _L_(0) 318 #define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) 319 #define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) 320 #define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ 321 #define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ 322 #define MUX_PA21A_EIC_EXTINT5 _L_(0) 323 #define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) 324 #define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) 325 #define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ 326 #define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ 327 #define MUX_PB05A_EIC_EXTINT5 _L_(0) 328 #define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) 329 #define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) 330 #define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ 331 #define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ 332 #define MUX_PA06A_EIC_EXTINT6 _L_(0) 333 #define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) 334 #define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) 335 #define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ 336 #define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ 337 #define MUX_PA22A_EIC_EXTINT6 _L_(0) 338 #define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) 339 #define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) 340 #define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ 341 #define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ 342 #define MUX_PB06A_EIC_EXTINT6 _L_(0) 343 #define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) 344 #define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) 345 #define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ 346 #define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ 347 #define MUX_PB22A_EIC_EXTINT6 _L_(0) 348 #define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) 349 #define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) 350 #define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ 351 #define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ 352 #define MUX_PA07A_EIC_EXTINT7 _L_(0) 353 #define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) 354 #define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) 355 #define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ 356 #define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ 357 #define MUX_PA23A_EIC_EXTINT7 _L_(0) 358 #define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) 359 #define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) 360 #define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ 361 #define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ 362 #define MUX_PB07A_EIC_EXTINT7 _L_(0) 363 #define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) 364 #define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) 365 #define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ 366 #define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ 367 #define MUX_PB23A_EIC_EXTINT7 _L_(0) 368 #define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) 369 #define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) 370 #define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ 371 #define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ 372 #define MUX_PA24A_EIC_EXTINT8 _L_(0) 373 #define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) 374 #define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) 375 #define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ 376 #define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ 377 #define MUX_PB08A_EIC_EXTINT8 _L_(0) 378 #define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) 379 #define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) 380 #define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ 381 #define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ 382 #define MUX_PA09A_EIC_EXTINT9 _L_(0) 383 #define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) 384 #define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) 385 #define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ 386 #define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ 387 #define MUX_PA25A_EIC_EXTINT9 _L_(0) 388 #define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) 389 #define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) 390 #define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ 391 #define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ 392 #define MUX_PB09A_EIC_EXTINT9 _L_(0) 393 #define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) 394 #define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) 395 #define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ 396 #define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ 397 #define MUX_PA10A_EIC_EXTINT10 _L_(0) 398 #define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) 399 #define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) 400 #define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ 401 #define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ 402 #define MUX_PB10A_EIC_EXTINT10 _L_(0) 403 #define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) 404 #define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) 405 #define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ 406 #define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ 407 #define MUX_PA11A_EIC_EXTINT11 _L_(0) 408 #define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) 409 #define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) 410 #define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ 411 #define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ 412 #define MUX_PA27A_EIC_EXTINT11 _L_(0) 413 #define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) 414 #define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) 415 #define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ 416 #define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ 417 #define MUX_PB11A_EIC_EXTINT11 _L_(0) 418 #define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) 419 #define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) 420 #define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ 421 #define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ 422 #define MUX_PA12A_EIC_EXTINT12 _L_(0) 423 #define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) 424 #define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) 425 #define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ 426 #define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ 427 #define MUX_PB12A_EIC_EXTINT12 _L_(0) 428 #define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) 429 #define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) 430 #define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ 431 #define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ 432 #define MUX_PA13A_EIC_EXTINT13 _L_(0) 433 #define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) 434 #define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) 435 #define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ 436 #define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ 437 #define MUX_PB13A_EIC_EXTINT13 _L_(0) 438 #define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) 439 #define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) 440 #define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ 441 #define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ 442 #define MUX_PA30A_EIC_EXTINT14 _L_(0) 443 #define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) 444 #define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) 445 #define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ 446 #define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ 447 #define MUX_PB14A_EIC_EXTINT14 _L_(0) 448 #define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) 449 #define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) 450 #define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ 451 #define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ 452 #define MUX_PB30A_EIC_EXTINT14 _L_(0) 453 #define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) 454 #define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) 455 #define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ 456 #define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ 457 #define MUX_PA14A_EIC_EXTINT14 _L_(0) 458 #define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) 459 #define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) 460 #define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ 461 #define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ 462 #define MUX_PA15A_EIC_EXTINT15 _L_(0) 463 #define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) 464 #define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) 465 #define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ 466 #define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ 467 #define MUX_PA31A_EIC_EXTINT15 _L_(0) 468 #define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) 469 #define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) 470 #define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ 471 #define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ 472 #define MUX_PB15A_EIC_EXTINT15 _L_(0) 473 #define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) 474 #define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) 475 #define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ 476 #define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ 477 #define MUX_PB31A_EIC_EXTINT15 _L_(0) 478 #define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) 479 #define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) 480 #define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ 481 #define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ 482 #define MUX_PA08A_EIC_NMI _L_(0) 483 #define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) 484 #define PORT_PA08A_EIC_NMI (_UL_(1) << 8) 485 /* ========== PORT definition for SERCOM0 peripheral ========== */ 486 #define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ 487 #define MUX_PA04D_SERCOM0_PAD0 _L_(3) 488 #define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) 489 #define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) 490 #define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ 491 #define MUX_PA08C_SERCOM0_PAD0 _L_(2) 492 #define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) 493 #define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) 494 #define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ 495 #define MUX_PA05D_SERCOM0_PAD1 _L_(3) 496 #define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) 497 #define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) 498 #define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ 499 #define MUX_PA09C_SERCOM0_PAD1 _L_(2) 500 #define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) 501 #define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) 502 #define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ 503 #define MUX_PA06D_SERCOM0_PAD2 _L_(3) 504 #define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) 505 #define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) 506 #define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ 507 #define MUX_PA10C_SERCOM0_PAD2 _L_(2) 508 #define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) 509 #define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) 510 #define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ 511 #define MUX_PA07D_SERCOM0_PAD3 _L_(3) 512 #define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) 513 #define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) 514 #define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ 515 #define MUX_PA11C_SERCOM0_PAD3 _L_(2) 516 #define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) 517 #define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) 518 /* ========== PORT definition for SERCOM1 peripheral ========== */ 519 #define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ 520 #define MUX_PA00D_SERCOM1_PAD0 _L_(3) 521 #define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) 522 #define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) 523 #define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ 524 #define MUX_PA16C_SERCOM1_PAD0 _L_(2) 525 #define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) 526 #define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) 527 #define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ 528 #define MUX_PA01D_SERCOM1_PAD1 _L_(3) 529 #define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) 530 #define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) 531 #define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ 532 #define MUX_PA17C_SERCOM1_PAD1 _L_(2) 533 #define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) 534 #define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) 535 #define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ 536 #define MUX_PA30D_SERCOM1_PAD2 _L_(3) 537 #define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) 538 #define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) 539 #define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ 540 #define MUX_PA18C_SERCOM1_PAD2 _L_(2) 541 #define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) 542 #define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) 543 #define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ 544 #define MUX_PB22C_SERCOM1_PAD2 _L_(2) 545 #define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) 546 #define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) 547 #define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ 548 #define MUX_PA31D_SERCOM1_PAD3 _L_(3) 549 #define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) 550 #define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) 551 #define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ 552 #define MUX_PA19C_SERCOM1_PAD3 _L_(2) 553 #define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) 554 #define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) 555 #define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ 556 #define MUX_PB23C_SERCOM1_PAD3 _L_(2) 557 #define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) 558 #define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) 559 /* ========== PORT definition for TC0 peripheral ========== */ 560 #define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ 561 #define MUX_PA04E_TC0_WO0 _L_(4) 562 #define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) 563 #define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) 564 #define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ 565 #define MUX_PA08E_TC0_WO0 _L_(4) 566 #define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) 567 #define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) 568 #define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ 569 #define MUX_PB30E_TC0_WO0 _L_(4) 570 #define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) 571 #define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) 572 #define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ 573 #define MUX_PA05E_TC0_WO1 _L_(4) 574 #define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) 575 #define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) 576 #define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ 577 #define MUX_PA09E_TC0_WO1 _L_(4) 578 #define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) 579 #define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) 580 #define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ 581 #define MUX_PB31E_TC0_WO1 _L_(4) 582 #define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) 583 #define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) 584 /* ========== PORT definition for TC1 peripheral ========== */ 585 #define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ 586 #define MUX_PA06E_TC1_WO0 _L_(4) 587 #define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) 588 #define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) 589 #define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ 590 #define MUX_PA10E_TC1_WO0 _L_(4) 591 #define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) 592 #define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) 593 #define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ 594 #define MUX_PA07E_TC1_WO1 _L_(4) 595 #define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) 596 #define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) 597 #define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ 598 #define MUX_PA11E_TC1_WO1 _L_(4) 599 #define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) 600 #define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) 601 /* ========== PORT definition for USB peripheral ========== */ 602 #define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ 603 #define MUX_PA24H_USB_DM _L_(7) 604 #define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) 605 #define PORT_PA24H_USB_DM (_UL_(1) << 24) 606 #define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ 607 #define MUX_PA25H_USB_DP _L_(7) 608 #define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) 609 #define PORT_PA25H_USB_DP (_UL_(1) << 25) 610 #define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ 611 #define MUX_PA23H_USB_SOF_1KHZ _L_(7) 612 #define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) 613 #define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) 614 #define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ 615 #define MUX_PB22H_USB_SOF_1KHZ _L_(7) 616 #define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) 617 #define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) 618 /* ========== PORT definition for SERCOM2 peripheral ========== */ 619 #define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ 620 #define MUX_PA09D_SERCOM2_PAD0 _L_(3) 621 #define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) 622 #define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) 623 #define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ 624 #define MUX_PA12C_SERCOM2_PAD0 _L_(2) 625 #define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) 626 #define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) 627 #define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ 628 #define MUX_PA08D_SERCOM2_PAD1 _L_(3) 629 #define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) 630 #define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) 631 #define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ 632 #define MUX_PA13C_SERCOM2_PAD1 _L_(2) 633 #define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) 634 #define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) 635 #define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ 636 #define MUX_PA10D_SERCOM2_PAD2 _L_(3) 637 #define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) 638 #define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) 639 #define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ 640 #define MUX_PA14C_SERCOM2_PAD2 _L_(2) 641 #define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) 642 #define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) 643 #define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ 644 #define MUX_PA11D_SERCOM2_PAD3 _L_(3) 645 #define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) 646 #define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) 647 #define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ 648 #define MUX_PA15C_SERCOM2_PAD3 _L_(2) 649 #define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) 650 #define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) 651 /* ========== PORT definition for SERCOM3 peripheral ========== */ 652 #define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ 653 #define MUX_PA17D_SERCOM3_PAD0 _L_(3) 654 #define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) 655 #define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) 656 #define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ 657 #define MUX_PA22C_SERCOM3_PAD0 _L_(2) 658 #define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) 659 #define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) 660 #define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ 661 #define MUX_PA16D_SERCOM3_PAD1 _L_(3) 662 #define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) 663 #define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) 664 #define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ 665 #define MUX_PA23C_SERCOM3_PAD1 _L_(2) 666 #define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) 667 #define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) 668 #define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ 669 #define MUX_PA18D_SERCOM3_PAD2 _L_(3) 670 #define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) 671 #define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) 672 #define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ 673 #define MUX_PA20D_SERCOM3_PAD2 _L_(3) 674 #define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) 675 #define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) 676 #define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ 677 #define MUX_PA24C_SERCOM3_PAD2 _L_(2) 678 #define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) 679 #define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) 680 #define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ 681 #define MUX_PA19D_SERCOM3_PAD3 _L_(3) 682 #define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) 683 #define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) 684 #define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ 685 #define MUX_PA21D_SERCOM3_PAD3 _L_(3) 686 #define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) 687 #define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) 688 #define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ 689 #define MUX_PA25C_SERCOM3_PAD3 _L_(2) 690 #define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) 691 #define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) 692 /* ========== PORT definition for TCC0 peripheral ========== */ 693 #define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ 694 #define MUX_PA20G_TCC0_WO0 _L_(6) 695 #define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) 696 #define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) 697 #define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ 698 #define MUX_PB12G_TCC0_WO0 _L_(6) 699 #define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) 700 #define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) 701 #define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ 702 #define MUX_PA08F_TCC0_WO0 _L_(5) 703 #define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) 704 #define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) 705 #define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ 706 #define MUX_PA21G_TCC0_WO1 _L_(6) 707 #define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) 708 #define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) 709 #define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ 710 #define MUX_PB13G_TCC0_WO1 _L_(6) 711 #define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) 712 #define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) 713 #define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ 714 #define MUX_PA09F_TCC0_WO1 _L_(5) 715 #define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) 716 #define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) 717 #define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ 718 #define MUX_PA22G_TCC0_WO2 _L_(6) 719 #define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) 720 #define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) 721 #define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ 722 #define MUX_PB14G_TCC0_WO2 _L_(6) 723 #define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) 724 #define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) 725 #define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ 726 #define MUX_PA10F_TCC0_WO2 _L_(5) 727 #define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) 728 #define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) 729 #define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ 730 #define MUX_PA23G_TCC0_WO3 _L_(6) 731 #define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) 732 #define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) 733 #define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ 734 #define MUX_PB15G_TCC0_WO3 _L_(6) 735 #define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) 736 #define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) 737 #define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ 738 #define MUX_PA11F_TCC0_WO3 _L_(5) 739 #define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) 740 #define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) 741 #define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ 742 #define MUX_PA16G_TCC0_WO4 _L_(6) 743 #define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) 744 #define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) 745 #define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ 746 #define MUX_PB16G_TCC0_WO4 _L_(6) 747 #define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) 748 #define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) 749 #define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ 750 #define MUX_PB10F_TCC0_WO4 _L_(5) 751 #define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) 752 #define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) 753 #define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ 754 #define MUX_PA17G_TCC0_WO5 _L_(6) 755 #define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) 756 #define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) 757 #define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ 758 #define MUX_PB17G_TCC0_WO5 _L_(6) 759 #define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) 760 #define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) 761 #define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ 762 #define MUX_PB11F_TCC0_WO5 _L_(5) 763 #define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) 764 #define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) 765 #define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ 766 #define MUX_PA18G_TCC0_WO6 _L_(6) 767 #define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) 768 #define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) 769 #define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ 770 #define MUX_PB30G_TCC0_WO6 _L_(6) 771 #define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) 772 #define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) 773 #define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ 774 #define MUX_PA12F_TCC0_WO6 _L_(5) 775 #define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) 776 #define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) 777 #define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ 778 #define MUX_PA19G_TCC0_WO7 _L_(6) 779 #define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) 780 #define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) 781 #define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ 782 #define MUX_PB31G_TCC0_WO7 _L_(6) 783 #define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) 784 #define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) 785 #define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ 786 #define MUX_PA13F_TCC0_WO7 _L_(5) 787 #define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) 788 #define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) 789 /* ========== PORT definition for TCC1 peripheral ========== */ 790 #define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ 791 #define MUX_PB10G_TCC1_WO0 _L_(6) 792 #define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) 793 #define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) 794 #define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ 795 #define MUX_PA16F_TCC1_WO0 _L_(5) 796 #define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) 797 #define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) 798 #define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ 799 #define MUX_PB11G_TCC1_WO1 _L_(6) 800 #define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) 801 #define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) 802 #define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ 803 #define MUX_PA17F_TCC1_WO1 _L_(5) 804 #define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) 805 #define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) 806 #define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ 807 #define MUX_PA12G_TCC1_WO2 _L_(6) 808 #define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) 809 #define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) 810 #define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ 811 #define MUX_PA14G_TCC1_WO2 _L_(6) 812 #define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) 813 #define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) 814 #define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ 815 #define MUX_PA18F_TCC1_WO2 _L_(5) 816 #define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) 817 #define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) 818 #define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ 819 #define MUX_PA13G_TCC1_WO3 _L_(6) 820 #define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) 821 #define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) 822 #define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ 823 #define MUX_PA15G_TCC1_WO3 _L_(6) 824 #define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) 825 #define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) 826 #define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ 827 #define MUX_PA19F_TCC1_WO3 _L_(5) 828 #define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) 829 #define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) 830 #define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ 831 #define MUX_PA08G_TCC1_WO4 _L_(6) 832 #define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) 833 #define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) 834 #define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ 835 #define MUX_PA20F_TCC1_WO4 _L_(5) 836 #define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) 837 #define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) 838 #define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ 839 #define MUX_PA09G_TCC1_WO5 _L_(6) 840 #define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) 841 #define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) 842 #define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ 843 #define MUX_PA21F_TCC1_WO5 _L_(5) 844 #define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) 845 #define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) 846 #define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ 847 #define MUX_PA10G_TCC1_WO6 _L_(6) 848 #define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) 849 #define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) 850 #define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ 851 #define MUX_PA22F_TCC1_WO6 _L_(5) 852 #define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) 853 #define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) 854 #define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ 855 #define MUX_PA11G_TCC1_WO7 _L_(6) 856 #define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) 857 #define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) 858 #define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ 859 #define MUX_PA23F_TCC1_WO7 _L_(5) 860 #define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) 861 #define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) 862 /* ========== PORT definition for TC2 peripheral ========== */ 863 #define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ 864 #define MUX_PA12E_TC2_WO0 _L_(4) 865 #define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) 866 #define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) 867 #define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ 868 #define MUX_PA16E_TC2_WO0 _L_(4) 869 #define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) 870 #define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) 871 #define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ 872 #define MUX_PA00E_TC2_WO0 _L_(4) 873 #define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) 874 #define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) 875 #define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ 876 #define MUX_PA01E_TC2_WO1 _L_(4) 877 #define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) 878 #define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) 879 #define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ 880 #define MUX_PA13E_TC2_WO1 _L_(4) 881 #define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) 882 #define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) 883 #define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ 884 #define MUX_PA17E_TC2_WO1 _L_(4) 885 #define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) 886 #define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) 887 /* ========== PORT definition for TC3 peripheral ========== */ 888 #define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ 889 #define MUX_PA18E_TC3_WO0 _L_(4) 890 #define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) 891 #define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) 892 #define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ 893 #define MUX_PA14E_TC3_WO0 _L_(4) 894 #define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) 895 #define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) 896 #define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ 897 #define MUX_PA15E_TC3_WO1 _L_(4) 898 #define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) 899 #define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) 900 #define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ 901 #define MUX_PA19E_TC3_WO1 _L_(4) 902 #define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) 903 #define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) 904 /* ========== PORT definition for TCC2 peripheral ========== */ 905 #define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ 906 #define MUX_PA14F_TCC2_WO0 _L_(5) 907 #define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) 908 #define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) 909 #define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ 910 #define MUX_PA30F_TCC2_WO0 _L_(5) 911 #define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) 912 #define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) 913 #define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ 914 #define MUX_PA15F_TCC2_WO1 _L_(5) 915 #define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) 916 #define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) 917 #define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ 918 #define MUX_PA31F_TCC2_WO1 _L_(5) 919 #define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) 920 #define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) 921 #define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ 922 #define MUX_PA24F_TCC2_WO2 _L_(5) 923 #define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) 924 #define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) 925 #define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ 926 #define MUX_PB02F_TCC2_WO2 _L_(5) 927 #define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) 928 #define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) 929 /* ========== PORT definition for TCC3 peripheral ========== */ 930 #define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ 931 #define MUX_PB12F_TCC3_WO0 _L_(5) 932 #define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) 933 #define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) 934 #define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ 935 #define MUX_PB16F_TCC3_WO0 _L_(5) 936 #define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) 937 #define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) 938 #define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ 939 #define MUX_PB13F_TCC3_WO1 _L_(5) 940 #define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) 941 #define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) 942 #define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ 943 #define MUX_PB17F_TCC3_WO1 _L_(5) 944 #define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) 945 #define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) 946 /* ========== PORT definition for TC4 peripheral ========== */ 947 #define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ 948 #define MUX_PA22E_TC4_WO0 _L_(4) 949 #define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) 950 #define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) 951 #define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ 952 #define MUX_PB08E_TC4_WO0 _L_(4) 953 #define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) 954 #define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) 955 #define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ 956 #define MUX_PB12E_TC4_WO0 _L_(4) 957 #define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) 958 #define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) 959 #define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ 960 #define MUX_PA23E_TC4_WO1 _L_(4) 961 #define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) 962 #define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) 963 #define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ 964 #define MUX_PB09E_TC4_WO1 _L_(4) 965 #define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) 966 #define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) 967 #define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ 968 #define MUX_PB13E_TC4_WO1 _L_(4) 969 #define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) 970 #define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) 971 /* ========== PORT definition for TC5 peripheral ========== */ 972 #define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ 973 #define MUX_PA24E_TC5_WO0 _L_(4) 974 #define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) 975 #define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) 976 #define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ 977 #define MUX_PB10E_TC5_WO0 _L_(4) 978 #define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) 979 #define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) 980 #define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ 981 #define MUX_PB14E_TC5_WO0 _L_(4) 982 #define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) 983 #define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) 984 #define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ 985 #define MUX_PA25E_TC5_WO1 _L_(4) 986 #define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) 987 #define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) 988 #define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ 989 #define MUX_PB11E_TC5_WO1 _L_(4) 990 #define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) 991 #define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) 992 #define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ 993 #define MUX_PB15E_TC5_WO1 _L_(4) 994 #define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) 995 #define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) 996 /* ========== PORT definition for PDEC peripheral ========== */ 997 #define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ 998 #define MUX_PB23G_PDEC_QDI0 _L_(6) 999 #define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) 1000 #define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) 1001 #define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ 1002 #define MUX_PA24G_PDEC_QDI0 _L_(6) 1003 #define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) 1004 #define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) 1005 #define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ 1006 #define MUX_PA25G_PDEC_QDI1 _L_(6) 1007 #define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) 1008 #define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) 1009 #define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ 1010 #define MUX_PB22G_PDEC_QDI2 _L_(6) 1011 #define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) 1012 #define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) 1013 /* ========== PORT definition for AC peripheral ========== */ 1014 #define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ 1015 #define MUX_PA04B_AC_AIN0 _L_(1) 1016 #define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) 1017 #define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) 1018 #define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ 1019 #define MUX_PA05B_AC_AIN1 _L_(1) 1020 #define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) 1021 #define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) 1022 #define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ 1023 #define MUX_PA06B_AC_AIN2 _L_(1) 1024 #define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) 1025 #define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) 1026 #define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ 1027 #define MUX_PA07B_AC_AIN3 _L_(1) 1028 #define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) 1029 #define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) 1030 #define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ 1031 #define MUX_PA12M_AC_CMP0 _L_(12) 1032 #define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) 1033 #define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) 1034 #define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ 1035 #define MUX_PA18M_AC_CMP0 _L_(12) 1036 #define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) 1037 #define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) 1038 #define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ 1039 #define MUX_PA13M_AC_CMP1 _L_(12) 1040 #define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) 1041 #define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) 1042 #define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ 1043 #define MUX_PA19M_AC_CMP1 _L_(12) 1044 #define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) 1045 #define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) 1046 /* ========== PORT definition for QSPI peripheral ========== */ 1047 #define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ 1048 #define MUX_PB11H_QSPI_CS _L_(7) 1049 #define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) 1050 #define PORT_PB11H_QSPI_CS (_UL_(1) << 11) 1051 #define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ 1052 #define MUX_PA08H_QSPI_DATA0 _L_(7) 1053 #define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) 1054 #define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) 1055 #define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ 1056 #define MUX_PA09H_QSPI_DATA1 _L_(7) 1057 #define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) 1058 #define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) 1059 #define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ 1060 #define MUX_PA10H_QSPI_DATA2 _L_(7) 1061 #define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) 1062 #define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) 1063 #define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ 1064 #define MUX_PA11H_QSPI_DATA3 _L_(7) 1065 #define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) 1066 #define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) 1067 #define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ 1068 #define MUX_PB10H_QSPI_SCK _L_(7) 1069 #define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) 1070 #define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) 1071 /* ========== PORT definition for CCL peripheral ========== */ 1072 #define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ 1073 #define MUX_PA04N_CCL_IN0 _L_(13) 1074 #define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) 1075 #define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) 1076 #define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ 1077 #define MUX_PA16N_CCL_IN0 _L_(13) 1078 #define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) 1079 #define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) 1080 #define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ 1081 #define MUX_PB22N_CCL_IN0 _L_(13) 1082 #define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) 1083 #define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) 1084 #define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ 1085 #define MUX_PA05N_CCL_IN1 _L_(13) 1086 #define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) 1087 #define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) 1088 #define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ 1089 #define MUX_PA17N_CCL_IN1 _L_(13) 1090 #define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) 1091 #define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) 1092 #define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ 1093 #define MUX_PB00N_CCL_IN1 _L_(13) 1094 #define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) 1095 #define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) 1096 #define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ 1097 #define MUX_PA06N_CCL_IN2 _L_(13) 1098 #define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) 1099 #define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) 1100 #define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ 1101 #define MUX_PA18N_CCL_IN2 _L_(13) 1102 #define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) 1103 #define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) 1104 #define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ 1105 #define MUX_PB01N_CCL_IN2 _L_(13) 1106 #define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) 1107 #define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) 1108 #define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ 1109 #define MUX_PA08N_CCL_IN3 _L_(13) 1110 #define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) 1111 #define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) 1112 #define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ 1113 #define MUX_PA30N_CCL_IN3 _L_(13) 1114 #define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) 1115 #define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) 1116 #define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ 1117 #define MUX_PA09N_CCL_IN4 _L_(13) 1118 #define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) 1119 #define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) 1120 #define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ 1121 #define MUX_PA10N_CCL_IN5 _L_(13) 1122 #define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) 1123 #define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) 1124 #define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ 1125 #define MUX_PA22N_CCL_IN6 _L_(13) 1126 #define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) 1127 #define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) 1128 #define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ 1129 #define MUX_PB06N_CCL_IN6 _L_(13) 1130 #define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) 1131 #define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) 1132 #define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ 1133 #define MUX_PA23N_CCL_IN7 _L_(13) 1134 #define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) 1135 #define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) 1136 #define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ 1137 #define MUX_PB07N_CCL_IN7 _L_(13) 1138 #define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) 1139 #define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) 1140 #define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ 1141 #define MUX_PA24N_CCL_IN8 _L_(13) 1142 #define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) 1143 #define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) 1144 #define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ 1145 #define MUX_PB08N_CCL_IN8 _L_(13) 1146 #define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) 1147 #define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) 1148 #define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ 1149 #define MUX_PB14N_CCL_IN9 _L_(13) 1150 #define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) 1151 #define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) 1152 #define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ 1153 #define MUX_PB15N_CCL_IN10 _L_(13) 1154 #define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) 1155 #define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) 1156 #define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ 1157 #define MUX_PB10N_CCL_IN11 _L_(13) 1158 #define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) 1159 #define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) 1160 #define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ 1161 #define MUX_PB16N_CCL_IN11 _L_(13) 1162 #define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) 1163 #define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) 1164 #define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ 1165 #define MUX_PA07N_CCL_OUT0 _L_(13) 1166 #define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) 1167 #define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) 1168 #define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ 1169 #define MUX_PA19N_CCL_OUT0 _L_(13) 1170 #define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) 1171 #define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) 1172 #define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ 1173 #define MUX_PB02N_CCL_OUT0 _L_(13) 1174 #define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) 1175 #define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) 1176 #define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ 1177 #define MUX_PB23N_CCL_OUT0 _L_(13) 1178 #define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) 1179 #define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) 1180 #define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ 1181 #define MUX_PA11N_CCL_OUT1 _L_(13) 1182 #define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) 1183 #define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) 1184 #define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ 1185 #define MUX_PA31N_CCL_OUT1 _L_(13) 1186 #define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) 1187 #define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) 1188 #define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ 1189 #define MUX_PB11N_CCL_OUT1 _L_(13) 1190 #define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) 1191 #define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) 1192 #define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ 1193 #define MUX_PA25N_CCL_OUT2 _L_(13) 1194 #define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) 1195 #define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) 1196 #define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ 1197 #define MUX_PB09N_CCL_OUT2 _L_(13) 1198 #define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) 1199 #define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) 1200 #define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ 1201 #define MUX_PB17N_CCL_OUT3 _L_(13) 1202 #define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) 1203 #define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) 1204 /* ========== PORT definition for SERCOM4 peripheral ========== */ 1205 #define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ 1206 #define MUX_PA13D_SERCOM4_PAD0 _L_(3) 1207 #define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) 1208 #define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) 1209 #define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ 1210 #define MUX_PB08D_SERCOM4_PAD0 _L_(3) 1211 #define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) 1212 #define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) 1213 #define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ 1214 #define MUX_PB12C_SERCOM4_PAD0 _L_(2) 1215 #define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) 1216 #define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) 1217 #define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ 1218 #define MUX_PA12D_SERCOM4_PAD1 _L_(3) 1219 #define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) 1220 #define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) 1221 #define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ 1222 #define MUX_PB09D_SERCOM4_PAD1 _L_(3) 1223 #define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) 1224 #define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) 1225 #define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ 1226 #define MUX_PB13C_SERCOM4_PAD1 _L_(2) 1227 #define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) 1228 #define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) 1229 #define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ 1230 #define MUX_PA14D_SERCOM4_PAD2 _L_(3) 1231 #define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) 1232 #define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) 1233 #define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ 1234 #define MUX_PB10D_SERCOM4_PAD2 _L_(3) 1235 #define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) 1236 #define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) 1237 #define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ 1238 #define MUX_PB14C_SERCOM4_PAD2 _L_(2) 1239 #define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) 1240 #define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) 1241 #define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ 1242 #define MUX_PB11D_SERCOM4_PAD3 _L_(3) 1243 #define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) 1244 #define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) 1245 #define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ 1246 #define MUX_PA15D_SERCOM4_PAD3 _L_(3) 1247 #define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) 1248 #define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) 1249 #define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ 1250 #define MUX_PB15C_SERCOM4_PAD3 _L_(2) 1251 #define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) 1252 #define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) 1253 /* ========== PORT definition for SERCOM5 peripheral ========== */ 1254 #define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ 1255 #define MUX_PA23D_SERCOM5_PAD0 _L_(3) 1256 #define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) 1257 #define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) 1258 #define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ 1259 #define MUX_PB02D_SERCOM5_PAD0 _L_(3) 1260 #define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) 1261 #define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) 1262 #define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ 1263 #define MUX_PB31D_SERCOM5_PAD0 _L_(3) 1264 #define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) 1265 #define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) 1266 #define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ 1267 #define MUX_PB16C_SERCOM5_PAD0 _L_(2) 1268 #define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) 1269 #define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) 1270 #define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ 1271 #define MUX_PA22D_SERCOM5_PAD1 _L_(3) 1272 #define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) 1273 #define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) 1274 #define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ 1275 #define MUX_PB03D_SERCOM5_PAD1 _L_(3) 1276 #define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) 1277 #define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) 1278 #define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ 1279 #define MUX_PB30D_SERCOM5_PAD1 _L_(3) 1280 #define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) 1281 #define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) 1282 #define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ 1283 #define MUX_PB17C_SERCOM5_PAD1 _L_(2) 1284 #define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) 1285 #define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) 1286 #define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ 1287 #define MUX_PA24D_SERCOM5_PAD2 _L_(3) 1288 #define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) 1289 #define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) 1290 #define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ 1291 #define MUX_PB00D_SERCOM5_PAD2 _L_(3) 1292 #define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) 1293 #define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) 1294 #define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ 1295 #define MUX_PB22D_SERCOM5_PAD2 _L_(3) 1296 #define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) 1297 #define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) 1298 #define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ 1299 #define MUX_PA20C_SERCOM5_PAD2 _L_(2) 1300 #define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) 1301 #define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) 1302 #define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ 1303 #define MUX_PA25D_SERCOM5_PAD3 _L_(3) 1304 #define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) 1305 #define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) 1306 #define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ 1307 #define MUX_PB01D_SERCOM5_PAD3 _L_(3) 1308 #define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) 1309 #define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) 1310 #define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ 1311 #define MUX_PB23D_SERCOM5_PAD3 _L_(3) 1312 #define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) 1313 #define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) 1314 #define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ 1315 #define MUX_PA21C_SERCOM5_PAD3 _L_(2) 1316 #define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) 1317 #define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) 1318 /* ========== PORT definition for TCC4 peripheral ========== */ 1319 #define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ 1320 #define MUX_PB14F_TCC4_WO0 _L_(5) 1321 #define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) 1322 #define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) 1323 #define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ 1324 #define MUX_PB30F_TCC4_WO0 _L_(5) 1325 #define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) 1326 #define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) 1327 #define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ 1328 #define MUX_PB15F_TCC4_WO1 _L_(5) 1329 #define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) 1330 #define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) 1331 #define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ 1332 #define MUX_PB31F_TCC4_WO1 _L_(5) 1333 #define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) 1334 #define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) 1335 /* ========== PORT definition for ADC0 peripheral ========== */ 1336 #define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ 1337 #define MUX_PA02B_ADC0_AIN0 _L_(1) 1338 #define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) 1339 #define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) 1340 #define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ 1341 #define MUX_PA03B_ADC0_AIN1 _L_(1) 1342 #define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) 1343 #define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) 1344 #define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ 1345 #define MUX_PB08B_ADC0_AIN2 _L_(1) 1346 #define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) 1347 #define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) 1348 #define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ 1349 #define MUX_PB09B_ADC0_AIN3 _L_(1) 1350 #define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) 1351 #define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) 1352 #define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ 1353 #define MUX_PA04B_ADC0_AIN4 _L_(1) 1354 #define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) 1355 #define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) 1356 #define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ 1357 #define MUX_PA05B_ADC0_AIN5 _L_(1) 1358 #define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) 1359 #define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) 1360 #define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ 1361 #define MUX_PA06B_ADC0_AIN6 _L_(1) 1362 #define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) 1363 #define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) 1364 #define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ 1365 #define MUX_PA07B_ADC0_AIN7 _L_(1) 1366 #define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) 1367 #define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) 1368 #define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ 1369 #define MUX_PA08B_ADC0_AIN8 _L_(1) 1370 #define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) 1371 #define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) 1372 #define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ 1373 #define MUX_PA09B_ADC0_AIN9 _L_(1) 1374 #define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) 1375 #define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) 1376 #define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ 1377 #define MUX_PA10B_ADC0_AIN10 _L_(1) 1378 #define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) 1379 #define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) 1380 #define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ 1381 #define MUX_PA11B_ADC0_AIN11 _L_(1) 1382 #define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) 1383 #define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) 1384 #define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ 1385 #define MUX_PB00B_ADC0_AIN12 _L_(1) 1386 #define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) 1387 #define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) 1388 #define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ 1389 #define MUX_PB01B_ADC0_AIN13 _L_(1) 1390 #define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) 1391 #define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) 1392 #define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ 1393 #define MUX_PB02B_ADC0_AIN14 _L_(1) 1394 #define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) 1395 #define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) 1396 #define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ 1397 #define MUX_PB03B_ADC0_AIN15 _L_(1) 1398 #define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) 1399 #define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) 1400 #define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ 1401 #define MUX_PA03O_ADC0_DRV0 _L_(14) 1402 #define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) 1403 #define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) 1404 #define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ 1405 #define MUX_PB08O_ADC0_DRV1 _L_(14) 1406 #define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) 1407 #define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) 1408 #define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ 1409 #define MUX_PB09O_ADC0_DRV2 _L_(14) 1410 #define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) 1411 #define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) 1412 #define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ 1413 #define MUX_PA04O_ADC0_DRV3 _L_(14) 1414 #define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) 1415 #define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) 1416 #define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ 1417 #define MUX_PA06O_ADC0_DRV4 _L_(14) 1418 #define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) 1419 #define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) 1420 #define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ 1421 #define MUX_PA07O_ADC0_DRV5 _L_(14) 1422 #define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) 1423 #define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) 1424 #define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ 1425 #define MUX_PA08O_ADC0_DRV6 _L_(14) 1426 #define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) 1427 #define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) 1428 #define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ 1429 #define MUX_PA09O_ADC0_DRV7 _L_(14) 1430 #define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) 1431 #define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) 1432 #define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ 1433 #define MUX_PA10O_ADC0_DRV8 _L_(14) 1434 #define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) 1435 #define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) 1436 #define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ 1437 #define MUX_PA11O_ADC0_DRV9 _L_(14) 1438 #define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) 1439 #define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) 1440 #define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ 1441 #define MUX_PA16O_ADC0_DRV10 _L_(14) 1442 #define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) 1443 #define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) 1444 #define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ 1445 #define MUX_PA17O_ADC0_DRV11 _L_(14) 1446 #define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) 1447 #define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) 1448 #define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ 1449 #define MUX_PA18O_ADC0_DRV12 _L_(14) 1450 #define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) 1451 #define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) 1452 #define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ 1453 #define MUX_PA19O_ADC0_DRV13 _L_(14) 1454 #define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) 1455 #define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) 1456 #define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ 1457 #define MUX_PA20O_ADC0_DRV14 _L_(14) 1458 #define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) 1459 #define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) 1460 #define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ 1461 #define MUX_PA21O_ADC0_DRV15 _L_(14) 1462 #define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) 1463 #define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) 1464 #define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ 1465 #define MUX_PA22O_ADC0_DRV16 _L_(14) 1466 #define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) 1467 #define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) 1468 #define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ 1469 #define MUX_PA23O_ADC0_DRV17 _L_(14) 1470 #define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) 1471 #define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) 1472 #define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ 1473 #define MUX_PA27O_ADC0_DRV18 _L_(14) 1474 #define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) 1475 #define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) 1476 #define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ 1477 #define MUX_PA30O_ADC0_DRV19 _L_(14) 1478 #define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) 1479 #define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) 1480 #define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ 1481 #define MUX_PB02O_ADC0_DRV20 _L_(14) 1482 #define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) 1483 #define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) 1484 #define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ 1485 #define MUX_PB03O_ADC0_DRV21 _L_(14) 1486 #define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) 1487 #define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) 1488 #define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ 1489 #define MUX_PB04O_ADC0_DRV22 _L_(14) 1490 #define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) 1491 #define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) 1492 #define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ 1493 #define MUX_PB05O_ADC0_DRV23 _L_(14) 1494 #define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) 1495 #define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) 1496 #define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ 1497 #define MUX_PB06O_ADC0_DRV24 _L_(14) 1498 #define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) 1499 #define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) 1500 #define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ 1501 #define MUX_PB07O_ADC0_DRV25 _L_(14) 1502 #define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) 1503 #define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) 1504 #define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ 1505 #define MUX_PB12O_ADC0_DRV26 _L_(14) 1506 #define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) 1507 #define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) 1508 #define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ 1509 #define MUX_PB13O_ADC0_DRV27 _L_(14) 1510 #define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) 1511 #define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) 1512 #define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ 1513 #define MUX_PB14O_ADC0_DRV28 _L_(14) 1514 #define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) 1515 #define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) 1516 #define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ 1517 #define MUX_PB15O_ADC0_DRV29 _L_(14) 1518 #define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) 1519 #define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) 1520 #define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ 1521 #define MUX_PB00O_ADC0_DRV30 _L_(14) 1522 #define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) 1523 #define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) 1524 #define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ 1525 #define MUX_PB01O_ADC0_DRV31 _L_(14) 1526 #define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) 1527 #define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) 1528 #define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ 1529 #define MUX_PA03B_ADC0_PTCXY0 _L_(1) 1530 #define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) 1531 #define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) 1532 #define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ 1533 #define MUX_PB08B_ADC0_PTCXY1 _L_(1) 1534 #define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) 1535 #define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) 1536 #define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ 1537 #define MUX_PB09B_ADC0_PTCXY2 _L_(1) 1538 #define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) 1539 #define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) 1540 #define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ 1541 #define MUX_PA04B_ADC0_PTCXY3 _L_(1) 1542 #define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) 1543 #define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) 1544 #define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ 1545 #define MUX_PA06B_ADC0_PTCXY4 _L_(1) 1546 #define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) 1547 #define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) 1548 #define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ 1549 #define MUX_PA07B_ADC0_PTCXY5 _L_(1) 1550 #define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) 1551 #define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) 1552 #define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ 1553 #define MUX_PA08B_ADC0_PTCXY6 _L_(1) 1554 #define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) 1555 #define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) 1556 #define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ 1557 #define MUX_PA09B_ADC0_PTCXY7 _L_(1) 1558 #define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) 1559 #define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) 1560 #define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ 1561 #define MUX_PA10B_ADC0_PTCXY8 _L_(1) 1562 #define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) 1563 #define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) 1564 #define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ 1565 #define MUX_PA11B_ADC0_PTCXY9 _L_(1) 1566 #define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) 1567 #define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) 1568 #define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ 1569 #define MUX_PA16B_ADC0_PTCXY10 _L_(1) 1570 #define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) 1571 #define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) 1572 #define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ 1573 #define MUX_PA17B_ADC0_PTCXY11 _L_(1) 1574 #define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) 1575 #define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) 1576 #define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ 1577 #define MUX_PA18B_ADC0_PTCXY12 _L_(1) 1578 #define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) 1579 #define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) 1580 #define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ 1581 #define MUX_PA19B_ADC0_PTCXY13 _L_(1) 1582 #define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) 1583 #define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) 1584 #define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ 1585 #define MUX_PA20B_ADC0_PTCXY14 _L_(1) 1586 #define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) 1587 #define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) 1588 #define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ 1589 #define MUX_PA21B_ADC0_PTCXY15 _L_(1) 1590 #define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) 1591 #define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) 1592 #define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ 1593 #define MUX_PA22B_ADC0_PTCXY16 _L_(1) 1594 #define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) 1595 #define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) 1596 #define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ 1597 #define MUX_PA23B_ADC0_PTCXY17 _L_(1) 1598 #define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) 1599 #define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) 1600 #define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ 1601 #define MUX_PA27B_ADC0_PTCXY18 _L_(1) 1602 #define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) 1603 #define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) 1604 #define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ 1605 #define MUX_PA30B_ADC0_PTCXY19 _L_(1) 1606 #define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) 1607 #define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) 1608 #define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ 1609 #define MUX_PB02B_ADC0_PTCXY20 _L_(1) 1610 #define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) 1611 #define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) 1612 #define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ 1613 #define MUX_PB03B_ADC0_PTCXY21 _L_(1) 1614 #define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) 1615 #define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) 1616 #define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ 1617 #define MUX_PB04B_ADC0_PTCXY22 _L_(1) 1618 #define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) 1619 #define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) 1620 #define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ 1621 #define MUX_PB05B_ADC0_PTCXY23 _L_(1) 1622 #define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) 1623 #define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) 1624 #define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ 1625 #define MUX_PB06B_ADC0_PTCXY24 _L_(1) 1626 #define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) 1627 #define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) 1628 #define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ 1629 #define MUX_PB07B_ADC0_PTCXY25 _L_(1) 1630 #define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) 1631 #define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) 1632 #define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ 1633 #define MUX_PB12B_ADC0_PTCXY26 _L_(1) 1634 #define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) 1635 #define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) 1636 #define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ 1637 #define MUX_PB13B_ADC0_PTCXY27 _L_(1) 1638 #define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) 1639 #define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) 1640 #define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ 1641 #define MUX_PB14B_ADC0_PTCXY28 _L_(1) 1642 #define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) 1643 #define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) 1644 #define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ 1645 #define MUX_PB15B_ADC0_PTCXY29 _L_(1) 1646 #define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) 1647 #define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) 1648 #define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ 1649 #define MUX_PB00B_ADC0_PTCXY30 _L_(1) 1650 #define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) 1651 #define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) 1652 #define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ 1653 #define MUX_PB01B_ADC0_PTCXY31 _L_(1) 1654 #define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) 1655 #define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) 1656 /* ========== PORT definition for ADC1 peripheral ========== */ 1657 #define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ 1658 #define MUX_PB08B_ADC1_AIN0 _L_(1) 1659 #define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) 1660 #define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) 1661 #define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ 1662 #define MUX_PB09B_ADC1_AIN1 _L_(1) 1663 #define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) 1664 #define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) 1665 #define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ 1666 #define MUX_PA08B_ADC1_AIN2 _L_(1) 1667 #define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) 1668 #define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) 1669 #define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ 1670 #define MUX_PA09B_ADC1_AIN3 _L_(1) 1671 #define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) 1672 #define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) 1673 #define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ 1674 #define MUX_PB04B_ADC1_AIN6 _L_(1) 1675 #define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) 1676 #define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) 1677 #define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ 1678 #define MUX_PB05B_ADC1_AIN7 _L_(1) 1679 #define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) 1680 #define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) 1681 #define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ 1682 #define MUX_PB06B_ADC1_AIN8 _L_(1) 1683 #define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) 1684 #define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) 1685 #define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ 1686 #define MUX_PB07B_ADC1_AIN9 _L_(1) 1687 #define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) 1688 #define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) 1689 /* ========== PORT definition for DAC peripheral ========== */ 1690 #define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ 1691 #define MUX_PA02B_DAC_VOUT0 _L_(1) 1692 #define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) 1693 #define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) 1694 #define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ 1695 #define MUX_PA05B_DAC_VOUT1 _L_(1) 1696 #define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) 1697 #define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) 1698 /* ========== PORT definition for I2S peripheral ========== */ 1699 #define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ 1700 #define MUX_PA09J_I2S_FS0 _L_(9) 1701 #define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) 1702 #define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) 1703 #define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ 1704 #define MUX_PA20J_I2S_FS0 _L_(9) 1705 #define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) 1706 #define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) 1707 #define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ 1708 #define MUX_PA23J_I2S_FS1 _L_(9) 1709 #define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) 1710 #define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) 1711 #define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ 1712 #define MUX_PB11J_I2S_FS1 _L_(9) 1713 #define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) 1714 #define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) 1715 #define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ 1716 #define MUX_PA08J_I2S_MCK0 _L_(9) 1717 #define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) 1718 #define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) 1719 #define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ 1720 #define MUX_PB17J_I2S_MCK0 _L_(9) 1721 #define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) 1722 #define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) 1723 #define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ 1724 #define MUX_PB13J_I2S_MCK1 _L_(9) 1725 #define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) 1726 #define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) 1727 #define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ 1728 #define MUX_PA10J_I2S_SCK0 _L_(9) 1729 #define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) 1730 #define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) 1731 #define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ 1732 #define MUX_PB16J_I2S_SCK0 _L_(9) 1733 #define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) 1734 #define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) 1735 #define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ 1736 #define MUX_PB12J_I2S_SCK1 _L_(9) 1737 #define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) 1738 #define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) 1739 #define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ 1740 #define MUX_PA22J_I2S_SDI _L_(9) 1741 #define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) 1742 #define PORT_PA22J_I2S_SDI (_UL_(1) << 22) 1743 #define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ 1744 #define MUX_PB10J_I2S_SDI _L_(9) 1745 #define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) 1746 #define PORT_PB10J_I2S_SDI (_UL_(1) << 10) 1747 #define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ 1748 #define MUX_PA11J_I2S_SDO _L_(9) 1749 #define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) 1750 #define PORT_PA11J_I2S_SDO (_UL_(1) << 11) 1751 #define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ 1752 #define MUX_PA21J_I2S_SDO _L_(9) 1753 #define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) 1754 #define PORT_PA21J_I2S_SDO (_UL_(1) << 21) 1755 /* ========== PORT definition for PCC peripheral ========== */ 1756 #define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ 1757 #define MUX_PA14K_PCC_CLK _L_(10) 1758 #define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) 1759 #define PORT_PA14K_PCC_CLK (_UL_(1) << 14) 1760 #define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ 1761 #define MUX_PA16K_PCC_DATA0 _L_(10) 1762 #define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) 1763 #define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) 1764 #define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ 1765 #define MUX_PA17K_PCC_DATA1 _L_(10) 1766 #define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) 1767 #define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) 1768 #define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ 1769 #define MUX_PA18K_PCC_DATA2 _L_(10) 1770 #define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) 1771 #define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) 1772 #define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ 1773 #define MUX_PA19K_PCC_DATA3 _L_(10) 1774 #define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) 1775 #define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) 1776 #define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ 1777 #define MUX_PA20K_PCC_DATA4 _L_(10) 1778 #define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) 1779 #define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) 1780 #define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ 1781 #define MUX_PA21K_PCC_DATA5 _L_(10) 1782 #define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) 1783 #define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) 1784 #define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ 1785 #define MUX_PA22K_PCC_DATA6 _L_(10) 1786 #define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) 1787 #define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) 1788 #define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ 1789 #define MUX_PA23K_PCC_DATA7 _L_(10) 1790 #define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) 1791 #define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) 1792 #define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ 1793 #define MUX_PB14K_PCC_DATA8 _L_(10) 1794 #define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) 1795 #define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) 1796 #define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ 1797 #define MUX_PB15K_PCC_DATA9 _L_(10) 1798 #define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) 1799 #define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) 1800 #define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ 1801 #define MUX_PA12K_PCC_DEN1 _L_(10) 1802 #define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) 1803 #define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) 1804 #define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ 1805 #define MUX_PA13K_PCC_DEN2 _L_(10) 1806 #define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) 1807 #define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) 1808 /* ========== PORT definition for SDHC0 peripheral ========== */ 1809 #define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ 1810 #define MUX_PA06I_SDHC0_SDCD _L_(8) 1811 #define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) 1812 #define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) 1813 #define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ 1814 #define MUX_PA12I_SDHC0_SDCD _L_(8) 1815 #define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) 1816 #define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) 1817 #define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ 1818 #define MUX_PB12I_SDHC0_SDCD _L_(8) 1819 #define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) 1820 #define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) 1821 #define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ 1822 #define MUX_PB11I_SDHC0_SDCK _L_(8) 1823 #define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) 1824 #define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) 1825 #define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ 1826 #define MUX_PA08I_SDHC0_SDCMD _L_(8) 1827 #define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) 1828 #define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) 1829 #define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ 1830 #define MUX_PA09I_SDHC0_SDDAT0 _L_(8) 1831 #define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) 1832 #define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) 1833 #define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ 1834 #define MUX_PA10I_SDHC0_SDDAT1 _L_(8) 1835 #define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) 1836 #define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) 1837 #define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ 1838 #define MUX_PA11I_SDHC0_SDDAT2 _L_(8) 1839 #define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) 1840 #define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) 1841 #define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ 1842 #define MUX_PB10I_SDHC0_SDDAT3 _L_(8) 1843 #define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) 1844 #define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) 1845 #define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ 1846 #define MUX_PA07I_SDHC0_SDWP _L_(8) 1847 #define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) 1848 #define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) 1849 #define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ 1850 #define MUX_PA13I_SDHC0_SDWP _L_(8) 1851 #define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) 1852 #define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) 1853 #define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ 1854 #define MUX_PB13I_SDHC0_SDWP _L_(8) 1855 #define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) 1856 #define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) 1857 1858 #endif /* _SAMD51J18A_PIO_ */ 1859
