1 /** 2 * \file 3 * 4 * \brief Peripheral I/O description for SAMV71Q21 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2017-01-08T14:00:00Z */ 31 #ifndef _SAMV71Q21_PIO_H_ 32 #define _SAMV71Q21_PIO_H_ 33 34 /* ========== Peripheral I/O pin numbers ========== */ 35 #define PIN_PA0 ( 0) /**< Pin Number for PA0 */ 36 #define PIN_PA1 ( 1) /**< Pin Number for PA1 */ 37 #define PIN_PA2 ( 2) /**< Pin Number for PA2 */ 38 #define PIN_PA3 ( 3) /**< Pin Number for PA3 */ 39 #define PIN_PA4 ( 4) /**< Pin Number for PA4 */ 40 #define PIN_PA5 ( 5) /**< Pin Number for PA5 */ 41 #define PIN_PA6 ( 6) /**< Pin Number for PA6 */ 42 #define PIN_PA7 ( 7) /**< Pin Number for PA7 */ 43 #define PIN_PA8 ( 8) /**< Pin Number for PA8 */ 44 #define PIN_PA9 ( 9) /**< Pin Number for PA9 */ 45 #define PIN_PA10 ( 10) /**< Pin Number for PA10 */ 46 #define PIN_PA11 ( 11) /**< Pin Number for PA11 */ 47 #define PIN_PA12 ( 12) /**< Pin Number for PA12 */ 48 #define PIN_PA13 ( 13) /**< Pin Number for PA13 */ 49 #define PIN_PA14 ( 14) /**< Pin Number for PA14 */ 50 #define PIN_PA15 ( 15) /**< Pin Number for PA15 */ 51 #define PIN_PA16 ( 16) /**< Pin Number for PA16 */ 52 #define PIN_PA17 ( 17) /**< Pin Number for PA17 */ 53 #define PIN_PA18 ( 18) /**< Pin Number for PA18 */ 54 #define PIN_PA19 ( 19) /**< Pin Number for PA19 */ 55 #define PIN_PA20 ( 20) /**< Pin Number for PA20 */ 56 #define PIN_PA21 ( 21) /**< Pin Number for PA21 */ 57 #define PIN_PA22 ( 22) /**< Pin Number for PA22 */ 58 #define PIN_PA23 ( 23) /**< Pin Number for PA23 */ 59 #define PIN_PA24 ( 24) /**< Pin Number for PA24 */ 60 #define PIN_PA25 ( 25) /**< Pin Number for PA25 */ 61 #define PIN_PA26 ( 26) /**< Pin Number for PA26 */ 62 #define PIN_PA27 ( 27) /**< Pin Number for PA27 */ 63 #define PIN_PA28 ( 28) /**< Pin Number for PA28 */ 64 #define PIN_PA29 ( 29) /**< Pin Number for PA29 */ 65 #define PIN_PA30 ( 30) /**< Pin Number for PA30 */ 66 #define PIN_PA31 ( 31) /**< Pin Number for PA31 */ 67 #define PIN_PB0 ( 32) /**< Pin Number for PB0 */ 68 #define PIN_PB1 ( 33) /**< Pin Number for PB1 */ 69 #define PIN_PB2 ( 34) /**< Pin Number for PB2 */ 70 #define PIN_PB3 ( 35) /**< Pin Number for PB3 */ 71 #define PIN_PB4 ( 36) /**< Pin Number for PB4 */ 72 #define PIN_PB5 ( 37) /**< Pin Number for PB5 */ 73 #define PIN_PB6 ( 38) /**< Pin Number for PB6 */ 74 #define PIN_PB7 ( 39) /**< Pin Number for PB7 */ 75 #define PIN_PB8 ( 40) /**< Pin Number for PB8 */ 76 #define PIN_PB9 ( 41) /**< Pin Number for PB9 */ 77 #define PIN_PB12 ( 44) /**< Pin Number for PB12 */ 78 #define PIN_PB13 ( 45) /**< Pin Number for PB13 */ 79 #define PIN_PC0 ( 64) /**< Pin Number for PC0 */ 80 #define PIN_PC1 ( 65) /**< Pin Number for PC1 */ 81 #define PIN_PC2 ( 66) /**< Pin Number for PC2 */ 82 #define PIN_PC3 ( 67) /**< Pin Number for PC3 */ 83 #define PIN_PC4 ( 68) /**< Pin Number for PC4 */ 84 #define PIN_PC5 ( 69) /**< Pin Number for PC5 */ 85 #define PIN_PC6 ( 70) /**< Pin Number for PC6 */ 86 #define PIN_PC7 ( 71) /**< Pin Number for PC7 */ 87 #define PIN_PC8 ( 72) /**< Pin Number for PC8 */ 88 #define PIN_PC9 ( 73) /**< Pin Number for PC9 */ 89 #define PIN_PC10 ( 74) /**< Pin Number for PC10 */ 90 #define PIN_PC11 ( 75) /**< Pin Number for PC11 */ 91 #define PIN_PC12 ( 76) /**< Pin Number for PC12 */ 92 #define PIN_PC13 ( 77) /**< Pin Number for PC13 */ 93 #define PIN_PC14 ( 78) /**< Pin Number for PC14 */ 94 #define PIN_PC15 ( 79) /**< Pin Number for PC15 */ 95 #define PIN_PC16 ( 80) /**< Pin Number for PC16 */ 96 #define PIN_PC17 ( 81) /**< Pin Number for PC17 */ 97 #define PIN_PC18 ( 82) /**< Pin Number for PC18 */ 98 #define PIN_PC19 ( 83) /**< Pin Number for PC19 */ 99 #define PIN_PC20 ( 84) /**< Pin Number for PC20 */ 100 #define PIN_PC21 ( 85) /**< Pin Number for PC21 */ 101 #define PIN_PC22 ( 86) /**< Pin Number for PC22 */ 102 #define PIN_PC23 ( 87) /**< Pin Number for PC23 */ 103 #define PIN_PC24 ( 88) /**< Pin Number for PC24 */ 104 #define PIN_PC25 ( 89) /**< Pin Number for PC25 */ 105 #define PIN_PC26 ( 90) /**< Pin Number for PC26 */ 106 #define PIN_PC27 ( 91) /**< Pin Number for PC27 */ 107 #define PIN_PC28 ( 92) /**< Pin Number for PC28 */ 108 #define PIN_PC29 ( 93) /**< Pin Number for PC29 */ 109 #define PIN_PC30 ( 94) /**< Pin Number for PC30 */ 110 #define PIN_PC31 ( 95) /**< Pin Number for PC31 */ 111 #define PIN_PD0 ( 96) /**< Pin Number for PD0 */ 112 #define PIN_PD1 ( 97) /**< Pin Number for PD1 */ 113 #define PIN_PD2 ( 98) /**< Pin Number for PD2 */ 114 #define PIN_PD3 ( 99) /**< Pin Number for PD3 */ 115 #define PIN_PD4 (100) /**< Pin Number for PD4 */ 116 #define PIN_PD5 (101) /**< Pin Number for PD5 */ 117 #define PIN_PD6 (102) /**< Pin Number for PD6 */ 118 #define PIN_PD7 (103) /**< Pin Number for PD7 */ 119 #define PIN_PD8 (104) /**< Pin Number for PD8 */ 120 #define PIN_PD9 (105) /**< Pin Number for PD9 */ 121 #define PIN_PD10 (106) /**< Pin Number for PD10 */ 122 #define PIN_PD11 (107) /**< Pin Number for PD11 */ 123 #define PIN_PD12 (108) /**< Pin Number for PD12 */ 124 #define PIN_PD13 (109) /**< Pin Number for PD13 */ 125 #define PIN_PD14 (110) /**< Pin Number for PD14 */ 126 #define PIN_PD15 (111) /**< Pin Number for PD15 */ 127 #define PIN_PD16 (112) /**< Pin Number for PD16 */ 128 #define PIN_PD17 (113) /**< Pin Number for PD17 */ 129 #define PIN_PD18 (114) /**< Pin Number for PD18 */ 130 #define PIN_PD19 (115) /**< Pin Number for PD19 */ 131 #define PIN_PD20 (116) /**< Pin Number for PD20 */ 132 #define PIN_PD21 (117) /**< Pin Number for PD21 */ 133 #define PIN_PD22 (118) /**< Pin Number for PD22 */ 134 #define PIN_PD23 (119) /**< Pin Number for PD23 */ 135 #define PIN_PD24 (120) /**< Pin Number for PD24 */ 136 #define PIN_PD25 (121) /**< Pin Number for PD25 */ 137 #define PIN_PD26 (122) /**< Pin Number for PD26 */ 138 #define PIN_PD27 (123) /**< Pin Number for PD27 */ 139 #define PIN_PD28 (124) /**< Pin Number for PD28 */ 140 #define PIN_PD29 (125) /**< Pin Number for PD29 */ 141 #define PIN_PD30 (126) /**< Pin Number for PD30 */ 142 #define PIN_PD31 (127) /**< Pin Number for PD31 */ 143 #define PIN_PE0 (128) /**< Pin Number for PE0 */ 144 #define PIN_PE1 (129) /**< Pin Number for PE1 */ 145 #define PIN_PE2 (130) /**< Pin Number for PE2 */ 146 #define PIN_PE3 (131) /**< Pin Number for PE3 */ 147 #define PIN_PE4 (132) /**< Pin Number for PE4 */ 148 #define PIN_PE5 (133) /**< Pin Number for PE5 */ 149 150 151 /* ========== Peripheral I/O masks ========== */ 152 #define PIO_PA0 (_U_(1) << 0) /**< PIO Mask for PA0 */ 153 #define PIO_PA1 (_U_(1) << 1) /**< PIO Mask for PA1 */ 154 #define PIO_PA2 (_U_(1) << 2) /**< PIO Mask for PA2 */ 155 #define PIO_PA3 (_U_(1) << 3) /**< PIO Mask for PA3 */ 156 #define PIO_PA4 (_U_(1) << 4) /**< PIO Mask for PA4 */ 157 #define PIO_PA5 (_U_(1) << 5) /**< PIO Mask for PA5 */ 158 #define PIO_PA6 (_U_(1) << 6) /**< PIO Mask for PA6 */ 159 #define PIO_PA7 (_U_(1) << 7) /**< PIO Mask for PA7 */ 160 #define PIO_PA8 (_U_(1) << 8) /**< PIO Mask for PA8 */ 161 #define PIO_PA9 (_U_(1) << 9) /**< PIO Mask for PA9 */ 162 #define PIO_PA10 (_U_(1) << 10) /**< PIO Mask for PA10 */ 163 #define PIO_PA11 (_U_(1) << 11) /**< PIO Mask for PA11 */ 164 #define PIO_PA12 (_U_(1) << 12) /**< PIO Mask for PA12 */ 165 #define PIO_PA13 (_U_(1) << 13) /**< PIO Mask for PA13 */ 166 #define PIO_PA14 (_U_(1) << 14) /**< PIO Mask for PA14 */ 167 #define PIO_PA15 (_U_(1) << 15) /**< PIO Mask for PA15 */ 168 #define PIO_PA16 (_U_(1) << 16) /**< PIO Mask for PA16 */ 169 #define PIO_PA17 (_U_(1) << 17) /**< PIO Mask for PA17 */ 170 #define PIO_PA18 (_U_(1) << 18) /**< PIO Mask for PA18 */ 171 #define PIO_PA19 (_U_(1) << 19) /**< PIO Mask for PA19 */ 172 #define PIO_PA20 (_U_(1) << 20) /**< PIO Mask for PA20 */ 173 #define PIO_PA21 (_U_(1) << 21) /**< PIO Mask for PA21 */ 174 #define PIO_PA22 (_U_(1) << 22) /**< PIO Mask for PA22 */ 175 #define PIO_PA23 (_U_(1) << 23) /**< PIO Mask for PA23 */ 176 #define PIO_PA24 (_U_(1) << 24) /**< PIO Mask for PA24 */ 177 #define PIO_PA25 (_U_(1) << 25) /**< PIO Mask for PA25 */ 178 #define PIO_PA26 (_U_(1) << 26) /**< PIO Mask for PA26 */ 179 #define PIO_PA27 (_U_(1) << 27) /**< PIO Mask for PA27 */ 180 #define PIO_PA28 (_U_(1) << 28) /**< PIO Mask for PA28 */ 181 #define PIO_PA29 (_U_(1) << 29) /**< PIO Mask for PA29 */ 182 #define PIO_PA30 (_U_(1) << 30) /**< PIO Mask for PA30 */ 183 #define PIO_PA31 (_U_(1) << 31) /**< PIO Mask for PA31 */ 184 #define PIO_PB0 (_U_(1) << 0) /**< PIO Mask for PB0 */ 185 #define PIO_PB1 (_U_(1) << 1) /**< PIO Mask for PB1 */ 186 #define PIO_PB2 (_U_(1) << 2) /**< PIO Mask for PB2 */ 187 #define PIO_PB3 (_U_(1) << 3) /**< PIO Mask for PB3 */ 188 #define PIO_PB4 (_U_(1) << 4) /**< PIO Mask for PB4 */ 189 #define PIO_PB5 (_U_(1) << 5) /**< PIO Mask for PB5 */ 190 #define PIO_PB6 (_U_(1) << 6) /**< PIO Mask for PB6 */ 191 #define PIO_PB7 (_U_(1) << 7) /**< PIO Mask for PB7 */ 192 #define PIO_PB8 (_U_(1) << 8) /**< PIO Mask for PB8 */ 193 #define PIO_PB9 (_U_(1) << 9) /**< PIO Mask for PB9 */ 194 #define PIO_PB12 (_U_(1) << 12) /**< PIO Mask for PB12 */ 195 #define PIO_PB13 (_U_(1) << 13) /**< PIO Mask for PB13 */ 196 #define PIO_PC0 (_U_(1) << 0) /**< PIO Mask for PC0 */ 197 #define PIO_PC1 (_U_(1) << 1) /**< PIO Mask for PC1 */ 198 #define PIO_PC2 (_U_(1) << 2) /**< PIO Mask for PC2 */ 199 #define PIO_PC3 (_U_(1) << 3) /**< PIO Mask for PC3 */ 200 #define PIO_PC4 (_U_(1) << 4) /**< PIO Mask for PC4 */ 201 #define PIO_PC5 (_U_(1) << 5) /**< PIO Mask for PC5 */ 202 #define PIO_PC6 (_U_(1) << 6) /**< PIO Mask for PC6 */ 203 #define PIO_PC7 (_U_(1) << 7) /**< PIO Mask for PC7 */ 204 #define PIO_PC8 (_U_(1) << 8) /**< PIO Mask for PC8 */ 205 #define PIO_PC9 (_U_(1) << 9) /**< PIO Mask for PC9 */ 206 #define PIO_PC10 (_U_(1) << 10) /**< PIO Mask for PC10 */ 207 #define PIO_PC11 (_U_(1) << 11) /**< PIO Mask for PC11 */ 208 #define PIO_PC12 (_U_(1) << 12) /**< PIO Mask for PC12 */ 209 #define PIO_PC13 (_U_(1) << 13) /**< PIO Mask for PC13 */ 210 #define PIO_PC14 (_U_(1) << 14) /**< PIO Mask for PC14 */ 211 #define PIO_PC15 (_U_(1) << 15) /**< PIO Mask for PC15 */ 212 #define PIO_PC16 (_U_(1) << 16) /**< PIO Mask for PC16 */ 213 #define PIO_PC17 (_U_(1) << 17) /**< PIO Mask for PC17 */ 214 #define PIO_PC18 (_U_(1) << 18) /**< PIO Mask for PC18 */ 215 #define PIO_PC19 (_U_(1) << 19) /**< PIO Mask for PC19 */ 216 #define PIO_PC20 (_U_(1) << 20) /**< PIO Mask for PC20 */ 217 #define PIO_PC21 (_U_(1) << 21) /**< PIO Mask for PC21 */ 218 #define PIO_PC22 (_U_(1) << 22) /**< PIO Mask for PC22 */ 219 #define PIO_PC23 (_U_(1) << 23) /**< PIO Mask for PC23 */ 220 #define PIO_PC24 (_U_(1) << 24) /**< PIO Mask for PC24 */ 221 #define PIO_PC25 (_U_(1) << 25) /**< PIO Mask for PC25 */ 222 #define PIO_PC26 (_U_(1) << 26) /**< PIO Mask for PC26 */ 223 #define PIO_PC27 (_U_(1) << 27) /**< PIO Mask for PC27 */ 224 #define PIO_PC28 (_U_(1) << 28) /**< PIO Mask for PC28 */ 225 #define PIO_PC29 (_U_(1) << 29) /**< PIO Mask for PC29 */ 226 #define PIO_PC30 (_U_(1) << 30) /**< PIO Mask for PC30 */ 227 #define PIO_PC31 (_U_(1) << 31) /**< PIO Mask for PC31 */ 228 #define PIO_PD0 (_U_(1) << 0) /**< PIO Mask for PD0 */ 229 #define PIO_PD1 (_U_(1) << 1) /**< PIO Mask for PD1 */ 230 #define PIO_PD2 (_U_(1) << 2) /**< PIO Mask for PD2 */ 231 #define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */ 232 #define PIO_PD4 (_U_(1) << 4) /**< PIO Mask for PD4 */ 233 #define PIO_PD5 (_U_(1) << 5) /**< PIO Mask for PD5 */ 234 #define PIO_PD6 (_U_(1) << 6) /**< PIO Mask for PD6 */ 235 #define PIO_PD7 (_U_(1) << 7) /**< PIO Mask for PD7 */ 236 #define PIO_PD8 (_U_(1) << 8) /**< PIO Mask for PD8 */ 237 #define PIO_PD9 (_U_(1) << 9) /**< PIO Mask for PD9 */ 238 #define PIO_PD10 (_U_(1) << 10) /**< PIO Mask for PD10 */ 239 #define PIO_PD11 (_U_(1) << 11) /**< PIO Mask for PD11 */ 240 #define PIO_PD12 (_U_(1) << 12) /**< PIO Mask for PD12 */ 241 #define PIO_PD13 (_U_(1) << 13) /**< PIO Mask for PD13 */ 242 #define PIO_PD14 (_U_(1) << 14) /**< PIO Mask for PD14 */ 243 #define PIO_PD15 (_U_(1) << 15) /**< PIO Mask for PD15 */ 244 #define PIO_PD16 (_U_(1) << 16) /**< PIO Mask for PD16 */ 245 #define PIO_PD17 (_U_(1) << 17) /**< PIO Mask for PD17 */ 246 #define PIO_PD18 (_U_(1) << 18) /**< PIO Mask for PD18 */ 247 #define PIO_PD19 (_U_(1) << 19) /**< PIO Mask for PD19 */ 248 #define PIO_PD20 (_U_(1) << 20) /**< PIO Mask for PD20 */ 249 #define PIO_PD21 (_U_(1) << 21) /**< PIO Mask for PD21 */ 250 #define PIO_PD22 (_U_(1) << 22) /**< PIO Mask for PD22 */ 251 #define PIO_PD23 (_U_(1) << 23) /**< PIO Mask for PD23 */ 252 #define PIO_PD24 (_U_(1) << 24) /**< PIO Mask for PD24 */ 253 #define PIO_PD25 (_U_(1) << 25) /**< PIO Mask for PD25 */ 254 #define PIO_PD26 (_U_(1) << 26) /**< PIO Mask for PD26 */ 255 #define PIO_PD27 (_U_(1) << 27) /**< PIO Mask for PD27 */ 256 #define PIO_PD28 (_U_(1) << 28) /**< PIO Mask for PD28 */ 257 #define PIO_PD29 (_U_(1) << 29) /**< PIO Mask for PD29 */ 258 #define PIO_PD30 (_U_(1) << 30) /**< PIO Mask for PD30 */ 259 #define PIO_PD31 (_U_(1) << 31) /**< PIO Mask for PD31 */ 260 #define PIO_PE0 (_U_(1) << 0) /**< PIO Mask for PE0 */ 261 #define PIO_PE1 (_U_(1) << 1) /**< PIO Mask for PE1 */ 262 #define PIO_PE2 (_U_(1) << 2) /**< PIO Mask for PE2 */ 263 #define PIO_PE3 (_U_(1) << 3) /**< PIO Mask for PE3 */ 264 #define PIO_PE4 (_U_(1) << 4) /**< PIO Mask for PE4 */ 265 #define PIO_PE5 (_U_(1) << 5) /**< PIO Mask for PE5 */ 266 267 268 /* ========== Peripheral I/O indexes ========== */ 269 #define PIO_PA0_IDX ( 0) /**< PIO Index Number for PA0 */ 270 #define PIO_PA1_IDX ( 1) /**< PIO Index Number for PA1 */ 271 #define PIO_PA2_IDX ( 2) /**< PIO Index Number for PA2 */ 272 #define PIO_PA3_IDX ( 3) /**< PIO Index Number for PA3 */ 273 #define PIO_PA4_IDX ( 4) /**< PIO Index Number for PA4 */ 274 #define PIO_PA5_IDX ( 5) /**< PIO Index Number for PA5 */ 275 #define PIO_PA6_IDX ( 6) /**< PIO Index Number for PA6 */ 276 #define PIO_PA7_IDX ( 7) /**< PIO Index Number for PA7 */ 277 #define PIO_PA8_IDX ( 8) /**< PIO Index Number for PA8 */ 278 #define PIO_PA9_IDX ( 9) /**< PIO Index Number for PA9 */ 279 #define PIO_PA10_IDX ( 10) /**< PIO Index Number for PA10 */ 280 #define PIO_PA11_IDX ( 11) /**< PIO Index Number for PA11 */ 281 #define PIO_PA12_IDX ( 12) /**< PIO Index Number for PA12 */ 282 #define PIO_PA13_IDX ( 13) /**< PIO Index Number for PA13 */ 283 #define PIO_PA14_IDX ( 14) /**< PIO Index Number for PA14 */ 284 #define PIO_PA15_IDX ( 15) /**< PIO Index Number for PA15 */ 285 #define PIO_PA16_IDX ( 16) /**< PIO Index Number for PA16 */ 286 #define PIO_PA17_IDX ( 17) /**< PIO Index Number for PA17 */ 287 #define PIO_PA18_IDX ( 18) /**< PIO Index Number for PA18 */ 288 #define PIO_PA19_IDX ( 19) /**< PIO Index Number for PA19 */ 289 #define PIO_PA20_IDX ( 20) /**< PIO Index Number for PA20 */ 290 #define PIO_PA21_IDX ( 21) /**< PIO Index Number for PA21 */ 291 #define PIO_PA22_IDX ( 22) /**< PIO Index Number for PA22 */ 292 #define PIO_PA23_IDX ( 23) /**< PIO Index Number for PA23 */ 293 #define PIO_PA24_IDX ( 24) /**< PIO Index Number for PA24 */ 294 #define PIO_PA25_IDX ( 25) /**< PIO Index Number for PA25 */ 295 #define PIO_PA26_IDX ( 26) /**< PIO Index Number for PA26 */ 296 #define PIO_PA27_IDX ( 27) /**< PIO Index Number for PA27 */ 297 #define PIO_PA28_IDX ( 28) /**< PIO Index Number for PA28 */ 298 #define PIO_PA29_IDX ( 29) /**< PIO Index Number for PA29 */ 299 #define PIO_PA30_IDX ( 30) /**< PIO Index Number for PA30 */ 300 #define PIO_PA31_IDX ( 31) /**< PIO Index Number for PA31 */ 301 #define PIO_PB0_IDX ( 32) /**< PIO Index Number for PB0 */ 302 #define PIO_PB1_IDX ( 33) /**< PIO Index Number for PB1 */ 303 #define PIO_PB2_IDX ( 34) /**< PIO Index Number for PB2 */ 304 #define PIO_PB3_IDX ( 35) /**< PIO Index Number for PB3 */ 305 #define PIO_PB4_IDX ( 36) /**< PIO Index Number for PB4 */ 306 #define PIO_PB5_IDX ( 37) /**< PIO Index Number for PB5 */ 307 #define PIO_PB6_IDX ( 38) /**< PIO Index Number for PB6 */ 308 #define PIO_PB7_IDX ( 39) /**< PIO Index Number for PB7 */ 309 #define PIO_PB8_IDX ( 40) /**< PIO Index Number for PB8 */ 310 #define PIO_PB9_IDX ( 41) /**< PIO Index Number for PB9 */ 311 #define PIO_PB12_IDX ( 44) /**< PIO Index Number for PB12 */ 312 #define PIO_PB13_IDX ( 45) /**< PIO Index Number for PB13 */ 313 #define PIO_PC0_IDX ( 64) /**< PIO Index Number for PC0 */ 314 #define PIO_PC1_IDX ( 65) /**< PIO Index Number for PC1 */ 315 #define PIO_PC2_IDX ( 66) /**< PIO Index Number for PC2 */ 316 #define PIO_PC3_IDX ( 67) /**< PIO Index Number for PC3 */ 317 #define PIO_PC4_IDX ( 68) /**< PIO Index Number for PC4 */ 318 #define PIO_PC5_IDX ( 69) /**< PIO Index Number for PC5 */ 319 #define PIO_PC6_IDX ( 70) /**< PIO Index Number for PC6 */ 320 #define PIO_PC7_IDX ( 71) /**< PIO Index Number for PC7 */ 321 #define PIO_PC8_IDX ( 72) /**< PIO Index Number for PC8 */ 322 #define PIO_PC9_IDX ( 73) /**< PIO Index Number for PC9 */ 323 #define PIO_PC10_IDX ( 74) /**< PIO Index Number for PC10 */ 324 #define PIO_PC11_IDX ( 75) /**< PIO Index Number for PC11 */ 325 #define PIO_PC12_IDX ( 76) /**< PIO Index Number for PC12 */ 326 #define PIO_PC13_IDX ( 77) /**< PIO Index Number for PC13 */ 327 #define PIO_PC14_IDX ( 78) /**< PIO Index Number for PC14 */ 328 #define PIO_PC15_IDX ( 79) /**< PIO Index Number for PC15 */ 329 #define PIO_PC16_IDX ( 80) /**< PIO Index Number for PC16 */ 330 #define PIO_PC17_IDX ( 81) /**< PIO Index Number for PC17 */ 331 #define PIO_PC18_IDX ( 82) /**< PIO Index Number for PC18 */ 332 #define PIO_PC19_IDX ( 83) /**< PIO Index Number for PC19 */ 333 #define PIO_PC20_IDX ( 84) /**< PIO Index Number for PC20 */ 334 #define PIO_PC21_IDX ( 85) /**< PIO Index Number for PC21 */ 335 #define PIO_PC22_IDX ( 86) /**< PIO Index Number for PC22 */ 336 #define PIO_PC23_IDX ( 87) /**< PIO Index Number for PC23 */ 337 #define PIO_PC24_IDX ( 88) /**< PIO Index Number for PC24 */ 338 #define PIO_PC25_IDX ( 89) /**< PIO Index Number for PC25 */ 339 #define PIO_PC26_IDX ( 90) /**< PIO Index Number for PC26 */ 340 #define PIO_PC27_IDX ( 91) /**< PIO Index Number for PC27 */ 341 #define PIO_PC28_IDX ( 92) /**< PIO Index Number for PC28 */ 342 #define PIO_PC29_IDX ( 93) /**< PIO Index Number for PC29 */ 343 #define PIO_PC30_IDX ( 94) /**< PIO Index Number for PC30 */ 344 #define PIO_PC31_IDX ( 95) /**< PIO Index Number for PC31 */ 345 #define PIO_PD0_IDX ( 96) /**< PIO Index Number for PD0 */ 346 #define PIO_PD1_IDX ( 97) /**< PIO Index Number for PD1 */ 347 #define PIO_PD2_IDX ( 98) /**< PIO Index Number for PD2 */ 348 #define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */ 349 #define PIO_PD4_IDX (100) /**< PIO Index Number for PD4 */ 350 #define PIO_PD5_IDX (101) /**< PIO Index Number for PD5 */ 351 #define PIO_PD6_IDX (102) /**< PIO Index Number for PD6 */ 352 #define PIO_PD7_IDX (103) /**< PIO Index Number for PD7 */ 353 #define PIO_PD8_IDX (104) /**< PIO Index Number for PD8 */ 354 #define PIO_PD9_IDX (105) /**< PIO Index Number for PD9 */ 355 #define PIO_PD10_IDX (106) /**< PIO Index Number for PD10 */ 356 #define PIO_PD11_IDX (107) /**< PIO Index Number for PD11 */ 357 #define PIO_PD12_IDX (108) /**< PIO Index Number for PD12 */ 358 #define PIO_PD13_IDX (109) /**< PIO Index Number for PD13 */ 359 #define PIO_PD14_IDX (110) /**< PIO Index Number for PD14 */ 360 #define PIO_PD15_IDX (111) /**< PIO Index Number for PD15 */ 361 #define PIO_PD16_IDX (112) /**< PIO Index Number for PD16 */ 362 #define PIO_PD17_IDX (113) /**< PIO Index Number for PD17 */ 363 #define PIO_PD18_IDX (114) /**< PIO Index Number for PD18 */ 364 #define PIO_PD19_IDX (115) /**< PIO Index Number for PD19 */ 365 #define PIO_PD20_IDX (116) /**< PIO Index Number for PD20 */ 366 #define PIO_PD21_IDX (117) /**< PIO Index Number for PD21 */ 367 #define PIO_PD22_IDX (118) /**< PIO Index Number for PD22 */ 368 #define PIO_PD23_IDX (119) /**< PIO Index Number for PD23 */ 369 #define PIO_PD24_IDX (120) /**< PIO Index Number for PD24 */ 370 #define PIO_PD25_IDX (121) /**< PIO Index Number for PD25 */ 371 #define PIO_PD26_IDX (122) /**< PIO Index Number for PD26 */ 372 #define PIO_PD27_IDX (123) /**< PIO Index Number for PD27 */ 373 #define PIO_PD28_IDX (124) /**< PIO Index Number for PD28 */ 374 #define PIO_PD29_IDX (125) /**< PIO Index Number for PD29 */ 375 #define PIO_PD30_IDX (126) /**< PIO Index Number for PD30 */ 376 #define PIO_PD31_IDX (127) /**< PIO Index Number for PD31 */ 377 #define PIO_PE0_IDX (128) /**< PIO Index Number for PE0 */ 378 #define PIO_PE1_IDX (129) /**< PIO Index Number for PE1 */ 379 #define PIO_PE2_IDX (130) /**< PIO Index Number for PE2 */ 380 #define PIO_PE3_IDX (131) /**< PIO Index Number for PE3 */ 381 #define PIO_PE4_IDX (132) /**< PIO Index Number for PE4 */ 382 #define PIO_PE5_IDX (133) /**< PIO Index Number for PE5 */ 383 384 /* ========== PIO definition for AFEC0 peripheral ========== */ 385 #define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: ADTRG on PA8 mux B*/ 386 #define MUX_PA8B_AFEC0_ADTRG _L_(1) /**< AFEC0 signal line function value: ADTRG */ 387 #define PIO_PA8B_AFEC0_ADTRG (_UL_(1) << 8) 388 389 #define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AD0 on PD30 mux X1*/ 390 #define PIO_PD30X1_AFEC0_AD0 (_UL_(1) << 30) 391 392 #define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AD1 on PA21 mux X1*/ 393 #define PIO_PA21X1_AFEC0_AD1 (_UL_(1) << 21) 394 395 #define PIN_PA21X1_AFEC0_PIODCEN2 _L_(21) /**< AFEC0 signal: PIODCEN2 on PA21 mux X1*/ 396 #define PIO_PA21X1_AFEC0_PIODCEN2 (_UL_(1) << 21) 397 398 #define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AD2 on PB3 mux X1*/ 399 #define PIO_PB3X1_AFEC0_AD2 (_UL_(1) << 3) 400 401 #define PIN_PB3X1_AFEC0_WKUP12 _L_(35) /**< AFEC0 signal: WKUP12 on PB3 mux X1*/ 402 #define PIO_PB3X1_AFEC0_WKUP12 (_UL_(1) << 3) 403 404 #define PIN_PE5X1_AFEC0_AD3 _L_(133) /**< AFEC0 signal: AD3 on PE5 mux X1*/ 405 #define PIO_PE5X1_AFEC0_AD3 (_UL_(1) << 5) 406 407 #define PIN_PE4X1_AFEC0_AD4 _L_(132) /**< AFEC0 signal: AD4 on PE4 mux X1*/ 408 #define PIO_PE4X1_AFEC0_AD4 (_UL_(1) << 4) 409 410 #define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AD5 on PB2 mux X1*/ 411 #define PIO_PB2X1_AFEC0_AD5 (_UL_(1) << 2) 412 413 #define PIN_PA17X1_AFEC0_AD6 _L_(17) /**< AFEC0 signal: AD6 on PA17 mux X1*/ 414 #define PIO_PA17X1_AFEC0_AD6 (_UL_(1) << 17) 415 416 #define PIN_PA18X1_AFEC0_AD7 _L_(18) /**< AFEC0 signal: AD7 on PA18 mux X1*/ 417 #define PIO_PA18X1_AFEC0_AD7 (_UL_(1) << 18) 418 419 #define PIN_PA19X1_AFEC0_AD8 _L_(19) /**< AFEC0 signal: AD8 on PA19 mux X1*/ 420 #define PIO_PA19X1_AFEC0_AD8 (_UL_(1) << 19) 421 422 #define PIN_PA19X1_AFEC0_WKUP9 _L_(19) /**< AFEC0 signal: WKUP9 on PA19 mux X1*/ 423 #define PIO_PA19X1_AFEC0_WKUP9 (_UL_(1) << 19) 424 425 #define PIN_PA20X1_AFEC0_AD9 _L_(20) /**< AFEC0 signal: AD9 on PA20 mux X1*/ 426 #define PIO_PA20X1_AFEC0_AD9 (_UL_(1) << 20) 427 428 #define PIN_PA20X1_AFEC0_WKUP10 _L_(20) /**< AFEC0 signal: WKUP10 on PA20 mux X1*/ 429 #define PIO_PA20X1_AFEC0_WKUP10 (_UL_(1) << 20) 430 431 #define PIN_PB0X1_AFEC0_AD10 _L_(32) /**< AFEC0 signal: AD10 on PB0 mux X1*/ 432 #define PIO_PB0X1_AFEC0_AD10 (_UL_(1) << 0) 433 434 #define PIN_PB0X1_AFEC0_RTCOUT0 _L_(32) /**< AFEC0 signal: RTCOUT0 on PB0 mux X1*/ 435 #define PIO_PB0X1_AFEC0_RTCOUT0 (_UL_(1) << 0) 436 437 /* ========== PIO definition for AFEC1 peripheral ========== */ 438 #define PIN_PD9C_AFEC1_ADTRG _L_(105) /**< AFEC1 signal: ADTRG on PD9 mux C*/ 439 #define MUX_PD9C_AFEC1_ADTRG _L_(2) /**< AFEC1 signal line function value: ADTRG */ 440 #define PIO_PD9C_AFEC1_ADTRG (_UL_(1) << 9) 441 442 #define PIN_PB1X1_AFEC1_AD0 _L_(33) /**< AFEC1 signal: AD0 on PB1 mux X1*/ 443 #define PIO_PB1X1_AFEC1_AD0 (_UL_(1) << 1) 444 445 #define PIN_PB1X1_AFEC1_RTCOUT1 _L_(33) /**< AFEC1 signal: RTCOUT1 on PB1 mux X1*/ 446 #define PIO_PB1X1_AFEC1_RTCOUT1 (_UL_(1) << 1) 447 448 #define PIN_PC13X1_AFEC1_AD1 _L_(77) /**< AFEC1 signal: AD1 on PC13 mux X1*/ 449 #define PIO_PC13X1_AFEC1_AD1 (_UL_(1) << 13) 450 451 #define PIN_PC15X1_AFEC1_AD2 _L_(79) /**< AFEC1 signal: AD2 on PC15 mux X1*/ 452 #define PIO_PC15X1_AFEC1_AD2 (_UL_(1) << 15) 453 454 #define PIN_PC12X1_AFEC1_AD3 _L_(76) /**< AFEC1 signal: AD3 on PC12 mux X1*/ 455 #define PIO_PC12X1_AFEC1_AD3 (_UL_(1) << 12) 456 457 #define PIN_PC29X1_AFEC1_AD4 _L_(93) /**< AFEC1 signal: AD4 on PC29 mux X1*/ 458 #define PIO_PC29X1_AFEC1_AD4 (_UL_(1) << 29) 459 460 #define PIN_PC30X1_AFEC1_AD5 _L_(94) /**< AFEC1 signal: AD5 on PC30 mux X1*/ 461 #define PIO_PC30X1_AFEC1_AD5 (_UL_(1) << 30) 462 463 #define PIN_PC31X1_AFEC1_AD6 _L_(95) /**< AFEC1 signal: AD6 on PC31 mux X1*/ 464 #define PIO_PC31X1_AFEC1_AD6 (_UL_(1) << 31) 465 466 #define PIN_PC26X1_AFEC1_AD7 _L_(90) /**< AFEC1 signal: AD7 on PC26 mux X1*/ 467 #define PIO_PC26X1_AFEC1_AD7 (_UL_(1) << 26) 468 469 #define PIN_PC27X1_AFEC1_AD8 _L_(91) /**< AFEC1 signal: AD8 on PC27 mux X1*/ 470 #define PIO_PC27X1_AFEC1_AD8 (_UL_(1) << 27) 471 472 #define PIN_PC0X1_AFEC1_AD9 _L_(64) /**< AFEC1 signal: AD9 on PC0 mux X1*/ 473 #define PIO_PC0X1_AFEC1_AD9 (_UL_(1) << 0) 474 475 #define PIN_PE3X1_AFEC1_AD10 _L_(131) /**< AFEC1 signal: AD10 on PE3 mux X1*/ 476 #define PIO_PE3X1_AFEC1_AD10 (_UL_(1) << 3) 477 478 #define PIN_PE0X1_AFEC1_AD11 _L_(128) /**< AFEC1 signal: AD11 on PE0 mux X1*/ 479 #define PIO_PE0X1_AFEC1_AD11 (_UL_(1) << 0) 480 481 /* ========== PIO definition for DACC peripheral ========== */ 482 #define PIN_PB13X1_DACC_DAC0 _L_(45) /**< DACC signal: DAC0 on PB13 mux X1*/ 483 #define PIO_PB13X1_DACC_DAC0 (_UL_(1) << 13) 484 485 #define PIN_PD0X1_DACC_DAC1 _L_(96) /**< DACC signal: DAC1 on PD0 mux X1*/ 486 #define PIO_PD0X1_DACC_DAC1 (_UL_(1) << 0) 487 488 #define PIN_PA2C_DACC_DATRG _L_(2) /**< DACC signal: DATRG on PA2 mux C*/ 489 #define MUX_PA2C_DACC_DATRG _L_(2) /**< DACC signal line function value: DATRG */ 490 #define PIO_PA2C_DACC_DATRG (_UL_(1) << 2) 491 492 /* ========== PIO definition for GMAC peripheral ========== */ 493 #define PIN_PD13A_GMAC_GCOL _L_(109) /**< GMAC signal: GCOL on PD13 mux A*/ 494 #define MUX_PD13A_GMAC_GCOL _L_(0) /**< GMAC signal line function value: GCOL */ 495 #define PIO_PD13A_GMAC_GCOL (_UL_(1) << 13) 496 497 #define PIN_PD10A_GMAC_GCRS _L_(106) /**< GMAC signal: GCRS on PD10 mux A*/ 498 #define MUX_PD10A_GMAC_GCRS _L_(0) /**< GMAC signal line function value: GCRS */ 499 #define PIO_PD10A_GMAC_GCRS (_UL_(1) << 10) 500 501 #define PIN_PD8A_GMAC_GMDC _L_(104) /**< GMAC signal: GMDC on PD8 mux A*/ 502 #define MUX_PD8A_GMAC_GMDC _L_(0) /**< GMAC signal line function value: GMDC */ 503 #define PIO_PD8A_GMAC_GMDC (_UL_(1) << 8) 504 505 #define PIN_PD9A_GMAC_GMDIO _L_(105) /**< GMAC signal: GMDIO on PD9 mux A*/ 506 #define MUX_PD9A_GMAC_GMDIO _L_(0) /**< GMAC signal line function value: GMDIO */ 507 #define PIO_PD9A_GMAC_GMDIO (_UL_(1) << 9) 508 509 #define PIN_PD14A_GMAC_GRXCK _L_(110) /**< GMAC signal: GRXCK on PD14 mux A*/ 510 #define MUX_PD14A_GMAC_GRXCK _L_(0) /**< GMAC signal line function value: GRXCK */ 511 #define PIO_PD14A_GMAC_GRXCK (_UL_(1) << 14) 512 513 #define PIN_PD4A_GMAC_GRXDV _L_(100) /**< GMAC signal: GRXDV on PD4 mux A*/ 514 #define MUX_PD4A_GMAC_GRXDV _L_(0) /**< GMAC signal line function value: GRXDV */ 515 #define PIO_PD4A_GMAC_GRXDV (_UL_(1) << 4) 516 517 #define PIN_PD7A_GMAC_GRXER _L_(103) /**< GMAC signal: GRXER on PD7 mux A*/ 518 #define MUX_PD7A_GMAC_GRXER _L_(0) /**< GMAC signal line function value: GRXER */ 519 #define PIO_PD7A_GMAC_GRXER (_UL_(1) << 7) 520 521 #define PIN_PD5A_GMAC_GRX0 _L_(101) /**< GMAC signal: GRX0 on PD5 mux A*/ 522 #define MUX_PD5A_GMAC_GRX0 _L_(0) /**< GMAC signal line function value: GRX0 */ 523 #define PIO_PD5A_GMAC_GRX0 (_UL_(1) << 5) 524 525 #define PIN_PD6A_GMAC_GRX1 _L_(102) /**< GMAC signal: GRX1 on PD6 mux A*/ 526 #define MUX_PD6A_GMAC_GRX1 _L_(0) /**< GMAC signal line function value: GRX1 */ 527 #define PIO_PD6A_GMAC_GRX1 (_UL_(1) << 6) 528 529 #define PIN_PD11A_GMAC_GRX2 _L_(107) /**< GMAC signal: GRX2 on PD11 mux A*/ 530 #define MUX_PD11A_GMAC_GRX2 _L_(0) /**< GMAC signal line function value: GRX2 */ 531 #define PIO_PD11A_GMAC_GRX2 (_UL_(1) << 11) 532 533 #define PIN_PD12A_GMAC_GRX3 _L_(108) /**< GMAC signal: GRX3 on PD12 mux A*/ 534 #define MUX_PD12A_GMAC_GRX3 _L_(0) /**< GMAC signal line function value: GRX3 */ 535 #define PIO_PD12A_GMAC_GRX3 (_UL_(1) << 12) 536 537 #define PIN_PB1B_GMAC_GTSUCOMP _L_(33) /**< GMAC signal: GTSUCOMP on PB1 mux B*/ 538 #define MUX_PB1B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GTSUCOMP */ 539 #define PIO_PB1B_GMAC_GTSUCOMP (_UL_(1) << 1) 540 541 #define PIN_PB12B_GMAC_GTSUCOMP _L_(44) /**< GMAC signal: GTSUCOMP on PB12 mux B*/ 542 #define MUX_PB12B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GTSUCOMP */ 543 #define PIO_PB12B_GMAC_GTSUCOMP (_UL_(1) << 12) 544 545 #define PIN_PD11C_GMAC_GTSUCOMP _L_(107) /**< GMAC signal: GTSUCOMP on PD11 mux C*/ 546 #define MUX_PD11C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GTSUCOMP */ 547 #define PIO_PD11C_GMAC_GTSUCOMP (_UL_(1) << 11) 548 549 #define PIN_PD20C_GMAC_GTSUCOMP _L_(116) /**< GMAC signal: GTSUCOMP on PD20 mux C*/ 550 #define MUX_PD20C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GTSUCOMP */ 551 #define PIO_PD20C_GMAC_GTSUCOMP (_UL_(1) << 20) 552 553 #define PIN_PD0A_GMAC_GTXCK _L_(96) /**< GMAC signal: GTXCK on PD0 mux A*/ 554 #define MUX_PD0A_GMAC_GTXCK _L_(0) /**< GMAC signal line function value: GTXCK */ 555 #define PIO_PD0A_GMAC_GTXCK (_UL_(1) << 0) 556 557 #define PIN_PD1A_GMAC_GTXEN _L_(97) /**< GMAC signal: GTXEN on PD1 mux A*/ 558 #define MUX_PD1A_GMAC_GTXEN _L_(0) /**< GMAC signal line function value: GTXEN */ 559 #define PIO_PD1A_GMAC_GTXEN (_UL_(1) << 1) 560 561 #define PIN_PD17A_GMAC_GTXER _L_(113) /**< GMAC signal: GTXER on PD17 mux A*/ 562 #define MUX_PD17A_GMAC_GTXER _L_(0) /**< GMAC signal line function value: GTXER */ 563 #define PIO_PD17A_GMAC_GTXER (_UL_(1) << 17) 564 565 #define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GTX0 on PD2 mux A*/ 566 #define MUX_PD2A_GMAC_GTX0 _L_(0) /**< GMAC signal line function value: GTX0 */ 567 #define PIO_PD2A_GMAC_GTX0 (_UL_(1) << 2) 568 569 #define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A*/ 570 #define MUX_PD3A_GMAC_GTX1 _L_(0) /**< GMAC signal line function value: GTX1 */ 571 #define PIO_PD3A_GMAC_GTX1 (_UL_(1) << 3) 572 573 #define PIN_PD15A_GMAC_GTX2 _L_(111) /**< GMAC signal: GTX2 on PD15 mux A*/ 574 #define MUX_PD15A_GMAC_GTX2 _L_(0) /**< GMAC signal line function value: GTX2 */ 575 #define PIO_PD15A_GMAC_GTX2 (_UL_(1) << 15) 576 577 #define PIN_PD16A_GMAC_GTX3 _L_(112) /**< GMAC signal: GTX3 on PD16 mux A*/ 578 #define MUX_PD16A_GMAC_GTX3 _L_(0) /**< GMAC signal line function value: GTX3 */ 579 #define PIO_PD16A_GMAC_GTX3 (_UL_(1) << 16) 580 581 /* ========== PIO definition for HSMCI peripheral ========== */ 582 #define PIN_PA28C_HSMCI_MCCDA _L_(28) /**< HSMCI signal: MCCDA on PA28 mux C*/ 583 #define MUX_PA28C_HSMCI_MCCDA _L_(2) /**< HSMCI signal line function value: MCCDA */ 584 #define PIO_PA28C_HSMCI_MCCDA (_UL_(1) << 28) 585 586 #define PIN_PA25D_HSMCI_MCCK _L_(25) /**< HSMCI signal: MCCK on PA25 mux D*/ 587 #define MUX_PA25D_HSMCI_MCCK _L_(3) /**< HSMCI signal line function value: MCCK */ 588 #define PIO_PA25D_HSMCI_MCCK (_UL_(1) << 25) 589 590 #define PIN_PA30C_HSMCI_MCDA0 _L_(30) /**< HSMCI signal: MCDA0 on PA30 mux C*/ 591 #define MUX_PA30C_HSMCI_MCDA0 _L_(2) /**< HSMCI signal line function value: MCDA0 */ 592 #define PIO_PA30C_HSMCI_MCDA0 (_UL_(1) << 30) 593 594 #define PIN_PA31C_HSMCI_MCDA1 _L_(31) /**< HSMCI signal: MCDA1 on PA31 mux C*/ 595 #define MUX_PA31C_HSMCI_MCDA1 _L_(2) /**< HSMCI signal line function value: MCDA1 */ 596 #define PIO_PA31C_HSMCI_MCDA1 (_UL_(1) << 31) 597 598 #define PIN_PA26C_HSMCI_MCDA2 _L_(26) /**< HSMCI signal: MCDA2 on PA26 mux C*/ 599 #define MUX_PA26C_HSMCI_MCDA2 _L_(2) /**< HSMCI signal line function value: MCDA2 */ 600 #define PIO_PA26C_HSMCI_MCDA2 (_UL_(1) << 26) 601 602 #define PIN_PA27C_HSMCI_MCDA3 _L_(27) /**< HSMCI signal: MCDA3 on PA27 mux C*/ 603 #define MUX_PA27C_HSMCI_MCDA3 _L_(2) /**< HSMCI signal line function value: MCDA3 */ 604 #define PIO_PA27C_HSMCI_MCDA3 (_UL_(1) << 27) 605 606 /* ========== PIO definition for ISI peripheral ========== */ 607 #define PIN_PD22D_ISI_D0 _L_(118) /**< ISI signal: D0 on PD22 mux D*/ 608 #define MUX_PD22D_ISI_D0 _L_(3) /**< ISI signal line function value: D0 */ 609 #define PIO_PD22D_ISI_D0 (_UL_(1) << 22) 610 611 #define PIN_PD21D_ISI_D1 _L_(117) /**< ISI signal: D1 on PD21 mux D*/ 612 #define MUX_PD21D_ISI_D1 _L_(3) /**< ISI signal line function value: D1 */ 613 #define PIO_PD21D_ISI_D1 (_UL_(1) << 21) 614 615 #define PIN_PB3D_ISI_D2 _L_(35) /**< ISI signal: D2 on PB3 mux D*/ 616 #define MUX_PB3D_ISI_D2 _L_(3) /**< ISI signal line function value: D2 */ 617 #define PIO_PB3D_ISI_D2 (_UL_(1) << 3) 618 619 #define PIN_PA9B_ISI_D3 _L_(9) /**< ISI signal: D3 on PA9 mux B*/ 620 #define MUX_PA9B_ISI_D3 _L_(1) /**< ISI signal line function value: D3 */ 621 #define PIO_PA9B_ISI_D3 (_UL_(1) << 9) 622 623 #define PIN_PA5B_ISI_D4 _L_(5) /**< ISI signal: D4 on PA5 mux B*/ 624 #define MUX_PA5B_ISI_D4 _L_(1) /**< ISI signal line function value: D4 */ 625 #define PIO_PA5B_ISI_D4 (_UL_(1) << 5) 626 627 #define PIN_PD11D_ISI_D5 _L_(107) /**< ISI signal: D5 on PD11 mux D*/ 628 #define MUX_PD11D_ISI_D5 _L_(3) /**< ISI signal line function value: D5 */ 629 #define PIO_PD11D_ISI_D5 (_UL_(1) << 11) 630 631 #define PIN_PD12D_ISI_D6 _L_(108) /**< ISI signal: D6 on PD12 mux D*/ 632 #define MUX_PD12D_ISI_D6 _L_(3) /**< ISI signal line function value: D6 */ 633 #define PIO_PD12D_ISI_D6 (_UL_(1) << 12) 634 635 #define PIN_PA27D_ISI_D7 _L_(27) /**< ISI signal: D7 on PA27 mux D*/ 636 #define MUX_PA27D_ISI_D7 _L_(3) /**< ISI signal line function value: D7 */ 637 #define PIO_PA27D_ISI_D7 (_UL_(1) << 27) 638 639 #define PIN_PD27D_ISI_D8 _L_(123) /**< ISI signal: D8 on PD27 mux D*/ 640 #define MUX_PD27D_ISI_D8 _L_(3) /**< ISI signal line function value: D8 */ 641 #define PIO_PD27D_ISI_D8 (_UL_(1) << 27) 642 643 #define PIN_PD28D_ISI_D9 _L_(124) /**< ISI signal: D9 on PD28 mux D*/ 644 #define MUX_PD28D_ISI_D9 _L_(3) /**< ISI signal line function value: D9 */ 645 #define PIO_PD28D_ISI_D9 (_UL_(1) << 28) 646 647 #define PIN_PD30D_ISI_D10 _L_(126) /**< ISI signal: D10 on PD30 mux D*/ 648 #define MUX_PD30D_ISI_D10 _L_(3) /**< ISI signal line function value: D10 */ 649 #define PIO_PD30D_ISI_D10 (_UL_(1) << 30) 650 651 #define PIN_PD31D_ISI_D11 _L_(127) /**< ISI signal: D11 on PD31 mux D*/ 652 #define MUX_PD31D_ISI_D11 _L_(3) /**< ISI signal line function value: D11 */ 653 #define PIO_PD31D_ISI_D11 (_UL_(1) << 31) 654 655 #define PIN_PD24D_ISI_HSYNC _L_(120) /**< ISI signal: HSYNC on PD24 mux D*/ 656 #define MUX_PD24D_ISI_HSYNC _L_(3) /**< ISI signal line function value: HSYNC */ 657 #define PIO_PD24D_ISI_HSYNC (_UL_(1) << 24) 658 659 #define PIN_PA24D_ISI_PCK _L_(24) /**< ISI signal: PCK on PA24 mux D*/ 660 #define MUX_PA24D_ISI_PCK _L_(3) /**< ISI signal line function value: PCK */ 661 #define PIO_PA24D_ISI_PCK (_UL_(1) << 24) 662 663 #define PIN_PD25D_ISI_VSYNC _L_(121) /**< ISI signal: VSYNC on PD25 mux D*/ 664 #define MUX_PD25D_ISI_VSYNC _L_(3) /**< ISI signal line function value: VSYNC */ 665 #define PIO_PD25D_ISI_VSYNC (_UL_(1) << 25) 666 667 /* ========== PIO definition for MCAN0 peripheral ========== */ 668 #define PIN_PB3A_MCAN0_CANRX0 _L_(35) /**< MCAN0 signal: CANRX0 on PB3 mux A*/ 669 #define MUX_PB3A_MCAN0_CANRX0 _L_(0) /**< MCAN0 signal line function value: CANRX0 */ 670 #define PIO_PB3A_MCAN0_CANRX0 (_UL_(1) << 3) 671 672 #define PIN_PB2A_MCAN0_CANTX0 _L_(34) /**< MCAN0 signal: CANTX0 on PB2 mux A*/ 673 #define MUX_PB2A_MCAN0_CANTX0 _L_(0) /**< MCAN0 signal line function value: CANTX0 */ 674 #define PIO_PB2A_MCAN0_CANTX0 (_UL_(1) << 2) 675 676 /* ========== PIO definition for MCAN1 peripheral ========== */ 677 #define PIN_PC12C_MCAN1_CANRX1 _L_(76) /**< MCAN1 signal: CANRX1 on PC12 mux C*/ 678 #define MUX_PC12C_MCAN1_CANRX1 _L_(2) /**< MCAN1 signal line function value: CANRX1 */ 679 #define PIO_PC12C_MCAN1_CANRX1 (_UL_(1) << 12) 680 681 #define PIN_PD28B_MCAN1_CANRX1 _L_(124) /**< MCAN1 signal: CANRX1 on PD28 mux B*/ 682 #define MUX_PD28B_MCAN1_CANRX1 _L_(1) /**< MCAN1 signal line function value: CANRX1 */ 683 #define PIO_PD28B_MCAN1_CANRX1 (_UL_(1) << 28) 684 685 #define PIN_PC14C_MCAN1_CANTX1 _L_(78) /**< MCAN1 signal: CANTX1 on PC14 mux C*/ 686 #define MUX_PC14C_MCAN1_CANTX1 _L_(2) /**< MCAN1 signal line function value: CANTX1 */ 687 #define PIO_PC14C_MCAN1_CANTX1 (_UL_(1) << 14) 688 689 #define PIN_PD12B_MCAN1_CANTX1 _L_(108) /**< MCAN1 signal: CANTX1 on PD12 mux B*/ 690 #define MUX_PD12B_MCAN1_CANTX1 _L_(1) /**< MCAN1 signal line function value: CANTX1 */ 691 #define PIO_PD12B_MCAN1_CANTX1 (_UL_(1) << 12) 692 693 /* ========== PIO definition for MLB peripheral ========== */ 694 #define PIN_PB4C_MLB_MLBCLK _L_(36) /**< MLB signal: MLBCLK on PB4 mux C*/ 695 #define MUX_PB4C_MLB_MLBCLK _L_(2) /**< MLB signal line function value: MLBCLK */ 696 #define PIO_PB4C_MLB_MLBCLK (_UL_(1) << 4) 697 698 #define PIN_PB5C_MLB_MLBDAT _L_(37) /**< MLB signal: MLBDAT on PB5 mux C*/ 699 #define MUX_PB5C_MLB_MLBDAT _L_(2) /**< MLB signal line function value: MLBDAT */ 700 #define PIO_PB5C_MLB_MLBDAT (_UL_(1) << 5) 701 702 #define PIN_PD10D_MLB_MLBSIG _L_(106) /**< MLB signal: MLBSIG on PD10 mux D*/ 703 #define MUX_PD10D_MLB_MLBSIG _L_(3) /**< MLB signal line function value: MLBSIG */ 704 #define PIO_PD10D_MLB_MLBSIG (_UL_(1) << 10) 705 706 /* ========== PIO definition for PMC peripheral ========== */ 707 #define PIN_PA6B_PMC_PCK0 _L_(6) /**< PMC signal: PCK0 on PA6 mux B*/ 708 #define MUX_PA6B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PCK0 */ 709 #define PIO_PA6B_PMC_PCK0 (_UL_(1) << 6) 710 711 #define PIN_PB12D_PMC_PCK0 _L_(44) /**< PMC signal: PCK0 on PB12 mux D*/ 712 #define MUX_PB12D_PMC_PCK0 _L_(3) /**< PMC signal line function value: PCK0 */ 713 #define PIO_PB12D_PMC_PCK0 (_UL_(1) << 12) 714 715 #define PIN_PB13B_PMC_PCK0 _L_(45) /**< PMC signal: PCK0 on PB13 mux B*/ 716 #define MUX_PB13B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PCK0 */ 717 #define PIO_PB13B_PMC_PCK0 (_UL_(1) << 13) 718 719 #define PIN_PA17B_PMC_PCK1 _L_(17) /**< PMC signal: PCK1 on PA17 mux B*/ 720 #define MUX_PA17B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PCK1 */ 721 #define PIO_PA17B_PMC_PCK1 (_UL_(1) << 17) 722 723 #define PIN_PA21B_PMC_PCK1 _L_(21) /**< PMC signal: PCK1 on PA21 mux B*/ 724 #define MUX_PA21B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PCK1 */ 725 #define PIO_PA21B_PMC_PCK1 (_UL_(1) << 21) 726 727 #define PIN_PA3C_PMC_PCK2 _L_(3) /**< PMC signal: PCK2 on PA3 mux C*/ 728 #define MUX_PA3C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PCK2 */ 729 #define PIO_PA3C_PMC_PCK2 (_UL_(1) << 3) 730 731 #define PIN_PA18B_PMC_PCK2 _L_(18) /**< PMC signal: PCK2 on PA18 mux B*/ 732 #define MUX_PA18B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PCK2 */ 733 #define PIO_PA18B_PMC_PCK2 (_UL_(1) << 18) 734 735 #define PIN_PA31B_PMC_PCK2 _L_(31) /**< PMC signal: PCK2 on PA31 mux B*/ 736 #define MUX_PA31B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PCK2 */ 737 #define PIO_PA31B_PMC_PCK2 (_UL_(1) << 31) 738 739 #define PIN_PB3B_PMC_PCK2 _L_(35) /**< PMC signal: PCK2 on PB3 mux B*/ 740 #define MUX_PB3B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PCK2 */ 741 #define PIO_PB3B_PMC_PCK2 (_UL_(1) << 3) 742 743 #define PIN_PD31C_PMC_PCK2 _L_(127) /**< PMC signal: PCK2 on PD31 mux C*/ 744 #define MUX_PD31C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PCK2 */ 745 #define PIO_PD31C_PMC_PCK2 (_UL_(1) << 31) 746 747 /* ========== PIO definition for PWM0 peripheral ========== */ 748 #define PIN_PA10B_PWM0_PWMEXTRG0 _L_(10) /**< PWM0 signal: PWMEXTRG0 on PA10 mux B*/ 749 #define MUX_PA10B_PWM0_PWMEXTRG0 _L_(1) /**< PWM0 signal line function value: PWMEXTRG0 */ 750 #define PIO_PA10B_PWM0_PWMEXTRG0 (_UL_(1) << 10) 751 752 #define PIN_PA22B_PWM0_PWMEXTRG1 _L_(22) /**< PWM0 signal: PWMEXTRG1 on PA22 mux B*/ 753 #define MUX_PA22B_PWM0_PWMEXTRG1 _L_(1) /**< PWM0 signal line function value: PWMEXTRG1 */ 754 #define PIO_PA22B_PWM0_PWMEXTRG1 (_UL_(1) << 22) 755 756 #define PIN_PA9C_PWM0_PWMFI0 _L_(9) /**< PWM0 signal: PWMFI0 on PA9 mux C*/ 757 #define MUX_PA9C_PWM0_PWMFI0 _L_(2) /**< PWM0 signal line function value: PWMFI0 */ 758 #define PIO_PA9C_PWM0_PWMFI0 (_UL_(1) << 9) 759 760 #define PIN_PD8B_PWM0_PWMFI1 _L_(104) /**< PWM0 signal: PWMFI1 on PD8 mux B*/ 761 #define MUX_PD8B_PWM0_PWMFI1 _L_(1) /**< PWM0 signal line function value: PWMFI1 */ 762 #define PIO_PD8B_PWM0_PWMFI1 (_UL_(1) << 8) 763 764 #define PIN_PD9B_PWM0_PWMFI2 _L_(105) /**< PWM0 signal: PWMFI2 on PD9 mux B*/ 765 #define MUX_PD9B_PWM0_PWMFI2 _L_(1) /**< PWM0 signal line function value: PWMFI2 */ 766 #define PIO_PD9B_PWM0_PWMFI2 (_UL_(1) << 9) 767 768 #define PIN_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal: PWMH0 on PA0 mux A*/ 769 #define MUX_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWMH0 */ 770 #define PIO_PA0A_PWM0_PWMH0 (_UL_(1) << 0) 771 772 #define PIN_PA11B_PWM0_PWMH0 _L_(11) /**< PWM0 signal: PWMH0 on PA11 mux B*/ 773 #define MUX_PA11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWMH0 */ 774 #define PIO_PA11B_PWM0_PWMH0 (_UL_(1) << 11) 775 776 #define PIN_PA23B_PWM0_PWMH0 _L_(23) /**< PWM0 signal: PWMH0 on PA23 mux B*/ 777 #define MUX_PA23B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWMH0 */ 778 #define PIO_PA23B_PWM0_PWMH0 (_UL_(1) << 23) 779 780 #define PIN_PB0A_PWM0_PWMH0 _L_(32) /**< PWM0 signal: PWMH0 on PB0 mux A*/ 781 #define MUX_PB0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWMH0 */ 782 #define PIO_PB0A_PWM0_PWMH0 (_UL_(1) << 0) 783 784 #define PIN_PD11B_PWM0_PWMH0 _L_(107) /**< PWM0 signal: PWMH0 on PD11 mux B*/ 785 #define MUX_PD11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWMH0 */ 786 #define PIO_PD11B_PWM0_PWMH0 (_UL_(1) << 11) 787 788 #define PIN_PD20A_PWM0_PWMH0 _L_(116) /**< PWM0 signal: PWMH0 on PD20 mux A*/ 789 #define MUX_PD20A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWMH0 */ 790 #define PIO_PD20A_PWM0_PWMH0 (_UL_(1) << 20) 791 792 #define PIN_PA2A_PWM0_PWMH1 _L_(2) /**< PWM0 signal: PWMH1 on PA2 mux A*/ 793 #define MUX_PA2A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWMH1 */ 794 #define PIO_PA2A_PWM0_PWMH1 (_UL_(1) << 2) 795 796 #define PIN_PA12B_PWM0_PWMH1 _L_(12) /**< PWM0 signal: PWMH1 on PA12 mux B*/ 797 #define MUX_PA12B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWMH1 */ 798 #define PIO_PA12B_PWM0_PWMH1 (_UL_(1) << 12) 799 800 #define PIN_PA24B_PWM0_PWMH1 _L_(24) /**< PWM0 signal: PWMH1 on PA24 mux B*/ 801 #define MUX_PA24B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWMH1 */ 802 #define PIO_PA24B_PWM0_PWMH1 (_UL_(1) << 24) 803 804 #define PIN_PB1A_PWM0_PWMH1 _L_(33) /**< PWM0 signal: PWMH1 on PB1 mux A*/ 805 #define MUX_PB1A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWMH1 */ 806 #define PIO_PB1A_PWM0_PWMH1 (_UL_(1) << 1) 807 808 #define PIN_PD21A_PWM0_PWMH1 _L_(117) /**< PWM0 signal: PWMH1 on PD21 mux A*/ 809 #define MUX_PD21A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWMH1 */ 810 #define PIO_PD21A_PWM0_PWMH1 (_UL_(1) << 21) 811 812 #define PIN_PA13B_PWM0_PWMH2 _L_(13) /**< PWM0 signal: PWMH2 on PA13 mux B*/ 813 #define MUX_PA13B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ 814 #define PIO_PA13B_PWM0_PWMH2 (_UL_(1) << 13) 815 816 #define PIN_PA25B_PWM0_PWMH2 _L_(25) /**< PWM0 signal: PWMH2 on PA25 mux B*/ 817 #define MUX_PA25B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ 818 #define PIO_PA25B_PWM0_PWMH2 (_UL_(1) << 25) 819 820 #define PIN_PB4B_PWM0_PWMH2 _L_(36) /**< PWM0 signal: PWMH2 on PB4 mux B*/ 821 #define MUX_PB4B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ 822 #define PIO_PB4B_PWM0_PWMH2 (_UL_(1) << 4) 823 824 #define PIN_PC19B_PWM0_PWMH2 _L_(83) /**< PWM0 signal: PWMH2 on PC19 mux B*/ 825 #define MUX_PC19B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ 826 #define PIO_PC19B_PWM0_PWMH2 (_UL_(1) << 19) 827 828 #define PIN_PD22A_PWM0_PWMH2 _L_(118) /**< PWM0 signal: PWMH2 on PD22 mux A*/ 829 #define MUX_PD22A_PWM0_PWMH2 _L_(0) /**< PWM0 signal line function value: PWMH2 */ 830 #define PIO_PD22A_PWM0_PWMH2 (_UL_(1) << 22) 831 832 #define PIN_PA7B_PWM0_PWMH3 _L_(7) /**< PWM0 signal: PWMH3 on PA7 mux B*/ 833 #define MUX_PA7B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWMH3 */ 834 #define PIO_PA7B_PWM0_PWMH3 (_UL_(1) << 7) 835 836 #define PIN_PA14B_PWM0_PWMH3 _L_(14) /**< PWM0 signal: PWMH3 on PA14 mux B*/ 837 #define MUX_PA14B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWMH3 */ 838 #define PIO_PA14B_PWM0_PWMH3 (_UL_(1) << 14) 839 840 #define PIN_PA17C_PWM0_PWMH3 _L_(17) /**< PWM0 signal: PWMH3 on PA17 mux C*/ 841 #define MUX_PA17C_PWM0_PWMH3 _L_(2) /**< PWM0 signal line function value: PWMH3 */ 842 #define PIO_PA17C_PWM0_PWMH3 (_UL_(1) << 17) 843 844 #define PIN_PC13B_PWM0_PWMH3 _L_(77) /**< PWM0 signal: PWMH3 on PC13 mux B*/ 845 #define MUX_PC13B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWMH3 */ 846 #define PIO_PC13B_PWM0_PWMH3 (_UL_(1) << 13) 847 848 #define PIN_PC21B_PWM0_PWMH3 _L_(85) /**< PWM0 signal: PWMH3 on PC21 mux B*/ 849 #define MUX_PC21B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWMH3 */ 850 #define PIO_PC21B_PWM0_PWMH3 (_UL_(1) << 21) 851 852 #define PIN_PD23A_PWM0_PWMH3 _L_(119) /**< PWM0 signal: PWMH3 on PD23 mux A*/ 853 #define MUX_PD23A_PWM0_PWMH3 _L_(0) /**< PWM0 signal line function value: PWMH3 */ 854 #define PIO_PD23A_PWM0_PWMH3 (_UL_(1) << 23) 855 856 #define PIN_PA1A_PWM0_PWML0 _L_(1) /**< PWM0 signal: PWML0 on PA1 mux A*/ 857 #define MUX_PA1A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWML0 */ 858 #define PIO_PA1A_PWM0_PWML0 (_UL_(1) << 1) 859 860 #define PIN_PA19B_PWM0_PWML0 _L_(19) /**< PWM0 signal: PWML0 on PA19 mux B*/ 861 #define MUX_PA19B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ 862 #define PIO_PA19B_PWM0_PWML0 (_UL_(1) << 19) 863 864 #define PIN_PB5B_PWM0_PWML0 _L_(37) /**< PWM0 signal: PWML0 on PB5 mux B*/ 865 #define MUX_PB5B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ 866 #define PIO_PB5B_PWM0_PWML0 (_UL_(1) << 5) 867 868 #define PIN_PC0B_PWM0_PWML0 _L_(64) /**< PWM0 signal: PWML0 on PC0 mux B*/ 869 #define MUX_PC0B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ 870 #define PIO_PC0B_PWM0_PWML0 (_UL_(1) << 0) 871 872 #define PIN_PD10B_PWM0_PWML0 _L_(106) /**< PWM0 signal: PWML0 on PD10 mux B*/ 873 #define MUX_PD10B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ 874 #define PIO_PD10B_PWM0_PWML0 (_UL_(1) << 10) 875 876 #define PIN_PD24A_PWM0_PWML0 _L_(120) /**< PWM0 signal: PWML0 on PD24 mux A*/ 877 #define MUX_PD24A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWML0 */ 878 #define PIO_PD24A_PWM0_PWML0 (_UL_(1) << 24) 879 880 #define PIN_PA20B_PWM0_PWML1 _L_(20) /**< PWM0 signal: PWML1 on PA20 mux B*/ 881 #define MUX_PA20B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWML1 */ 882 #define PIO_PA20B_PWM0_PWML1 (_UL_(1) << 20) 883 884 #define PIN_PB12A_PWM0_PWML1 _L_(44) /**< PWM0 signal: PWML1 on PB12 mux A*/ 885 #define MUX_PB12A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWML1 */ 886 #define PIO_PB12A_PWM0_PWML1 (_UL_(1) << 12) 887 888 #define PIN_PC1B_PWM0_PWML1 _L_(65) /**< PWM0 signal: PWML1 on PC1 mux B*/ 889 #define MUX_PC1B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWML1 */ 890 #define PIO_PC1B_PWM0_PWML1 (_UL_(1) << 1) 891 892 #define PIN_PC18B_PWM0_PWML1 _L_(82) /**< PWM0 signal: PWML1 on PC18 mux B*/ 893 #define MUX_PC18B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWML1 */ 894 #define PIO_PC18B_PWM0_PWML1 (_UL_(1) << 18) 895 896 #define PIN_PD25A_PWM0_PWML1 _L_(121) /**< PWM0 signal: PWML1 on PD25 mux A*/ 897 #define MUX_PD25A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWML1 */ 898 #define PIO_PD25A_PWM0_PWML1 (_UL_(1) << 25) 899 900 #define PIN_PA16C_PWM0_PWML2 _L_(16) /**< PWM0 signal: PWML2 on PA16 mux C*/ 901 #define MUX_PA16C_PWM0_PWML2 _L_(2) /**< PWM0 signal line function value: PWML2 */ 902 #define PIO_PA16C_PWM0_PWML2 (_UL_(1) << 16) 903 904 #define PIN_PA30A_PWM0_PWML2 _L_(30) /**< PWM0 signal: PWML2 on PA30 mux A*/ 905 #define MUX_PA30A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWML2 */ 906 #define PIO_PA30A_PWM0_PWML2 (_UL_(1) << 30) 907 908 #define PIN_PB13A_PWM0_PWML2 _L_(45) /**< PWM0 signal: PWML2 on PB13 mux A*/ 909 #define MUX_PB13A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWML2 */ 910 #define PIO_PB13A_PWM0_PWML2 (_UL_(1) << 13) 911 912 #define PIN_PC2B_PWM0_PWML2 _L_(66) /**< PWM0 signal: PWML2 on PC2 mux B*/ 913 #define MUX_PC2B_PWM0_PWML2 _L_(1) /**< PWM0 signal line function value: PWML2 */ 914 #define PIO_PC2B_PWM0_PWML2 (_UL_(1) << 2) 915 916 #define PIN_PC20B_PWM0_PWML2 _L_(84) /**< PWM0 signal: PWML2 on PC20 mux B*/ 917 #define MUX_PC20B_PWM0_PWML2 _L_(1) /**< PWM0 signal line function value: PWML2 */ 918 #define PIO_PC20B_PWM0_PWML2 (_UL_(1) << 20) 919 920 #define PIN_PD26A_PWM0_PWML2 _L_(122) /**< PWM0 signal: PWML2 on PD26 mux A*/ 921 #define MUX_PD26A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWML2 */ 922 #define PIO_PD26A_PWM0_PWML2 (_UL_(1) << 26) 923 924 #define PIN_PA15C_PWM0_PWML3 _L_(15) /**< PWM0 signal: PWML3 on PA15 mux C*/ 925 #define MUX_PA15C_PWM0_PWML3 _L_(2) /**< PWM0 signal line function value: PWML3 */ 926 #define PIO_PA15C_PWM0_PWML3 (_UL_(1) << 15) 927 928 #define PIN_PC3B_PWM0_PWML3 _L_(67) /**< PWM0 signal: PWML3 on PC3 mux B*/ 929 #define MUX_PC3B_PWM0_PWML3 _L_(1) /**< PWM0 signal line function value: PWML3 */ 930 #define PIO_PC3B_PWM0_PWML3 (_UL_(1) << 3) 931 932 #define PIN_PC15B_PWM0_PWML3 _L_(79) /**< PWM0 signal: PWML3 on PC15 mux B*/ 933 #define MUX_PC15B_PWM0_PWML3 _L_(1) /**< PWM0 signal line function value: PWML3 */ 934 #define PIO_PC15B_PWM0_PWML3 (_UL_(1) << 15) 935 936 #define PIN_PC22B_PWM0_PWML3 _L_(86) /**< PWM0 signal: PWML3 on PC22 mux B*/ 937 #define MUX_PC22B_PWM0_PWML3 _L_(1) /**< PWM0 signal line function value: PWML3 */ 938 #define PIO_PC22B_PWM0_PWML3 (_UL_(1) << 22) 939 940 #define PIN_PD27A_PWM0_PWML3 _L_(123) /**< PWM0 signal: PWML3 on PD27 mux A*/ 941 #define MUX_PD27A_PWM0_PWML3 _L_(0) /**< PWM0 signal line function value: PWML3 */ 942 #define PIO_PD27A_PWM0_PWML3 (_UL_(1) << 27) 943 944 /* ========== PIO definition for PWM1 peripheral ========== */ 945 #define PIN_PA30B_PWM1_PWMEXTRG0 _L_(30) /**< PWM1 signal: PWMEXTRG0 on PA30 mux B*/ 946 #define MUX_PA30B_PWM1_PWMEXTRG0 _L_(1) /**< PWM1 signal line function value: PWMEXTRG0 */ 947 #define PIO_PA30B_PWM1_PWMEXTRG0 (_UL_(1) << 30) 948 949 #define PIN_PA18A_PWM1_PWMEXTRG1 _L_(18) /**< PWM1 signal: PWMEXTRG1 on PA18 mux A*/ 950 #define MUX_PA18A_PWM1_PWMEXTRG1 _L_(0) /**< PWM1 signal line function value: PWMEXTRG1 */ 951 #define PIO_PA18A_PWM1_PWMEXTRG1 (_UL_(1) << 18) 952 953 #define PIN_PA21C_PWM1_PWMFI0 _L_(21) /**< PWM1 signal: PWMFI0 on PA21 mux C*/ 954 #define MUX_PA21C_PWM1_PWMFI0 _L_(2) /**< PWM1 signal line function value: PWMFI0 */ 955 #define PIO_PA21C_PWM1_PWMFI0 (_UL_(1) << 21) 956 957 #define PIN_PA26D_PWM1_PWMFI1 _L_(26) /**< PWM1 signal: PWMFI1 on PA26 mux D*/ 958 #define MUX_PA26D_PWM1_PWMFI1 _L_(3) /**< PWM1 signal line function value: PWMFI1 */ 959 #define PIO_PA26D_PWM1_PWMFI1 (_UL_(1) << 26) 960 961 #define PIN_PA28D_PWM1_PWMFI2 _L_(28) /**< PWM1 signal: PWMFI2 on PA28 mux D*/ 962 #define MUX_PA28D_PWM1_PWMFI2 _L_(3) /**< PWM1 signal line function value: PWMFI2 */ 963 #define PIO_PA28D_PWM1_PWMFI2 (_UL_(1) << 28) 964 965 #define PIN_PA12C_PWM1_PWMH0 _L_(12) /**< PWM1 signal: PWMH0 on PA12 mux C*/ 966 #define MUX_PA12C_PWM1_PWMH0 _L_(2) /**< PWM1 signal line function value: PWMH0 */ 967 #define PIO_PA12C_PWM1_PWMH0 (_UL_(1) << 12) 968 969 #define PIN_PD1B_PWM1_PWMH0 _L_(97) /**< PWM1 signal: PWMH0 on PD1 mux B*/ 970 #define MUX_PD1B_PWM1_PWMH0 _L_(1) /**< PWM1 signal line function value: PWMH0 */ 971 #define PIO_PD1B_PWM1_PWMH0 (_UL_(1) << 1) 972 973 #define PIN_PA14C_PWM1_PWMH1 _L_(14) /**< PWM1 signal: PWMH1 on PA14 mux C*/ 974 #define MUX_PA14C_PWM1_PWMH1 _L_(2) /**< PWM1 signal line function value: PWMH1 */ 975 #define PIO_PA14C_PWM1_PWMH1 (_UL_(1) << 14) 976 977 #define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux B*/ 978 #define MUX_PD3B_PWM1_PWMH1 _L_(1) /**< PWM1 signal line function value: PWMH1 */ 979 #define PIO_PD3B_PWM1_PWMH1 (_UL_(1) << 3) 980 981 #define PIN_PA31D_PWM1_PWMH2 _L_(31) /**< PWM1 signal: PWMH2 on PA31 mux D*/ 982 #define MUX_PA31D_PWM1_PWMH2 _L_(3) /**< PWM1 signal line function value: PWMH2 */ 983 #define PIO_PA31D_PWM1_PWMH2 (_UL_(1) << 31) 984 985 #define PIN_PD5B_PWM1_PWMH2 _L_(101) /**< PWM1 signal: PWMH2 on PD5 mux B*/ 986 #define MUX_PD5B_PWM1_PWMH2 _L_(1) /**< PWM1 signal line function value: PWMH2 */ 987 #define PIO_PD5B_PWM1_PWMH2 (_UL_(1) << 5) 988 989 #define PIN_PA8A_PWM1_PWMH3 _L_(8) /**< PWM1 signal: PWMH3 on PA8 mux A*/ 990 #define MUX_PA8A_PWM1_PWMH3 _L_(0) /**< PWM1 signal line function value: PWMH3 */ 991 #define PIO_PA8A_PWM1_PWMH3 (_UL_(1) << 8) 992 993 #define PIN_PD7B_PWM1_PWMH3 _L_(103) /**< PWM1 signal: PWMH3 on PD7 mux B*/ 994 #define MUX_PD7B_PWM1_PWMH3 _L_(1) /**< PWM1 signal line function value: PWMH3 */ 995 #define PIO_PD7B_PWM1_PWMH3 (_UL_(1) << 7) 996 997 #define PIN_PA11C_PWM1_PWML0 _L_(11) /**< PWM1 signal: PWML0 on PA11 mux C*/ 998 #define MUX_PA11C_PWM1_PWML0 _L_(2) /**< PWM1 signal line function value: PWML0 */ 999 #define PIO_PA11C_PWM1_PWML0 (_UL_(1) << 11) 1000 1001 #define PIN_PD0B_PWM1_PWML0 _L_(96) /**< PWM1 signal: PWML0 on PD0 mux B*/ 1002 #define MUX_PD0B_PWM1_PWML0 _L_(1) /**< PWM1 signal line function value: PWML0 */ 1003 #define PIO_PD0B_PWM1_PWML0 (_UL_(1) << 0) 1004 1005 #define PIN_PA13C_PWM1_PWML1 _L_(13) /**< PWM1 signal: PWML1 on PA13 mux C*/ 1006 #define MUX_PA13C_PWM1_PWML1 _L_(2) /**< PWM1 signal line function value: PWML1 */ 1007 #define PIO_PA13C_PWM1_PWML1 (_UL_(1) << 13) 1008 1009 #define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWML1 on PD2 mux B*/ 1010 #define MUX_PD2B_PWM1_PWML1 _L_(1) /**< PWM1 signal line function value: PWML1 */ 1011 #define PIO_PD2B_PWM1_PWML1 (_UL_(1) << 2) 1012 1013 #define PIN_PA23D_PWM1_PWML2 _L_(23) /**< PWM1 signal: PWML2 on PA23 mux D*/ 1014 #define MUX_PA23D_PWM1_PWML2 _L_(3) /**< PWM1 signal line function value: PWML2 */ 1015 #define PIO_PA23D_PWM1_PWML2 (_UL_(1) << 23) 1016 1017 #define PIN_PD4B_PWM1_PWML2 _L_(100) /**< PWM1 signal: PWML2 on PD4 mux B*/ 1018 #define MUX_PD4B_PWM1_PWML2 _L_(1) /**< PWM1 signal line function value: PWML2 */ 1019 #define PIO_PD4B_PWM1_PWML2 (_UL_(1) << 4) 1020 1021 #define PIN_PA5A_PWM1_PWML3 _L_(5) /**< PWM1 signal: PWML3 on PA5 mux A*/ 1022 #define MUX_PA5A_PWM1_PWML3 _L_(0) /**< PWM1 signal line function value: PWML3 */ 1023 #define PIO_PA5A_PWM1_PWML3 (_UL_(1) << 5) 1024 1025 #define PIN_PD6B_PWM1_PWML3 _L_(102) /**< PWM1 signal: PWML3 on PD6 mux B*/ 1026 #define MUX_PD6B_PWM1_PWML3 _L_(1) /**< PWM1 signal line function value: PWML3 */ 1027 #define PIO_PD6B_PWM1_PWML3 (_UL_(1) << 6) 1028 1029 /* ========== PIO definition for QSPI peripheral ========== */ 1030 #define PIN_PA11A_QSPI_QCS _L_(11) /**< QSPI signal: QCS on PA11 mux A*/ 1031 #define MUX_PA11A_QSPI_QCS _L_(0) /**< QSPI signal line function value: QCS */ 1032 #define PIO_PA11A_QSPI_QCS (_UL_(1) << 11) 1033 1034 #define PIN_PA13A_QSPI_QIO0 _L_(13) /**< QSPI signal: QIO0 on PA13 mux A*/ 1035 #define MUX_PA13A_QSPI_QIO0 _L_(0) /**< QSPI signal line function value: QIO0 */ 1036 #define PIO_PA13A_QSPI_QIO0 (_UL_(1) << 13) 1037 1038 #define PIN_PA12A_QSPI_QIO1 _L_(12) /**< QSPI signal: QIO1 on PA12 mux A*/ 1039 #define MUX_PA12A_QSPI_QIO1 _L_(0) /**< QSPI signal line function value: QIO1 */ 1040 #define PIO_PA12A_QSPI_QIO1 (_UL_(1) << 12) 1041 1042 #define PIN_PA17A_QSPI_QIO2 _L_(17) /**< QSPI signal: QIO2 on PA17 mux A*/ 1043 #define MUX_PA17A_QSPI_QIO2 _L_(0) /**< QSPI signal line function value: QIO2 */ 1044 #define PIO_PA17A_QSPI_QIO2 (_UL_(1) << 17) 1045 1046 #define PIN_PD31A_QSPI_QIO3 _L_(127) /**< QSPI signal: QIO3 on PD31 mux A*/ 1047 #define MUX_PD31A_QSPI_QIO3 _L_(0) /**< QSPI signal line function value: QIO3 */ 1048 #define PIO_PD31A_QSPI_QIO3 (_UL_(1) << 31) 1049 1050 #define PIN_PA14A_QSPI_QSCK _L_(14) /**< QSPI signal: QSCK on PA14 mux A*/ 1051 #define MUX_PA14A_QSPI_QSCK _L_(0) /**< QSPI signal line function value: QSCK */ 1052 #define PIO_PA14A_QSPI_QSCK (_UL_(1) << 14) 1053 1054 /* ========== PIO definition for SDRAMC peripheral ========== */ 1055 #define PIN_PC18A_SDRAMC_A0 _L_(82) /**< SDRAMC signal: A0 on PC18 mux A*/ 1056 #define MUX_PC18A_SDRAMC_A0 _L_(0) /**< SDRAMC signal line function value: A0 */ 1057 #define PIO_PC18A_SDRAMC_A0 (_UL_(1) << 18) 1058 1059 #define PIN_PC18A_SDRAMC_NBS0 _L_(82) /**< SDRAMC signal: NBS0 on PC18 mux A*/ 1060 #define MUX_PC18A_SDRAMC_NBS0 _L_(0) /**< SDRAMC signal line function value: NBS0 */ 1061 #define PIO_PC18A_SDRAMC_NBS0 (_UL_(1) << 18) 1062 1063 #define PIN_PC19A_SDRAMC_A1 _L_(83) /**< SDRAMC signal: A1 on PC19 mux A*/ 1064 #define MUX_PC19A_SDRAMC_A1 _L_(0) /**< SDRAMC signal line function value: A1 */ 1065 #define PIO_PC19A_SDRAMC_A1 (_UL_(1) << 19) 1066 1067 #define PIN_PC20A_SDRAMC_A2 _L_(84) /**< SDRAMC signal: A2 on PC20 mux A*/ 1068 #define MUX_PC20A_SDRAMC_A2 _L_(0) /**< SDRAMC signal line function value: A2 */ 1069 #define PIO_PC20A_SDRAMC_A2 (_UL_(1) << 20) 1070 1071 #define PIN_PC21A_SDRAMC_A3 _L_(85) /**< SDRAMC signal: A3 on PC21 mux A*/ 1072 #define MUX_PC21A_SDRAMC_A3 _L_(0) /**< SDRAMC signal line function value: A3 */ 1073 #define PIO_PC21A_SDRAMC_A3 (_UL_(1) << 21) 1074 1075 #define PIN_PC22A_SDRAMC_A4 _L_(86) /**< SDRAMC signal: A4 on PC22 mux A*/ 1076 #define MUX_PC22A_SDRAMC_A4 _L_(0) /**< SDRAMC signal line function value: A4 */ 1077 #define PIO_PC22A_SDRAMC_A4 (_UL_(1) << 22) 1078 1079 #define PIN_PC23A_SDRAMC_A5 _L_(87) /**< SDRAMC signal: A5 on PC23 mux A*/ 1080 #define MUX_PC23A_SDRAMC_A5 _L_(0) /**< SDRAMC signal line function value: A5 */ 1081 #define PIO_PC23A_SDRAMC_A5 (_UL_(1) << 23) 1082 1083 #define PIN_PC24A_SDRAMC_A6 _L_(88) /**< SDRAMC signal: A6 on PC24 mux A*/ 1084 #define MUX_PC24A_SDRAMC_A6 _L_(0) /**< SDRAMC signal line function value: A6 */ 1085 #define PIO_PC24A_SDRAMC_A6 (_UL_(1) << 24) 1086 1087 #define PIN_PC25A_SDRAMC_A7 _L_(89) /**< SDRAMC signal: A7 on PC25 mux A*/ 1088 #define MUX_PC25A_SDRAMC_A7 _L_(0) /**< SDRAMC signal line function value: A7 */ 1089 #define PIO_PC25A_SDRAMC_A7 (_UL_(1) << 25) 1090 1091 #define PIN_PC26A_SDRAMC_A8 _L_(90) /**< SDRAMC signal: A8 on PC26 mux A*/ 1092 #define MUX_PC26A_SDRAMC_A8 _L_(0) /**< SDRAMC signal line function value: A8 */ 1093 #define PIO_PC26A_SDRAMC_A8 (_UL_(1) << 26) 1094 1095 #define PIN_PC27A_SDRAMC_A9 _L_(91) /**< SDRAMC signal: A9 on PC27 mux A*/ 1096 #define MUX_PC27A_SDRAMC_A9 _L_(0) /**< SDRAMC signal line function value: A9 */ 1097 #define PIO_PC27A_SDRAMC_A9 (_UL_(1) << 27) 1098 1099 #define PIN_PC28A_SDRAMC_A10 _L_(92) /**< SDRAMC signal: A10 on PC28 mux A*/ 1100 #define MUX_PC28A_SDRAMC_A10 _L_(0) /**< SDRAMC signal line function value: A10 */ 1101 #define PIO_PC28A_SDRAMC_A10 (_UL_(1) << 28) 1102 1103 #define PIN_PC29A_SDRAMC_A11 _L_(93) /**< SDRAMC signal: A11 on PC29 mux A*/ 1104 #define MUX_PC29A_SDRAMC_A11 _L_(0) /**< SDRAMC signal line function value: A11 */ 1105 #define PIO_PC29A_SDRAMC_A11 (_UL_(1) << 29) 1106 1107 #define PIN_PC30A_SDRAMC_A12 _L_(94) /**< SDRAMC signal: A12 on PC30 mux A*/ 1108 #define MUX_PC30A_SDRAMC_A12 _L_(0) /**< SDRAMC signal line function value: A12 */ 1109 #define PIO_PC30A_SDRAMC_A12 (_UL_(1) << 30) 1110 1111 #define PIN_PC31A_SDRAMC_A13 _L_(95) /**< SDRAMC signal: A13 on PC31 mux A*/ 1112 #define MUX_PC31A_SDRAMC_A13 _L_(0) /**< SDRAMC signal line function value: A13 */ 1113 #define PIO_PC31A_SDRAMC_A13 (_UL_(1) << 31) 1114 1115 #define PIN_PA18C_SDRAMC_A14 _L_(18) /**< SDRAMC signal: A14 on PA18 mux C*/ 1116 #define MUX_PA18C_SDRAMC_A14 _L_(2) /**< SDRAMC signal line function value: A14 */ 1117 #define PIO_PA18C_SDRAMC_A14 (_UL_(1) << 18) 1118 1119 #define PIN_PA19C_SDRAMC_A15 _L_(19) /**< SDRAMC signal: A15 on PA19 mux C*/ 1120 #define MUX_PA19C_SDRAMC_A15 _L_(2) /**< SDRAMC signal line function value: A15 */ 1121 #define PIO_PA19C_SDRAMC_A15 (_UL_(1) << 19) 1122 1123 #define PIN_PA20C_SDRAMC_A16 _L_(20) /**< SDRAMC signal: A16 on PA20 mux C*/ 1124 #define MUX_PA20C_SDRAMC_A16 _L_(2) /**< SDRAMC signal line function value: A16 */ 1125 #define PIO_PA20C_SDRAMC_A16 (_UL_(1) << 20) 1126 1127 #define PIN_PA20C_SDRAMC_BA0 _L_(20) /**< SDRAMC signal: BA0 on PA20 mux C*/ 1128 #define MUX_PA20C_SDRAMC_BA0 _L_(2) /**< SDRAMC signal line function value: BA0 */ 1129 #define PIO_PA20C_SDRAMC_BA0 (_UL_(1) << 20) 1130 1131 #define PIN_PA0C_SDRAMC_A17 _L_(0) /**< SDRAMC signal: A17 on PA0 mux C*/ 1132 #define MUX_PA0C_SDRAMC_A17 _L_(2) /**< SDRAMC signal line function value: A17 */ 1133 #define PIO_PA0C_SDRAMC_A17 (_UL_(1) << 0) 1134 1135 #define PIN_PA0C_SDRAMC_BA1 _L_(0) /**< SDRAMC signal: BA1 on PA0 mux C*/ 1136 #define MUX_PA0C_SDRAMC_BA1 _L_(2) /**< SDRAMC signal line function value: BA1 */ 1137 #define PIO_PA0C_SDRAMC_BA1 (_UL_(1) << 0) 1138 1139 #define PIN_PA1C_SDRAMC_A18 _L_(1) /**< SDRAMC signal: A18 on PA1 mux C*/ 1140 #define MUX_PA1C_SDRAMC_A18 _L_(2) /**< SDRAMC signal line function value: A18 */ 1141 #define PIO_PA1C_SDRAMC_A18 (_UL_(1) << 1) 1142 1143 #define PIN_PA23C_SDRAMC_A19 _L_(23) /**< SDRAMC signal: A19 on PA23 mux C*/ 1144 #define MUX_PA23C_SDRAMC_A19 _L_(2) /**< SDRAMC signal line function value: A19 */ 1145 #define PIO_PA23C_SDRAMC_A19 (_UL_(1) << 23) 1146 1147 #define PIN_PA24C_SDRAMC_A20 _L_(24) /**< SDRAMC signal: A20 on PA24 mux C*/ 1148 #define MUX_PA24C_SDRAMC_A20 _L_(2) /**< SDRAMC signal line function value: A20 */ 1149 #define PIO_PA24C_SDRAMC_A20 (_UL_(1) << 24) 1150 1151 #define PIN_PC16A_SDRAMC_A21 _L_(80) /**< SDRAMC signal: A21 on PC16 mux A*/ 1152 #define MUX_PC16A_SDRAMC_A21 _L_(0) /**< SDRAMC signal line function value: A21 */ 1153 #define PIO_PC16A_SDRAMC_A21 (_UL_(1) << 16) 1154 1155 #define PIN_PC16A_SDRAMC_NANDALE _L_(80) /**< SDRAMC signal: NANDALE on PC16 mux A*/ 1156 #define MUX_PC16A_SDRAMC_NANDALE _L_(0) /**< SDRAMC signal line function value: NANDALE */ 1157 #define PIO_PC16A_SDRAMC_NANDALE (_UL_(1) << 16) 1158 1159 #define PIN_PC17A_SDRAMC_A22 _L_(81) /**< SDRAMC signal: A22 on PC17 mux A*/ 1160 #define MUX_PC17A_SDRAMC_A22 _L_(0) /**< SDRAMC signal line function value: A22 */ 1161 #define PIO_PC17A_SDRAMC_A22 (_UL_(1) << 17) 1162 1163 #define PIN_PC17A_SDRAMC_NANDCLE _L_(81) /**< SDRAMC signal: NANDCLE on PC17 mux A*/ 1164 #define MUX_PC17A_SDRAMC_NANDCLE _L_(0) /**< SDRAMC signal line function value: NANDCLE */ 1165 #define PIO_PC17A_SDRAMC_NANDCLE (_UL_(1) << 17) 1166 1167 #define PIN_PA25C_SDRAMC_A23 _L_(25) /**< SDRAMC signal: A23 on PA25 mux C*/ 1168 #define MUX_PA25C_SDRAMC_A23 _L_(2) /**< SDRAMC signal line function value: A23 */ 1169 #define PIO_PA25C_SDRAMC_A23 (_UL_(1) << 25) 1170 1171 #define PIN_PD17C_SDRAMC_CAS _L_(113) /**< SDRAMC signal: CAS on PD17 mux C*/ 1172 #define MUX_PD17C_SDRAMC_CAS _L_(2) /**< SDRAMC signal line function value: CAS */ 1173 #define PIO_PD17C_SDRAMC_CAS (_UL_(1) << 17) 1174 1175 #define PIN_PC0A_SDRAMC_D0 _L_(64) /**< SDRAMC signal: D0 on PC0 mux A*/ 1176 #define MUX_PC0A_SDRAMC_D0 _L_(0) /**< SDRAMC signal line function value: D0 */ 1177 #define PIO_PC0A_SDRAMC_D0 (_UL_(1) << 0) 1178 1179 #define PIN_PC1A_SDRAMC_D1 _L_(65) /**< SDRAMC signal: D1 on PC1 mux A*/ 1180 #define MUX_PC1A_SDRAMC_D1 _L_(0) /**< SDRAMC signal line function value: D1 */ 1181 #define PIO_PC1A_SDRAMC_D1 (_UL_(1) << 1) 1182 1183 #define PIN_PC2A_SDRAMC_D2 _L_(66) /**< SDRAMC signal: D2 on PC2 mux A*/ 1184 #define MUX_PC2A_SDRAMC_D2 _L_(0) /**< SDRAMC signal line function value: D2 */ 1185 #define PIO_PC2A_SDRAMC_D2 (_UL_(1) << 2) 1186 1187 #define PIN_PC3A_SDRAMC_D3 _L_(67) /**< SDRAMC signal: D3 on PC3 mux A*/ 1188 #define MUX_PC3A_SDRAMC_D3 _L_(0) /**< SDRAMC signal line function value: D3 */ 1189 #define PIO_PC3A_SDRAMC_D3 (_UL_(1) << 3) 1190 1191 #define PIN_PC4A_SDRAMC_D4 _L_(68) /**< SDRAMC signal: D4 on PC4 mux A*/ 1192 #define MUX_PC4A_SDRAMC_D4 _L_(0) /**< SDRAMC signal line function value: D4 */ 1193 #define PIO_PC4A_SDRAMC_D4 (_UL_(1) << 4) 1194 1195 #define PIN_PC5A_SDRAMC_D5 _L_(69) /**< SDRAMC signal: D5 on PC5 mux A*/ 1196 #define MUX_PC5A_SDRAMC_D5 _L_(0) /**< SDRAMC signal line function value: D5 */ 1197 #define PIO_PC5A_SDRAMC_D5 (_UL_(1) << 5) 1198 1199 #define PIN_PC6A_SDRAMC_D6 _L_(70) /**< SDRAMC signal: D6 on PC6 mux A*/ 1200 #define MUX_PC6A_SDRAMC_D6 _L_(0) /**< SDRAMC signal line function value: D6 */ 1201 #define PIO_PC6A_SDRAMC_D6 (_UL_(1) << 6) 1202 1203 #define PIN_PC7A_SDRAMC_D7 _L_(71) /**< SDRAMC signal: D7 on PC7 mux A*/ 1204 #define MUX_PC7A_SDRAMC_D7 _L_(0) /**< SDRAMC signal line function value: D7 */ 1205 #define PIO_PC7A_SDRAMC_D7 (_UL_(1) << 7) 1206 1207 #define PIN_PE0A_SDRAMC_D8 _L_(128) /**< SDRAMC signal: D8 on PE0 mux A*/ 1208 #define MUX_PE0A_SDRAMC_D8 _L_(0) /**< SDRAMC signal line function value: D8 */ 1209 #define PIO_PE0A_SDRAMC_D8 (_UL_(1) << 0) 1210 1211 #define PIN_PE1A_SDRAMC_D9 _L_(129) /**< SDRAMC signal: D9 on PE1 mux A*/ 1212 #define MUX_PE1A_SDRAMC_D9 _L_(0) /**< SDRAMC signal line function value: D9 */ 1213 #define PIO_PE1A_SDRAMC_D9 (_UL_(1) << 1) 1214 1215 #define PIN_PE2A_SDRAMC_D10 _L_(130) /**< SDRAMC signal: D10 on PE2 mux A*/ 1216 #define MUX_PE2A_SDRAMC_D10 _L_(0) /**< SDRAMC signal line function value: D10 */ 1217 #define PIO_PE2A_SDRAMC_D10 (_UL_(1) << 2) 1218 1219 #define PIN_PE3A_SDRAMC_D11 _L_(131) /**< SDRAMC signal: D11 on PE3 mux A*/ 1220 #define MUX_PE3A_SDRAMC_D11 _L_(0) /**< SDRAMC signal line function value: D11 */ 1221 #define PIO_PE3A_SDRAMC_D11 (_UL_(1) << 3) 1222 1223 #define PIN_PE4A_SDRAMC_D12 _L_(132) /**< SDRAMC signal: D12 on PE4 mux A*/ 1224 #define MUX_PE4A_SDRAMC_D12 _L_(0) /**< SDRAMC signal line function value: D12 */ 1225 #define PIO_PE4A_SDRAMC_D12 (_UL_(1) << 4) 1226 1227 #define PIN_PE5A_SDRAMC_D13 _L_(133) /**< SDRAMC signal: D13 on PE5 mux A*/ 1228 #define MUX_PE5A_SDRAMC_D13 _L_(0) /**< SDRAMC signal line function value: D13 */ 1229 #define PIO_PE5A_SDRAMC_D13 (_UL_(1) << 5) 1230 1231 #define PIN_PA15A_SDRAMC_D14 _L_(15) /**< SDRAMC signal: D14 on PA15 mux A*/ 1232 #define MUX_PA15A_SDRAMC_D14 _L_(0) /**< SDRAMC signal line function value: D14 */ 1233 #define PIO_PA15A_SDRAMC_D14 (_UL_(1) << 15) 1234 1235 #define PIN_PA16A_SDRAMC_D15 _L_(16) /**< SDRAMC signal: D15 on PA16 mux A*/ 1236 #define MUX_PA16A_SDRAMC_D15 _L_(0) /**< SDRAMC signal line function value: D15 */ 1237 #define PIO_PA16A_SDRAMC_D15 (_UL_(1) << 16) 1238 1239 #define PIN_PC9A_SDRAMC_NANDOE _L_(73) /**< SDRAMC signal: NANDOE on PC9 mux A*/ 1240 #define MUX_PC9A_SDRAMC_NANDOE _L_(0) /**< SDRAMC signal line function value: NANDOE */ 1241 #define PIO_PC9A_SDRAMC_NANDOE (_UL_(1) << 9) 1242 1243 #define PIN_PC10A_SDRAMC_NANDWE _L_(74) /**< SDRAMC signal: NANDWE on PC10 mux A*/ 1244 #define MUX_PC10A_SDRAMC_NANDWE _L_(0) /**< SDRAMC signal line function value: NANDWE */ 1245 #define PIO_PC10A_SDRAMC_NANDWE (_UL_(1) << 10) 1246 1247 #define PIN_PC14A_SDRAMC_NCS0 _L_(78) /**< SDRAMC signal: NCS0 on PC14 mux A*/ 1248 #define MUX_PC14A_SDRAMC_NCS0 _L_(0) /**< SDRAMC signal line function value: NCS0 */ 1249 #define PIO_PC14A_SDRAMC_NCS0 (_UL_(1) << 14) 1250 1251 #define PIN_PC15A_SDRAMC_NCS1 _L_(79) /**< SDRAMC signal: NCS1 on PC15 mux A*/ 1252 #define MUX_PC15A_SDRAMC_NCS1 _L_(0) /**< SDRAMC signal line function value: NCS1 */ 1253 #define PIO_PC15A_SDRAMC_NCS1 (_UL_(1) << 15) 1254 1255 #define PIN_PC15A_SDRAMC_SDCS _L_(79) /**< SDRAMC signal: SDCS on PC15 mux A*/ 1256 #define MUX_PC15A_SDRAMC_SDCS _L_(0) /**< SDRAMC signal line function value: SDCS */ 1257 #define PIO_PC15A_SDRAMC_SDCS (_UL_(1) << 15) 1258 1259 #define PIN_PD18A_SDRAMC_NCS1 _L_(114) /**< SDRAMC signal: NCS1 on PD18 mux A*/ 1260 #define MUX_PD18A_SDRAMC_NCS1 _L_(0) /**< SDRAMC signal line function value: NCS1 */ 1261 #define PIO_PD18A_SDRAMC_NCS1 (_UL_(1) << 18) 1262 1263 #define PIN_PD18A_SDRAMC_SDCS _L_(114) /**< SDRAMC signal: SDCS on PD18 mux A*/ 1264 #define MUX_PD18A_SDRAMC_SDCS _L_(0) /**< SDRAMC signal line function value: SDCS */ 1265 #define PIO_PD18A_SDRAMC_SDCS (_UL_(1) << 18) 1266 1267 #define PIN_PA22C_SDRAMC_NCS2 _L_(22) /**< SDRAMC signal: NCS2 on PA22 mux C*/ 1268 #define MUX_PA22C_SDRAMC_NCS2 _L_(2) /**< SDRAMC signal line function value: NCS2 */ 1269 #define PIO_PA22C_SDRAMC_NCS2 (_UL_(1) << 22) 1270 1271 #define PIN_PC12A_SDRAMC_NCS3 _L_(76) /**< SDRAMC signal: NCS3 on PC12 mux A*/ 1272 #define MUX_PC12A_SDRAMC_NCS3 _L_(0) /**< SDRAMC signal line function value: NCS3 */ 1273 #define PIO_PC12A_SDRAMC_NCS3 (_UL_(1) << 12) 1274 1275 #define PIN_PD19A_SDRAMC_NCS3 _L_(115) /**< SDRAMC signal: NCS3 on PD19 mux A*/ 1276 #define MUX_PD19A_SDRAMC_NCS3 _L_(0) /**< SDRAMC signal line function value: NCS3 */ 1277 #define PIO_PD19A_SDRAMC_NCS3 (_UL_(1) << 19) 1278 1279 #define PIN_PC11A_SDRAMC_NRD _L_(75) /**< SDRAMC signal: NRD on PC11 mux A*/ 1280 #define MUX_PC11A_SDRAMC_NRD _L_(0) /**< SDRAMC signal line function value: NRD */ 1281 #define PIO_PC11A_SDRAMC_NRD (_UL_(1) << 11) 1282 1283 #define PIN_PC13A_SDRAMC_NWAIT _L_(77) /**< SDRAMC signal: NWAIT on PC13 mux A*/ 1284 #define MUX_PC13A_SDRAMC_NWAIT _L_(0) /**< SDRAMC signal line function value: NWAIT */ 1285 #define PIO_PC13A_SDRAMC_NWAIT (_UL_(1) << 13) 1286 1287 #define PIN_PC8A_SDRAMC_NWR0 _L_(72) /**< SDRAMC signal: NWR0 on PC8 mux A*/ 1288 #define MUX_PC8A_SDRAMC_NWR0 _L_(0) /**< SDRAMC signal line function value: NWR0 */ 1289 #define PIO_PC8A_SDRAMC_NWR0 (_UL_(1) << 8) 1290 1291 #define PIN_PC8A_SDRAMC_NWE _L_(72) /**< SDRAMC signal: NWE on PC8 mux A*/ 1292 #define MUX_PC8A_SDRAMC_NWE _L_(0) /**< SDRAMC signal line function value: NWE */ 1293 #define PIO_PC8A_SDRAMC_NWE (_UL_(1) << 8) 1294 1295 #define PIN_PD15C_SDRAMC_NWR1 _L_(111) /**< SDRAMC signal: NWR1 on PD15 mux C*/ 1296 #define MUX_PD15C_SDRAMC_NWR1 _L_(2) /**< SDRAMC signal line function value: NWR1 */ 1297 #define PIO_PD15C_SDRAMC_NWR1 (_UL_(1) << 15) 1298 1299 #define PIN_PD15C_SDRAMC_NBS1 _L_(111) /**< SDRAMC signal: NBS1 on PD15 mux C*/ 1300 #define MUX_PD15C_SDRAMC_NBS1 _L_(2) /**< SDRAMC signal line function value: NBS1 */ 1301 #define PIO_PD15C_SDRAMC_NBS1 (_UL_(1) << 15) 1302 1303 #define PIN_PD16C_SDRAMC_RAS _L_(112) /**< SDRAMC signal: RAS on PD16 mux C*/ 1304 #define MUX_PD16C_SDRAMC_RAS _L_(2) /**< SDRAMC signal line function value: RAS */ 1305 #define PIO_PD16C_SDRAMC_RAS (_UL_(1) << 16) 1306 1307 #define PIN_PC13C_SDRAMC_SDA10 _L_(77) /**< SDRAMC signal: SDA10 on PC13 mux C*/ 1308 #define MUX_PC13C_SDRAMC_SDA10 _L_(2) /**< SDRAMC signal line function value: SDA10 */ 1309 #define PIO_PC13C_SDRAMC_SDA10 (_UL_(1) << 13) 1310 1311 #define PIN_PD13C_SDRAMC_SDA10 _L_(109) /**< SDRAMC signal: SDA10 on PD13 mux C*/ 1312 #define MUX_PD13C_SDRAMC_SDA10 _L_(2) /**< SDRAMC signal line function value: SDA10 */ 1313 #define PIO_PD13C_SDRAMC_SDA10 (_UL_(1) << 13) 1314 1315 #define PIN_PD23C_SDRAMC_SDCK _L_(119) /**< SDRAMC signal: SDCK on PD23 mux C*/ 1316 #define MUX_PD23C_SDRAMC_SDCK _L_(2) /**< SDRAMC signal line function value: SDCK */ 1317 #define PIO_PD23C_SDRAMC_SDCK (_UL_(1) << 23) 1318 1319 #define PIN_PD14C_SDRAMC_SDCKE _L_(110) /**< SDRAMC signal: SDCKE on PD14 mux C*/ 1320 #define MUX_PD14C_SDRAMC_SDCKE _L_(2) /**< SDRAMC signal line function value: SDCKE */ 1321 #define PIO_PD14C_SDRAMC_SDCKE (_UL_(1) << 14) 1322 1323 #define PIN_PD29C_SDRAMC_SDWE _L_(125) /**< SDRAMC signal: SDWE on PD29 mux C*/ 1324 #define MUX_PD29C_SDRAMC_SDWE _L_(2) /**< SDRAMC signal line function value: SDWE */ 1325 #define PIO_PD29C_SDRAMC_SDWE (_UL_(1) << 29) 1326 1327 /* ========== PIO definition for SMC peripheral ========== */ 1328 #define PIN_PC18A_SMC_A0 _L_(82) /**< SMC signal: A0 on PC18 mux A*/ 1329 #define MUX_PC18A_SMC_A0 _L_(0) /**< SMC signal line function value: A0 */ 1330 #define PIO_PC18A_SMC_A0 (_UL_(1) << 18) 1331 1332 #define PIN_PC18A_SMC_NBS0 _L_(82) /**< SMC signal: NBS0 on PC18 mux A*/ 1333 #define MUX_PC18A_SMC_NBS0 _L_(0) /**< SMC signal line function value: NBS0 */ 1334 #define PIO_PC18A_SMC_NBS0 (_UL_(1) << 18) 1335 1336 #define PIN_PC19A_SMC_A1 _L_(83) /**< SMC signal: A1 on PC19 mux A*/ 1337 #define MUX_PC19A_SMC_A1 _L_(0) /**< SMC signal line function value: A1 */ 1338 #define PIO_PC19A_SMC_A1 (_UL_(1) << 19) 1339 1340 #define PIN_PC20A_SMC_A2 _L_(84) /**< SMC signal: A2 on PC20 mux A*/ 1341 #define MUX_PC20A_SMC_A2 _L_(0) /**< SMC signal line function value: A2 */ 1342 #define PIO_PC20A_SMC_A2 (_UL_(1) << 20) 1343 1344 #define PIN_PC21A_SMC_A3 _L_(85) /**< SMC signal: A3 on PC21 mux A*/ 1345 #define MUX_PC21A_SMC_A3 _L_(0) /**< SMC signal line function value: A3 */ 1346 #define PIO_PC21A_SMC_A3 (_UL_(1) << 21) 1347 1348 #define PIN_PC22A_SMC_A4 _L_(86) /**< SMC signal: A4 on PC22 mux A*/ 1349 #define MUX_PC22A_SMC_A4 _L_(0) /**< SMC signal line function value: A4 */ 1350 #define PIO_PC22A_SMC_A4 (_UL_(1) << 22) 1351 1352 #define PIN_PC23A_SMC_A5 _L_(87) /**< SMC signal: A5 on PC23 mux A*/ 1353 #define MUX_PC23A_SMC_A5 _L_(0) /**< SMC signal line function value: A5 */ 1354 #define PIO_PC23A_SMC_A5 (_UL_(1) << 23) 1355 1356 #define PIN_PC24A_SMC_A6 _L_(88) /**< SMC signal: A6 on PC24 mux A*/ 1357 #define MUX_PC24A_SMC_A6 _L_(0) /**< SMC signal line function value: A6 */ 1358 #define PIO_PC24A_SMC_A6 (_UL_(1) << 24) 1359 1360 #define PIN_PC25A_SMC_A7 _L_(89) /**< SMC signal: A7 on PC25 mux A*/ 1361 #define MUX_PC25A_SMC_A7 _L_(0) /**< SMC signal line function value: A7 */ 1362 #define PIO_PC25A_SMC_A7 (_UL_(1) << 25) 1363 1364 #define PIN_PC26A_SMC_A8 _L_(90) /**< SMC signal: A8 on PC26 mux A*/ 1365 #define MUX_PC26A_SMC_A8 _L_(0) /**< SMC signal line function value: A8 */ 1366 #define PIO_PC26A_SMC_A8 (_UL_(1) << 26) 1367 1368 #define PIN_PC27A_SMC_A9 _L_(91) /**< SMC signal: A9 on PC27 mux A*/ 1369 #define MUX_PC27A_SMC_A9 _L_(0) /**< SMC signal line function value: A9 */ 1370 #define PIO_PC27A_SMC_A9 (_UL_(1) << 27) 1371 1372 #define PIN_PC28A_SMC_A10 _L_(92) /**< SMC signal: A10 on PC28 mux A*/ 1373 #define MUX_PC28A_SMC_A10 _L_(0) /**< SMC signal line function value: A10 */ 1374 #define PIO_PC28A_SMC_A10 (_UL_(1) << 28) 1375 1376 #define PIN_PC29A_SMC_A11 _L_(93) /**< SMC signal: A11 on PC29 mux A*/ 1377 #define MUX_PC29A_SMC_A11 _L_(0) /**< SMC signal line function value: A11 */ 1378 #define PIO_PC29A_SMC_A11 (_UL_(1) << 29) 1379 1380 #define PIN_PC30A_SMC_A12 _L_(94) /**< SMC signal: A12 on PC30 mux A*/ 1381 #define MUX_PC30A_SMC_A12 _L_(0) /**< SMC signal line function value: A12 */ 1382 #define PIO_PC30A_SMC_A12 (_UL_(1) << 30) 1383 1384 #define PIN_PC31A_SMC_A13 _L_(95) /**< SMC signal: A13 on PC31 mux A*/ 1385 #define MUX_PC31A_SMC_A13 _L_(0) /**< SMC signal line function value: A13 */ 1386 #define PIO_PC31A_SMC_A13 (_UL_(1) << 31) 1387 1388 #define PIN_PA18C_SMC_A14 _L_(18) /**< SMC signal: A14 on PA18 mux C*/ 1389 #define MUX_PA18C_SMC_A14 _L_(2) /**< SMC signal line function value: A14 */ 1390 #define PIO_PA18C_SMC_A14 (_UL_(1) << 18) 1391 1392 #define PIN_PA19C_SMC_A15 _L_(19) /**< SMC signal: A15 on PA19 mux C*/ 1393 #define MUX_PA19C_SMC_A15 _L_(2) /**< SMC signal line function value: A15 */ 1394 #define PIO_PA19C_SMC_A15 (_UL_(1) << 19) 1395 1396 #define PIN_PA20C_SMC_A16 _L_(20) /**< SMC signal: A16 on PA20 mux C*/ 1397 #define MUX_PA20C_SMC_A16 _L_(2) /**< SMC signal line function value: A16 */ 1398 #define PIO_PA20C_SMC_A16 (_UL_(1) << 20) 1399 1400 #define PIN_PA20C_SMC_BA0 _L_(20) /**< SMC signal: BA0 on PA20 mux C*/ 1401 #define MUX_PA20C_SMC_BA0 _L_(2) /**< SMC signal line function value: BA0 */ 1402 #define PIO_PA20C_SMC_BA0 (_UL_(1) << 20) 1403 1404 #define PIN_PA0C_SMC_A17 _L_(0) /**< SMC signal: A17 on PA0 mux C*/ 1405 #define MUX_PA0C_SMC_A17 _L_(2) /**< SMC signal line function value: A17 */ 1406 #define PIO_PA0C_SMC_A17 (_UL_(1) << 0) 1407 1408 #define PIN_PA0C_SMC_BA1 _L_(0) /**< SMC signal: BA1 on PA0 mux C*/ 1409 #define MUX_PA0C_SMC_BA1 _L_(2) /**< SMC signal line function value: BA1 */ 1410 #define PIO_PA0C_SMC_BA1 (_UL_(1) << 0) 1411 1412 #define PIN_PA1C_SMC_A18 _L_(1) /**< SMC signal: A18 on PA1 mux C*/ 1413 #define MUX_PA1C_SMC_A18 _L_(2) /**< SMC signal line function value: A18 */ 1414 #define PIO_PA1C_SMC_A18 (_UL_(1) << 1) 1415 1416 #define PIN_PA23C_SMC_A19 _L_(23) /**< SMC signal: A19 on PA23 mux C*/ 1417 #define MUX_PA23C_SMC_A19 _L_(2) /**< SMC signal line function value: A19 */ 1418 #define PIO_PA23C_SMC_A19 (_UL_(1) << 23) 1419 1420 #define PIN_PA24C_SMC_A20 _L_(24) /**< SMC signal: A20 on PA24 mux C*/ 1421 #define MUX_PA24C_SMC_A20 _L_(2) /**< SMC signal line function value: A20 */ 1422 #define PIO_PA24C_SMC_A20 (_UL_(1) << 24) 1423 1424 #define PIN_PC16A_SMC_A21 _L_(80) /**< SMC signal: A21 on PC16 mux A*/ 1425 #define MUX_PC16A_SMC_A21 _L_(0) /**< SMC signal line function value: A21 */ 1426 #define PIO_PC16A_SMC_A21 (_UL_(1) << 16) 1427 1428 #define PIN_PC16A_SMC_NANDALE _L_(80) /**< SMC signal: NANDALE on PC16 mux A*/ 1429 #define MUX_PC16A_SMC_NANDALE _L_(0) /**< SMC signal line function value: NANDALE */ 1430 #define PIO_PC16A_SMC_NANDALE (_UL_(1) << 16) 1431 1432 #define PIN_PC17A_SMC_A22 _L_(81) /**< SMC signal: A22 on PC17 mux A*/ 1433 #define MUX_PC17A_SMC_A22 _L_(0) /**< SMC signal line function value: A22 */ 1434 #define PIO_PC17A_SMC_A22 (_UL_(1) << 17) 1435 1436 #define PIN_PC17A_SMC_NANDCLE _L_(81) /**< SMC signal: NANDCLE on PC17 mux A*/ 1437 #define MUX_PC17A_SMC_NANDCLE _L_(0) /**< SMC signal line function value: NANDCLE */ 1438 #define PIO_PC17A_SMC_NANDCLE (_UL_(1) << 17) 1439 1440 #define PIN_PA25C_SMC_A23 _L_(25) /**< SMC signal: A23 on PA25 mux C*/ 1441 #define MUX_PA25C_SMC_A23 _L_(2) /**< SMC signal line function value: A23 */ 1442 #define PIO_PA25C_SMC_A23 (_UL_(1) << 25) 1443 1444 #define PIN_PD17C_SMC_CAS _L_(113) /**< SMC signal: CAS on PD17 mux C*/ 1445 #define MUX_PD17C_SMC_CAS _L_(2) /**< SMC signal line function value: CAS */ 1446 #define PIO_PD17C_SMC_CAS (_UL_(1) << 17) 1447 1448 #define PIN_PC0A_SMC_D0 _L_(64) /**< SMC signal: D0 on PC0 mux A*/ 1449 #define MUX_PC0A_SMC_D0 _L_(0) /**< SMC signal line function value: D0 */ 1450 #define PIO_PC0A_SMC_D0 (_UL_(1) << 0) 1451 1452 #define PIN_PC1A_SMC_D1 _L_(65) /**< SMC signal: D1 on PC1 mux A*/ 1453 #define MUX_PC1A_SMC_D1 _L_(0) /**< SMC signal line function value: D1 */ 1454 #define PIO_PC1A_SMC_D1 (_UL_(1) << 1) 1455 1456 #define PIN_PC2A_SMC_D2 _L_(66) /**< SMC signal: D2 on PC2 mux A*/ 1457 #define MUX_PC2A_SMC_D2 _L_(0) /**< SMC signal line function value: D2 */ 1458 #define PIO_PC2A_SMC_D2 (_UL_(1) << 2) 1459 1460 #define PIN_PC3A_SMC_D3 _L_(67) /**< SMC signal: D3 on PC3 mux A*/ 1461 #define MUX_PC3A_SMC_D3 _L_(0) /**< SMC signal line function value: D3 */ 1462 #define PIO_PC3A_SMC_D3 (_UL_(1) << 3) 1463 1464 #define PIN_PC4A_SMC_D4 _L_(68) /**< SMC signal: D4 on PC4 mux A*/ 1465 #define MUX_PC4A_SMC_D4 _L_(0) /**< SMC signal line function value: D4 */ 1466 #define PIO_PC4A_SMC_D4 (_UL_(1) << 4) 1467 1468 #define PIN_PC5A_SMC_D5 _L_(69) /**< SMC signal: D5 on PC5 mux A*/ 1469 #define MUX_PC5A_SMC_D5 _L_(0) /**< SMC signal line function value: D5 */ 1470 #define PIO_PC5A_SMC_D5 (_UL_(1) << 5) 1471 1472 #define PIN_PC6A_SMC_D6 _L_(70) /**< SMC signal: D6 on PC6 mux A*/ 1473 #define MUX_PC6A_SMC_D6 _L_(0) /**< SMC signal line function value: D6 */ 1474 #define PIO_PC6A_SMC_D6 (_UL_(1) << 6) 1475 1476 #define PIN_PC7A_SMC_D7 _L_(71) /**< SMC signal: D7 on PC7 mux A*/ 1477 #define MUX_PC7A_SMC_D7 _L_(0) /**< SMC signal line function value: D7 */ 1478 #define PIO_PC7A_SMC_D7 (_UL_(1) << 7) 1479 1480 #define PIN_PE0A_SMC_D8 _L_(128) /**< SMC signal: D8 on PE0 mux A*/ 1481 #define MUX_PE0A_SMC_D8 _L_(0) /**< SMC signal line function value: D8 */ 1482 #define PIO_PE0A_SMC_D8 (_UL_(1) << 0) 1483 1484 #define PIN_PE1A_SMC_D9 _L_(129) /**< SMC signal: D9 on PE1 mux A*/ 1485 #define MUX_PE1A_SMC_D9 _L_(0) /**< SMC signal line function value: D9 */ 1486 #define PIO_PE1A_SMC_D9 (_UL_(1) << 1) 1487 1488 #define PIN_PE2A_SMC_D10 _L_(130) /**< SMC signal: D10 on PE2 mux A*/ 1489 #define MUX_PE2A_SMC_D10 _L_(0) /**< SMC signal line function value: D10 */ 1490 #define PIO_PE2A_SMC_D10 (_UL_(1) << 2) 1491 1492 #define PIN_PE3A_SMC_D11 _L_(131) /**< SMC signal: D11 on PE3 mux A*/ 1493 #define MUX_PE3A_SMC_D11 _L_(0) /**< SMC signal line function value: D11 */ 1494 #define PIO_PE3A_SMC_D11 (_UL_(1) << 3) 1495 1496 #define PIN_PE4A_SMC_D12 _L_(132) /**< SMC signal: D12 on PE4 mux A*/ 1497 #define MUX_PE4A_SMC_D12 _L_(0) /**< SMC signal line function value: D12 */ 1498 #define PIO_PE4A_SMC_D12 (_UL_(1) << 4) 1499 1500 #define PIN_PE5A_SMC_D13 _L_(133) /**< SMC signal: D13 on PE5 mux A*/ 1501 #define MUX_PE5A_SMC_D13 _L_(0) /**< SMC signal line function value: D13 */ 1502 #define PIO_PE5A_SMC_D13 (_UL_(1) << 5) 1503 1504 #define PIN_PA15A_SMC_D14 _L_(15) /**< SMC signal: D14 on PA15 mux A*/ 1505 #define MUX_PA15A_SMC_D14 _L_(0) /**< SMC signal line function value: D14 */ 1506 #define PIO_PA15A_SMC_D14 (_UL_(1) << 15) 1507 1508 #define PIN_PA16A_SMC_D15 _L_(16) /**< SMC signal: D15 on PA16 mux A*/ 1509 #define MUX_PA16A_SMC_D15 _L_(0) /**< SMC signal line function value: D15 */ 1510 #define PIO_PA16A_SMC_D15 (_UL_(1) << 16) 1511 1512 #define PIN_PC9A_SMC_NANDOE _L_(73) /**< SMC signal: NANDOE on PC9 mux A*/ 1513 #define MUX_PC9A_SMC_NANDOE _L_(0) /**< SMC signal line function value: NANDOE */ 1514 #define PIO_PC9A_SMC_NANDOE (_UL_(1) << 9) 1515 1516 #define PIN_PC10A_SMC_NANDWE _L_(74) /**< SMC signal: NANDWE on PC10 mux A*/ 1517 #define MUX_PC10A_SMC_NANDWE _L_(0) /**< SMC signal line function value: NANDWE */ 1518 #define PIO_PC10A_SMC_NANDWE (_UL_(1) << 10) 1519 1520 #define PIN_PC14A_SMC_NCS0 _L_(78) /**< SMC signal: NCS0 on PC14 mux A*/ 1521 #define MUX_PC14A_SMC_NCS0 _L_(0) /**< SMC signal line function value: NCS0 */ 1522 #define PIO_PC14A_SMC_NCS0 (_UL_(1) << 14) 1523 1524 #define PIN_PC15A_SMC_NCS1 _L_(79) /**< SMC signal: NCS1 on PC15 mux A*/ 1525 #define MUX_PC15A_SMC_NCS1 _L_(0) /**< SMC signal line function value: NCS1 */ 1526 #define PIO_PC15A_SMC_NCS1 (_UL_(1) << 15) 1527 1528 #define PIN_PC15A_SMC_SDCS _L_(79) /**< SMC signal: SDCS on PC15 mux A*/ 1529 #define MUX_PC15A_SMC_SDCS _L_(0) /**< SMC signal line function value: SDCS */ 1530 #define PIO_PC15A_SMC_SDCS (_UL_(1) << 15) 1531 1532 #define PIN_PD18A_SMC_NCS1 _L_(114) /**< SMC signal: NCS1 on PD18 mux A*/ 1533 #define MUX_PD18A_SMC_NCS1 _L_(0) /**< SMC signal line function value: NCS1 */ 1534 #define PIO_PD18A_SMC_NCS1 (_UL_(1) << 18) 1535 1536 #define PIN_PD18A_SMC_SDCS _L_(114) /**< SMC signal: SDCS on PD18 mux A*/ 1537 #define MUX_PD18A_SMC_SDCS _L_(0) /**< SMC signal line function value: SDCS */ 1538 #define PIO_PD18A_SMC_SDCS (_UL_(1) << 18) 1539 1540 #define PIN_PA22C_SMC_NCS2 _L_(22) /**< SMC signal: NCS2 on PA22 mux C*/ 1541 #define MUX_PA22C_SMC_NCS2 _L_(2) /**< SMC signal line function value: NCS2 */ 1542 #define PIO_PA22C_SMC_NCS2 (_UL_(1) << 22) 1543 1544 #define PIN_PC12A_SMC_NCS3 _L_(76) /**< SMC signal: NCS3 on PC12 mux A*/ 1545 #define MUX_PC12A_SMC_NCS3 _L_(0) /**< SMC signal line function value: NCS3 */ 1546 #define PIO_PC12A_SMC_NCS3 (_UL_(1) << 12) 1547 1548 #define PIN_PD19A_SMC_NCS3 _L_(115) /**< SMC signal: NCS3 on PD19 mux A*/ 1549 #define MUX_PD19A_SMC_NCS3 _L_(0) /**< SMC signal line function value: NCS3 */ 1550 #define PIO_PD19A_SMC_NCS3 (_UL_(1) << 19) 1551 1552 #define PIN_PC11A_SMC_NRD _L_(75) /**< SMC signal: NRD on PC11 mux A*/ 1553 #define MUX_PC11A_SMC_NRD _L_(0) /**< SMC signal line function value: NRD */ 1554 #define PIO_PC11A_SMC_NRD (_UL_(1) << 11) 1555 1556 #define PIN_PC13A_SMC_NWAIT _L_(77) /**< SMC signal: NWAIT on PC13 mux A*/ 1557 #define MUX_PC13A_SMC_NWAIT _L_(0) /**< SMC signal line function value: NWAIT */ 1558 #define PIO_PC13A_SMC_NWAIT (_UL_(1) << 13) 1559 1560 #define PIN_PC8A_SMC_NWR0 _L_(72) /**< SMC signal: NWR0 on PC8 mux A*/ 1561 #define MUX_PC8A_SMC_NWR0 _L_(0) /**< SMC signal line function value: NWR0 */ 1562 #define PIO_PC8A_SMC_NWR0 (_UL_(1) << 8) 1563 1564 #define PIN_PC8A_SMC_NWE _L_(72) /**< SMC signal: NWE on PC8 mux A*/ 1565 #define MUX_PC8A_SMC_NWE _L_(0) /**< SMC signal line function value: NWE */ 1566 #define PIO_PC8A_SMC_NWE (_UL_(1) << 8) 1567 1568 #define PIN_PD15C_SMC_NWR1 _L_(111) /**< SMC signal: NWR1 on PD15 mux C*/ 1569 #define MUX_PD15C_SMC_NWR1 _L_(2) /**< SMC signal line function value: NWR1 */ 1570 #define PIO_PD15C_SMC_NWR1 (_UL_(1) << 15) 1571 1572 #define PIN_PD15C_SMC_NBS1 _L_(111) /**< SMC signal: NBS1 on PD15 mux C*/ 1573 #define MUX_PD15C_SMC_NBS1 _L_(2) /**< SMC signal line function value: NBS1 */ 1574 #define PIO_PD15C_SMC_NBS1 (_UL_(1) << 15) 1575 1576 #define PIN_PD16C_SMC_RAS _L_(112) /**< SMC signal: RAS on PD16 mux C*/ 1577 #define MUX_PD16C_SMC_RAS _L_(2) /**< SMC signal line function value: RAS */ 1578 #define PIO_PD16C_SMC_RAS (_UL_(1) << 16) 1579 1580 #define PIN_PC13C_SMC_SDA10 _L_(77) /**< SMC signal: SDA10 on PC13 mux C*/ 1581 #define MUX_PC13C_SMC_SDA10 _L_(2) /**< SMC signal line function value: SDA10 */ 1582 #define PIO_PC13C_SMC_SDA10 (_UL_(1) << 13) 1583 1584 #define PIN_PD13C_SMC_SDA10 _L_(109) /**< SMC signal: SDA10 on PD13 mux C*/ 1585 #define MUX_PD13C_SMC_SDA10 _L_(2) /**< SMC signal line function value: SDA10 */ 1586 #define PIO_PD13C_SMC_SDA10 (_UL_(1) << 13) 1587 1588 #define PIN_PD23C_SMC_SDCK _L_(119) /**< SMC signal: SDCK on PD23 mux C*/ 1589 #define MUX_PD23C_SMC_SDCK _L_(2) /**< SMC signal line function value: SDCK */ 1590 #define PIO_PD23C_SMC_SDCK (_UL_(1) << 23) 1591 1592 #define PIN_PD14C_SMC_SDCKE _L_(110) /**< SMC signal: SDCKE on PD14 mux C*/ 1593 #define MUX_PD14C_SMC_SDCKE _L_(2) /**< SMC signal line function value: SDCKE */ 1594 #define PIO_PD14C_SMC_SDCKE (_UL_(1) << 14) 1595 1596 #define PIN_PD29C_SMC_SDWE _L_(125) /**< SMC signal: SDWE on PD29 mux C*/ 1597 #define MUX_PD29C_SMC_SDWE _L_(2) /**< SMC signal line function value: SDWE */ 1598 #define PIO_PD29C_SMC_SDWE (_UL_(1) << 29) 1599 1600 /* ========== PIO definition for SPI0 peripheral ========== */ 1601 #define PIN_PD20B_SPI0_MISO _L_(116) /**< SPI0 signal: MISO on PD20 mux B*/ 1602 #define MUX_PD20B_SPI0_MISO _L_(1) /**< SPI0 signal line function value: MISO */ 1603 #define PIO_PD20B_SPI0_MISO (_UL_(1) << 20) 1604 1605 #define PIN_PD21B_SPI0_MOSI _L_(117) /**< SPI0 signal: MOSI on PD21 mux B*/ 1606 #define MUX_PD21B_SPI0_MOSI _L_(1) /**< SPI0 signal line function value: MOSI */ 1607 #define PIO_PD21B_SPI0_MOSI (_UL_(1) << 21) 1608 1609 #define PIN_PB2D_SPI0_NPCS0 _L_(34) /**< SPI0 signal: NPCS0 on PB2 mux D*/ 1610 #define MUX_PB2D_SPI0_NPCS0 _L_(3) /**< SPI0 signal line function value: NPCS0 */ 1611 #define PIO_PB2D_SPI0_NPCS0 (_UL_(1) << 2) 1612 1613 #define PIN_PA31A_SPI0_NPCS1 _L_(31) /**< SPI0 signal: NPCS1 on PA31 mux A*/ 1614 #define MUX_PA31A_SPI0_NPCS1 _L_(0) /**< SPI0 signal line function value: NPCS1 */ 1615 #define PIO_PA31A_SPI0_NPCS1 (_UL_(1) << 31) 1616 1617 #define PIN_PD25B_SPI0_NPCS1 _L_(121) /**< SPI0 signal: NPCS1 on PD25 mux B*/ 1618 #define MUX_PD25B_SPI0_NPCS1 _L_(1) /**< SPI0 signal line function value: NPCS1 */ 1619 #define PIO_PD25B_SPI0_NPCS1 (_UL_(1) << 25) 1620 1621 #define PIN_PD12C_SPI0_NPCS2 _L_(108) /**< SPI0 signal: NPCS2 on PD12 mux C*/ 1622 #define MUX_PD12C_SPI0_NPCS2 _L_(2) /**< SPI0 signal line function value: NPCS2 */ 1623 #define PIO_PD12C_SPI0_NPCS2 (_UL_(1) << 12) 1624 1625 #define PIN_PD27B_SPI0_NPCS3 _L_(123) /**< SPI0 signal: NPCS3 on PD27 mux B*/ 1626 #define MUX_PD27B_SPI0_NPCS3 _L_(1) /**< SPI0 signal line function value: NPCS3 */ 1627 #define PIO_PD27B_SPI0_NPCS3 (_UL_(1) << 27) 1628 1629 #define PIN_PD22B_SPI0_SPCK _L_(118) /**< SPI0 signal: SPCK on PD22 mux B*/ 1630 #define MUX_PD22B_SPI0_SPCK _L_(1) /**< SPI0 signal line function value: SPCK */ 1631 #define PIO_PD22B_SPI0_SPCK (_UL_(1) << 22) 1632 1633 /* ========== PIO definition for SPI1 peripheral ========== */ 1634 #define PIN_PC26C_SPI1_MISO _L_(90) /**< SPI1 signal: MISO on PC26 mux C*/ 1635 #define MUX_PC26C_SPI1_MISO _L_(2) /**< SPI1 signal line function value: MISO */ 1636 #define PIO_PC26C_SPI1_MISO (_UL_(1) << 26) 1637 1638 #define PIN_PC27C_SPI1_MOSI _L_(91) /**< SPI1 signal: MOSI on PC27 mux C*/ 1639 #define MUX_PC27C_SPI1_MOSI _L_(2) /**< SPI1 signal line function value: MOSI */ 1640 #define PIO_PC27C_SPI1_MOSI (_UL_(1) << 27) 1641 1642 #define PIN_PC25C_SPI1_NPCS0 _L_(89) /**< SPI1 signal: NPCS0 on PC25 mux C*/ 1643 #define MUX_PC25C_SPI1_NPCS0 _L_(2) /**< SPI1 signal line function value: NPCS0 */ 1644 #define PIO_PC25C_SPI1_NPCS0 (_UL_(1) << 25) 1645 1646 #define PIN_PC28C_SPI1_NPCS1 _L_(92) /**< SPI1 signal: NPCS1 on PC28 mux C*/ 1647 #define MUX_PC28C_SPI1_NPCS1 _L_(2) /**< SPI1 signal line function value: NPCS1 */ 1648 #define PIO_PC28C_SPI1_NPCS1 (_UL_(1) << 28) 1649 1650 #define PIN_PD0C_SPI1_NPCS1 _L_(96) /**< SPI1 signal: NPCS1 on PD0 mux C*/ 1651 #define MUX_PD0C_SPI1_NPCS1 _L_(2) /**< SPI1 signal line function value: NPCS1 */ 1652 #define PIO_PD0C_SPI1_NPCS1 (_UL_(1) << 0) 1653 1654 #define PIN_PC29C_SPI1_NPCS2 _L_(93) /**< SPI1 signal: NPCS2 on PC29 mux C*/ 1655 #define MUX_PC29C_SPI1_NPCS2 _L_(2) /**< SPI1 signal line function value: NPCS2 */ 1656 #define PIO_PC29C_SPI1_NPCS2 (_UL_(1) << 29) 1657 1658 #define PIN_PD1C_SPI1_NPCS2 _L_(97) /**< SPI1 signal: NPCS2 on PD1 mux C*/ 1659 #define MUX_PD1C_SPI1_NPCS2 _L_(2) /**< SPI1 signal line function value: NPCS2 */ 1660 #define PIO_PD1C_SPI1_NPCS2 (_UL_(1) << 1) 1661 1662 #define PIN_PC30C_SPI1_NPCS3 _L_(94) /**< SPI1 signal: NPCS3 on PC30 mux C*/ 1663 #define MUX_PC30C_SPI1_NPCS3 _L_(2) /**< SPI1 signal line function value: NPCS3 */ 1664 #define PIO_PC30C_SPI1_NPCS3 (_UL_(1) << 30) 1665 1666 #define PIN_PD2C_SPI1_NPCS3 _L_(98) /**< SPI1 signal: NPCS3 on PD2 mux C*/ 1667 #define MUX_PD2C_SPI1_NPCS3 _L_(2) /**< SPI1 signal line function value: NPCS3 */ 1668 #define PIO_PD2C_SPI1_NPCS3 (_UL_(1) << 2) 1669 1670 #define PIN_PC24C_SPI1_SPCK _L_(88) /**< SPI1 signal: SPCK on PC24 mux C*/ 1671 #define MUX_PC24C_SPI1_SPCK _L_(2) /**< SPI1 signal line function value: SPCK */ 1672 #define PIO_PC24C_SPI1_SPCK (_UL_(1) << 24) 1673 1674 /* ========== PIO definition for SSC peripheral ========== */ 1675 #define PIN_PA10C_SSC_RD _L_(10) /**< SSC signal: RD on PA10 mux C*/ 1676 #define MUX_PA10C_SSC_RD _L_(2) /**< SSC signal line function value: RD */ 1677 #define PIO_PA10C_SSC_RD (_UL_(1) << 10) 1678 1679 #define PIN_PD24B_SSC_RF _L_(120) /**< SSC signal: RF on PD24 mux B*/ 1680 #define MUX_PD24B_SSC_RF _L_(1) /**< SSC signal line function value: RF */ 1681 #define PIO_PD24B_SSC_RF (_UL_(1) << 24) 1682 1683 #define PIN_PA22A_SSC_RK _L_(22) /**< SSC signal: RK on PA22 mux A*/ 1684 #define MUX_PA22A_SSC_RK _L_(0) /**< SSC signal line function value: RK */ 1685 #define PIO_PA22A_SSC_RK (_UL_(1) << 22) 1686 1687 #define PIN_PB5D_SSC_TD _L_(37) /**< SSC signal: TD on PB5 mux D*/ 1688 #define MUX_PB5D_SSC_TD _L_(3) /**< SSC signal line function value: TD */ 1689 #define PIO_PB5D_SSC_TD (_UL_(1) << 5) 1690 1691 #define PIN_PD10C_SSC_TD _L_(106) /**< SSC signal: TD on PD10 mux C*/ 1692 #define MUX_PD10C_SSC_TD _L_(2) /**< SSC signal line function value: TD */ 1693 #define PIO_PD10C_SSC_TD (_UL_(1) << 10) 1694 1695 #define PIN_PD26B_SSC_TD _L_(122) /**< SSC signal: TD on PD26 mux B*/ 1696 #define MUX_PD26B_SSC_TD _L_(1) /**< SSC signal line function value: TD */ 1697 #define PIO_PD26B_SSC_TD (_UL_(1) << 26) 1698 1699 #define PIN_PB0D_SSC_TF _L_(32) /**< SSC signal: TF on PB0 mux D*/ 1700 #define MUX_PB0D_SSC_TF _L_(3) /**< SSC signal line function value: TF */ 1701 #define PIO_PB0D_SSC_TF (_UL_(1) << 0) 1702 1703 #define PIN_PB1D_SSC_TK _L_(33) /**< SSC signal: TK on PB1 mux D*/ 1704 #define MUX_PB1D_SSC_TK _L_(3) /**< SSC signal line function value: TK */ 1705 #define PIO_PB1D_SSC_TK (_UL_(1) << 1) 1706 1707 /* ========== PIO definition for TC0 peripheral ========== */ 1708 #define PIN_PA4B_TC0_TCLK0 _L_(4) /**< TC0 signal: TCLK0 on PA4 mux B*/ 1709 #define MUX_PA4B_TC0_TCLK0 _L_(1) /**< TC0 signal line function value: TCLK0 */ 1710 #define PIO_PA4B_TC0_TCLK0 (_UL_(1) << 4) 1711 1712 #define PIN_PA28B_TC0_TCLK1 _L_(28) /**< TC0 signal: TCLK1 on PA28 mux B*/ 1713 #define MUX_PA28B_TC0_TCLK1 _L_(1) /**< TC0 signal line function value: TCLK1 */ 1714 #define PIO_PA28B_TC0_TCLK1 (_UL_(1) << 28) 1715 1716 #define PIN_PA29B_TC0_TCLK2 _L_(29) /**< TC0 signal: TCLK2 on PA29 mux B*/ 1717 #define MUX_PA29B_TC0_TCLK2 _L_(1) /**< TC0 signal line function value: TCLK2 */ 1718 #define PIO_PA29B_TC0_TCLK2 (_UL_(1) << 29) 1719 1720 #define PIN_PA0B_TC0_TIOA0 _L_(0) /**< TC0 signal: TIOA0 on PA0 mux B*/ 1721 #define MUX_PA0B_TC0_TIOA0 _L_(1) /**< TC0 signal line function value: TIOA0 */ 1722 #define PIO_PA0B_TC0_TIOA0 (_UL_(1) << 0) 1723 1724 #define PIN_PA15B_TC0_TIOA1 _L_(15) /**< TC0 signal: TIOA1 on PA15 mux B*/ 1725 #define MUX_PA15B_TC0_TIOA1 _L_(1) /**< TC0 signal line function value: TIOA1 */ 1726 #define PIO_PA15B_TC0_TIOA1 (_UL_(1) << 15) 1727 1728 #define PIN_PA26B_TC0_TIOA2 _L_(26) /**< TC0 signal: TIOA2 on PA26 mux B*/ 1729 #define MUX_PA26B_TC0_TIOA2 _L_(1) /**< TC0 signal line function value: TIOA2 */ 1730 #define PIO_PA26B_TC0_TIOA2 (_UL_(1) << 26) 1731 1732 #define PIN_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal: TIOB0 on PA1 mux B*/ 1733 #define MUX_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal line function value: TIOB0 */ 1734 #define PIO_PA1B_TC0_TIOB0 (_UL_(1) << 1) 1735 1736 #define PIN_PA16B_TC0_TIOB1 _L_(16) /**< TC0 signal: TIOB1 on PA16 mux B*/ 1737 #define MUX_PA16B_TC0_TIOB1 _L_(1) /**< TC0 signal line function value: TIOB1 */ 1738 #define PIO_PA16B_TC0_TIOB1 (_UL_(1) << 16) 1739 1740 #define PIN_PA27B_TC0_TIOB2 _L_(27) /**< TC0 signal: TIOB2 on PA27 mux B*/ 1741 #define MUX_PA27B_TC0_TIOB2 _L_(1) /**< TC0 signal line function value: TIOB2 */ 1742 #define PIO_PA27B_TC0_TIOB2 (_UL_(1) << 27) 1743 1744 /* ========== PIO definition for TC1 peripheral ========== */ 1745 #define PIN_PC25B_TC1_TCLK3 _L_(89) /**< TC1 signal: TCLK3 on PC25 mux B*/ 1746 #define MUX_PC25B_TC1_TCLK3 _L_(1) /**< TC1 signal line function value: TCLK3 */ 1747 #define PIO_PC25B_TC1_TCLK3 (_UL_(1) << 25) 1748 1749 #define PIN_PC28B_TC1_TCLK4 _L_(92) /**< TC1 signal: TCLK4 on PC28 mux B*/ 1750 #define MUX_PC28B_TC1_TCLK4 _L_(1) /**< TC1 signal line function value: TCLK4 */ 1751 #define PIO_PC28B_TC1_TCLK4 (_UL_(1) << 28) 1752 1753 #define PIN_PC31B_TC1_TCLK5 _L_(95) /**< TC1 signal: TCLK5 on PC31 mux B*/ 1754 #define MUX_PC31B_TC1_TCLK5 _L_(1) /**< TC1 signal line function value: TCLK5 */ 1755 #define PIO_PC31B_TC1_TCLK5 (_UL_(1) << 31) 1756 1757 #define PIN_PC23B_TC1_TIOA3 _L_(87) /**< TC1 signal: TIOA3 on PC23 mux B*/ 1758 #define MUX_PC23B_TC1_TIOA3 _L_(1) /**< TC1 signal line function value: TIOA3 */ 1759 #define PIO_PC23B_TC1_TIOA3 (_UL_(1) << 23) 1760 1761 #define PIN_PC26B_TC1_TIOA4 _L_(90) /**< TC1 signal: TIOA4 on PC26 mux B*/ 1762 #define MUX_PC26B_TC1_TIOA4 _L_(1) /**< TC1 signal line function value: TIOA4 */ 1763 #define PIO_PC26B_TC1_TIOA4 (_UL_(1) << 26) 1764 1765 #define PIN_PC29B_TC1_TIOA5 _L_(93) /**< TC1 signal: TIOA5 on PC29 mux B*/ 1766 #define MUX_PC29B_TC1_TIOA5 _L_(1) /**< TC1 signal line function value: TIOA5 */ 1767 #define PIO_PC29B_TC1_TIOA5 (_UL_(1) << 29) 1768 1769 #define PIN_PC24B_TC1_TIOB3 _L_(88) /**< TC1 signal: TIOB3 on PC24 mux B*/ 1770 #define MUX_PC24B_TC1_TIOB3 _L_(1) /**< TC1 signal line function value: TIOB3 */ 1771 #define PIO_PC24B_TC1_TIOB3 (_UL_(1) << 24) 1772 1773 #define PIN_PC27B_TC1_TIOB4 _L_(91) /**< TC1 signal: TIOB4 on PC27 mux B*/ 1774 #define MUX_PC27B_TC1_TIOB4 _L_(1) /**< TC1 signal line function value: TIOB4 */ 1775 #define PIO_PC27B_TC1_TIOB4 (_UL_(1) << 27) 1776 1777 #define PIN_PC30B_TC1_TIOB5 _L_(94) /**< TC1 signal: TIOB5 on PC30 mux B*/ 1778 #define MUX_PC30B_TC1_TIOB5 _L_(1) /**< TC1 signal line function value: TIOB5 */ 1779 #define PIO_PC30B_TC1_TIOB5 (_UL_(1) << 30) 1780 1781 /* ========== PIO definition for TC2 peripheral ========== */ 1782 #define PIN_PC7B_TC2_TCLK6 _L_(71) /**< TC2 signal: TCLK6 on PC7 mux B*/ 1783 #define MUX_PC7B_TC2_TCLK6 _L_(1) /**< TC2 signal line function value: TCLK6 */ 1784 #define PIO_PC7B_TC2_TCLK6 (_UL_(1) << 7) 1785 1786 #define PIN_PC10B_TC2_TCLK7 _L_(74) /**< TC2 signal: TCLK7 on PC10 mux B*/ 1787 #define MUX_PC10B_TC2_TCLK7 _L_(1) /**< TC2 signal line function value: TCLK7 */ 1788 #define PIO_PC10B_TC2_TCLK7 (_UL_(1) << 10) 1789 1790 #define PIN_PC14B_TC2_TCLK8 _L_(78) /**< TC2 signal: TCLK8 on PC14 mux B*/ 1791 #define MUX_PC14B_TC2_TCLK8 _L_(1) /**< TC2 signal line function value: TCLK8 */ 1792 #define PIO_PC14B_TC2_TCLK8 (_UL_(1) << 14) 1793 1794 #define PIN_PC5B_TC2_TIOA6 _L_(69) /**< TC2 signal: TIOA6 on PC5 mux B*/ 1795 #define MUX_PC5B_TC2_TIOA6 _L_(1) /**< TC2 signal line function value: TIOA6 */ 1796 #define PIO_PC5B_TC2_TIOA6 (_UL_(1) << 5) 1797 1798 #define PIN_PC8B_TC2_TIOA7 _L_(72) /**< TC2 signal: TIOA7 on PC8 mux B*/ 1799 #define MUX_PC8B_TC2_TIOA7 _L_(1) /**< TC2 signal line function value: TIOA7 */ 1800 #define PIO_PC8B_TC2_TIOA7 (_UL_(1) << 8) 1801 1802 #define PIN_PC11B_TC2_TIOA8 _L_(75) /**< TC2 signal: TIOA8 on PC11 mux B*/ 1803 #define MUX_PC11B_TC2_TIOA8 _L_(1) /**< TC2 signal line function value: TIOA8 */ 1804 #define PIO_PC11B_TC2_TIOA8 (_UL_(1) << 11) 1805 1806 #define PIN_PC6B_TC2_TIOB6 _L_(70) /**< TC2 signal: TIOB6 on PC6 mux B*/ 1807 #define MUX_PC6B_TC2_TIOB6 _L_(1) /**< TC2 signal line function value: TIOB6 */ 1808 #define PIO_PC6B_TC2_TIOB6 (_UL_(1) << 6) 1809 1810 #define PIN_PC9B_TC2_TIOB7 _L_(73) /**< TC2 signal: TIOB7 on PC9 mux B*/ 1811 #define MUX_PC9B_TC2_TIOB7 _L_(1) /**< TC2 signal line function value: TIOB7 */ 1812 #define PIO_PC9B_TC2_TIOB7 (_UL_(1) << 9) 1813 1814 #define PIN_PC12B_TC2_TIOB8 _L_(76) /**< TC2 signal: TIOB8 on PC12 mux B*/ 1815 #define MUX_PC12B_TC2_TIOB8 _L_(1) /**< TC2 signal line function value: TIOB8 */ 1816 #define PIO_PC12B_TC2_TIOB8 (_UL_(1) << 12) 1817 1818 /* ========== PIO definition for TC3 peripheral ========== */ 1819 #define PIN_PE2B_TC3_TCLK9 _L_(130) /**< TC3 signal: TCLK9 on PE2 mux B*/ 1820 #define MUX_PE2B_TC3_TCLK9 _L_(1) /**< TC3 signal line function value: TCLK9 */ 1821 #define PIO_PE2B_TC3_TCLK9 (_UL_(1) << 2) 1822 1823 #define PIN_PE5B_TC3_TCLK10 _L_(133) /**< TC3 signal: TCLK10 on PE5 mux B*/ 1824 #define MUX_PE5B_TC3_TCLK10 _L_(1) /**< TC3 signal line function value: TCLK10 */ 1825 #define PIO_PE5B_TC3_TCLK10 (_UL_(1) << 5) 1826 1827 #define PIN_PD24C_TC3_TCLK11 _L_(120) /**< TC3 signal: TCLK11 on PD24 mux C*/ 1828 #define MUX_PD24C_TC3_TCLK11 _L_(2) /**< TC3 signal line function value: TCLK11 */ 1829 #define PIO_PD24C_TC3_TCLK11 (_UL_(1) << 24) 1830 1831 #define PIN_PE0B_TC3_TIOA9 _L_(128) /**< TC3 signal: TIOA9 on PE0 mux B*/ 1832 #define MUX_PE0B_TC3_TIOA9 _L_(1) /**< TC3 signal line function value: TIOA9 */ 1833 #define PIO_PE0B_TC3_TIOA9 (_UL_(1) << 0) 1834 1835 #define PIN_PE3B_TC3_TIOA10 _L_(131) /**< TC3 signal: TIOA10 on PE3 mux B*/ 1836 #define MUX_PE3B_TC3_TIOA10 _L_(1) /**< TC3 signal line function value: TIOA10 */ 1837 #define PIO_PE3B_TC3_TIOA10 (_UL_(1) << 3) 1838 1839 #define PIN_PD21C_TC3_TIOA11 _L_(117) /**< TC3 signal: TIOA11 on PD21 mux C*/ 1840 #define MUX_PD21C_TC3_TIOA11 _L_(2) /**< TC3 signal line function value: TIOA11 */ 1841 #define PIO_PD21C_TC3_TIOA11 (_UL_(1) << 21) 1842 1843 #define PIN_PE1B_TC3_TIOB9 _L_(129) /**< TC3 signal: TIOB9 on PE1 mux B*/ 1844 #define MUX_PE1B_TC3_TIOB9 _L_(1) /**< TC3 signal line function value: TIOB9 */ 1845 #define PIO_PE1B_TC3_TIOB9 (_UL_(1) << 1) 1846 1847 #define PIN_PE4B_TC3_TIOB10 _L_(132) /**< TC3 signal: TIOB10 on PE4 mux B*/ 1848 #define MUX_PE4B_TC3_TIOB10 _L_(1) /**< TC3 signal line function value: TIOB10 */ 1849 #define PIO_PE4B_TC3_TIOB10 (_UL_(1) << 4) 1850 1851 #define PIN_PD22C_TC3_TIOB11 _L_(118) /**< TC3 signal: TIOB11 on PD22 mux C*/ 1852 #define MUX_PD22C_TC3_TIOB11 _L_(2) /**< TC3 signal line function value: TIOB11 */ 1853 #define PIO_PD22C_TC3_TIOB11 (_UL_(1) << 22) 1854 1855 /* ========== PIO definition for TWIHS0 peripheral ========== */ 1856 #define PIN_PA4A_TWIHS0_TWCK0 _L_(4) /**< TWIHS0 signal: TWCK0 on PA4 mux A*/ 1857 #define MUX_PA4A_TWIHS0_TWCK0 _L_(0) /**< TWIHS0 signal line function value: TWCK0 */ 1858 #define PIO_PA4A_TWIHS0_TWCK0 (_UL_(1) << 4) 1859 1860 #define PIN_PA3A_TWIHS0_TWD0 _L_(3) /**< TWIHS0 signal: TWD0 on PA3 mux A*/ 1861 #define MUX_PA3A_TWIHS0_TWD0 _L_(0) /**< TWIHS0 signal line function value: TWD0 */ 1862 #define PIO_PA3A_TWIHS0_TWD0 (_UL_(1) << 3) 1863 1864 /* ========== PIO definition for TWIHS1 peripheral ========== */ 1865 #define PIN_PB5A_TWIHS1_TWCK1 _L_(37) /**< TWIHS1 signal: TWCK1 on PB5 mux A*/ 1866 #define MUX_PB5A_TWIHS1_TWCK1 _L_(0) /**< TWIHS1 signal line function value: TWCK1 */ 1867 #define PIO_PB5A_TWIHS1_TWCK1 (_UL_(1) << 5) 1868 1869 #define PIN_PB4A_TWIHS1_TWD1 _L_(36) /**< TWIHS1 signal: TWD1 on PB4 mux A*/ 1870 #define MUX_PB4A_TWIHS1_TWD1 _L_(0) /**< TWIHS1 signal line function value: TWD1 */ 1871 #define PIO_PB4A_TWIHS1_TWD1 (_UL_(1) << 4) 1872 1873 /* ========== PIO definition for TWIHS2 peripheral ========== */ 1874 #define PIN_PD28C_TWIHS2_TWCK2 _L_(124) /**< TWIHS2 signal: TWCK2 on PD28 mux C*/ 1875 #define MUX_PD28C_TWIHS2_TWCK2 _L_(2) /**< TWIHS2 signal line function value: TWCK2 */ 1876 #define PIO_PD28C_TWIHS2_TWCK2 (_UL_(1) << 28) 1877 1878 #define PIN_PD27C_TWIHS2_TWD2 _L_(123) /**< TWIHS2 signal: TWD2 on PD27 mux C*/ 1879 #define MUX_PD27C_TWIHS2_TWD2 _L_(2) /**< TWIHS2 signal line function value: TWD2 */ 1880 #define PIO_PD27C_TWIHS2_TWD2 (_UL_(1) << 27) 1881 1882 /* ========== PIO definition for UART0 peripheral ========== */ 1883 #define PIN_PA9A_UART0_URXD0 _L_(9) /**< UART0 signal: URXD0 on PA9 mux A*/ 1884 #define MUX_PA9A_UART0_URXD0 _L_(0) /**< UART0 signal line function value: URXD0 */ 1885 #define PIO_PA9A_UART0_URXD0 (_UL_(1) << 9) 1886 1887 #define PIN_PA10A_UART0_UTXD0 _L_(10) /**< UART0 signal: UTXD0 on PA10 mux A*/ 1888 #define MUX_PA10A_UART0_UTXD0 _L_(0) /**< UART0 signal line function value: UTXD0 */ 1889 #define PIO_PA10A_UART0_UTXD0 (_UL_(1) << 10) 1890 1891 /* ========== PIO definition for UART1 peripheral ========== */ 1892 #define PIN_PA5C_UART1_URXD1 _L_(5) /**< UART1 signal: URXD1 on PA5 mux C*/ 1893 #define MUX_PA5C_UART1_URXD1 _L_(2) /**< UART1 signal line function value: URXD1 */ 1894 #define PIO_PA5C_UART1_URXD1 (_UL_(1) << 5) 1895 1896 #define PIN_PA4C_UART1_UTXD1 _L_(4) /**< UART1 signal: UTXD1 on PA4 mux C*/ 1897 #define MUX_PA4C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UTXD1 */ 1898 #define PIO_PA4C_UART1_UTXD1 (_UL_(1) << 4) 1899 1900 #define PIN_PA6C_UART1_UTXD1 _L_(6) /**< UART1 signal: UTXD1 on PA6 mux C*/ 1901 #define MUX_PA6C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UTXD1 */ 1902 #define PIO_PA6C_UART1_UTXD1 (_UL_(1) << 6) 1903 1904 #define PIN_PD26D_UART1_UTXD1 _L_(122) /**< UART1 signal: UTXD1 on PD26 mux D*/ 1905 #define MUX_PD26D_UART1_UTXD1 _L_(3) /**< UART1 signal line function value: UTXD1 */ 1906 #define PIO_PD26D_UART1_UTXD1 (_UL_(1) << 26) 1907 1908 /* ========== PIO definition for UART2 peripheral ========== */ 1909 #define PIN_PD25C_UART2_URXD2 _L_(121) /**< UART2 signal: URXD2 on PD25 mux C*/ 1910 #define MUX_PD25C_UART2_URXD2 _L_(2) /**< UART2 signal line function value: URXD2 */ 1911 #define PIO_PD25C_UART2_URXD2 (_UL_(1) << 25) 1912 1913 #define PIN_PD26C_UART2_UTXD2 _L_(122) /**< UART2 signal: UTXD2 on PD26 mux C*/ 1914 #define MUX_PD26C_UART2_UTXD2 _L_(2) /**< UART2 signal line function value: UTXD2 */ 1915 #define PIO_PD26C_UART2_UTXD2 (_UL_(1) << 26) 1916 1917 /* ========== PIO definition for UART3 peripheral ========== */ 1918 #define PIN_PD28A_UART3_URXD3 _L_(124) /**< UART3 signal: URXD3 on PD28 mux A*/ 1919 #define MUX_PD28A_UART3_URXD3 _L_(0) /**< UART3 signal line function value: URXD3 */ 1920 #define PIO_PD28A_UART3_URXD3 (_UL_(1) << 28) 1921 1922 #define PIN_PD30A_UART3_UTXD3 _L_(126) /**< UART3 signal: UTXD3 on PD30 mux A*/ 1923 #define MUX_PD30A_UART3_UTXD3 _L_(0) /**< UART3 signal line function value: UTXD3 */ 1924 #define PIO_PD30A_UART3_UTXD3 (_UL_(1) << 30) 1925 1926 #define PIN_PD31B_UART3_UTXD3 _L_(127) /**< UART3 signal: UTXD3 on PD31 mux B*/ 1927 #define MUX_PD31B_UART3_UTXD3 _L_(1) /**< UART3 signal line function value: UTXD3 */ 1928 #define PIO_PD31B_UART3_UTXD3 (_UL_(1) << 31) 1929 1930 /* ========== PIO definition for UART4 peripheral ========== */ 1931 #define PIN_PD18C_UART4_URXD4 _L_(114) /**< UART4 signal: URXD4 on PD18 mux C*/ 1932 #define MUX_PD18C_UART4_URXD4 _L_(2) /**< UART4 signal line function value: URXD4 */ 1933 #define PIO_PD18C_UART4_URXD4 (_UL_(1) << 18) 1934 1935 #define PIN_PD3C_UART4_UTXD4 _L_(99) /**< UART4 signal: UTXD4 on PD3 mux C*/ 1936 #define MUX_PD3C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UTXD4 */ 1937 #define PIO_PD3C_UART4_UTXD4 (_UL_(1) << 3) 1938 1939 #define PIN_PD19C_UART4_UTXD4 _L_(115) /**< UART4 signal: UTXD4 on PD19 mux C*/ 1940 #define MUX_PD19C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UTXD4 */ 1941 #define PIO_PD19C_UART4_UTXD4 (_UL_(1) << 19) 1942 1943 /* ========== PIO definition for USART0 peripheral ========== */ 1944 #define PIN_PB2C_USART0_CTS0 _L_(34) /**< USART0 signal: CTS0 on PB2 mux C*/ 1945 #define MUX_PB2C_USART0_CTS0 _L_(2) /**< USART0 signal line function value: CTS0 */ 1946 #define PIO_PB2C_USART0_CTS0 (_UL_(1) << 2) 1947 1948 #define PIN_PD0D_USART0_DCD0 _L_(96) /**< USART0 signal: DCD0 on PD0 mux D*/ 1949 #define MUX_PD0D_USART0_DCD0 _L_(3) /**< USART0 signal line function value: DCD0 */ 1950 #define PIO_PD0D_USART0_DCD0 (_UL_(1) << 0) 1951 1952 #define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: DSR0 on PD2 mux D*/ 1953 #define MUX_PD2D_USART0_DSR0 _L_(3) /**< USART0 signal line function value: DSR0 */ 1954 #define PIO_PD2D_USART0_DSR0 (_UL_(1) << 2) 1955 1956 #define PIN_PD1D_USART0_DTR0 _L_(97) /**< USART0 signal: DTR0 on PD1 mux D*/ 1957 #define MUX_PD1D_USART0_DTR0 _L_(3) /**< USART0 signal line function value: DTR0 */ 1958 #define PIO_PD1D_USART0_DTR0 (_UL_(1) << 1) 1959 1960 #define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux D*/ 1961 #define MUX_PD3D_USART0_RI0 _L_(3) /**< USART0 signal line function value: RI0 */ 1962 #define PIO_PD3D_USART0_RI0 (_UL_(1) << 3) 1963 1964 #define PIN_PB3C_USART0_RTS0 _L_(35) /**< USART0 signal: RTS0 on PB3 mux C*/ 1965 #define MUX_PB3C_USART0_RTS0 _L_(2) /**< USART0 signal line function value: RTS0 */ 1966 #define PIO_PB3C_USART0_RTS0 (_UL_(1) << 3) 1967 1968 #define PIN_PB0C_USART0_RXD0 _L_(32) /**< USART0 signal: RXD0 on PB0 mux C*/ 1969 #define MUX_PB0C_USART0_RXD0 _L_(2) /**< USART0 signal line function value: RXD0 */ 1970 #define PIO_PB0C_USART0_RXD0 (_UL_(1) << 0) 1971 1972 #define PIN_PB13C_USART0_SCK0 _L_(45) /**< USART0 signal: SCK0 on PB13 mux C*/ 1973 #define MUX_PB13C_USART0_SCK0 _L_(2) /**< USART0 signal line function value: SCK0 */ 1974 #define PIO_PB13C_USART0_SCK0 (_UL_(1) << 13) 1975 1976 #define PIN_PB1C_USART0_TXD0 _L_(33) /**< USART0 signal: TXD0 on PB1 mux C*/ 1977 #define MUX_PB1C_USART0_TXD0 _L_(2) /**< USART0 signal line function value: TXD0 */ 1978 #define PIO_PB1C_USART0_TXD0 (_UL_(1) << 1) 1979 1980 /* ========== PIO definition for USART1 peripheral ========== */ 1981 #define PIN_PA25A_USART1_CTS1 _L_(25) /**< USART1 signal: CTS1 on PA25 mux A*/ 1982 #define MUX_PA25A_USART1_CTS1 _L_(0) /**< USART1 signal line function value: CTS1 */ 1983 #define PIO_PA25A_USART1_CTS1 (_UL_(1) << 25) 1984 1985 #define PIN_PA26A_USART1_DCD1 _L_(26) /**< USART1 signal: DCD1 on PA26 mux A*/ 1986 #define MUX_PA26A_USART1_DCD1 _L_(0) /**< USART1 signal line function value: DCD1 */ 1987 #define PIO_PA26A_USART1_DCD1 (_UL_(1) << 26) 1988 1989 #define PIN_PA28A_USART1_DSR1 _L_(28) /**< USART1 signal: DSR1 on PA28 mux A*/ 1990 #define MUX_PA28A_USART1_DSR1 _L_(0) /**< USART1 signal line function value: DSR1 */ 1991 #define PIO_PA28A_USART1_DSR1 (_UL_(1) << 28) 1992 1993 #define PIN_PA27A_USART1_DTR1 _L_(27) /**< USART1 signal: DTR1 on PA27 mux A*/ 1994 #define MUX_PA27A_USART1_DTR1 _L_(0) /**< USART1 signal line function value: DTR1 */ 1995 #define PIO_PA27A_USART1_DTR1 (_UL_(1) << 27) 1996 1997 #define PIN_PA3B_USART1_LONCOL1 _L_(3) /**< USART1 signal: LONCOL1 on PA3 mux B*/ 1998 #define MUX_PA3B_USART1_LONCOL1 _L_(1) /**< USART1 signal line function value: LONCOL1 */ 1999 #define PIO_PA3B_USART1_LONCOL1 (_UL_(1) << 3) 2000 2001 #define PIN_PA29A_USART1_RI1 _L_(29) /**< USART1 signal: RI1 on PA29 mux A*/ 2002 #define MUX_PA29A_USART1_RI1 _L_(0) /**< USART1 signal line function value: RI1 */ 2003 #define PIO_PA29A_USART1_RI1 (_UL_(1) << 29) 2004 2005 #define PIN_PA24A_USART1_RTS1 _L_(24) /**< USART1 signal: RTS1 on PA24 mux A*/ 2006 #define MUX_PA24A_USART1_RTS1 _L_(0) /**< USART1 signal line function value: RTS1 */ 2007 #define PIO_PA24A_USART1_RTS1 (_UL_(1) << 24) 2008 2009 #define PIN_PA21A_USART1_RXD1 _L_(21) /**< USART1 signal: RXD1 on PA21 mux A*/ 2010 #define MUX_PA21A_USART1_RXD1 _L_(0) /**< USART1 signal line function value: RXD1 */ 2011 #define PIO_PA21A_USART1_RXD1 (_UL_(1) << 21) 2012 2013 #define PIN_PA23A_USART1_SCK1 _L_(23) /**< USART1 signal: SCK1 on PA23 mux A*/ 2014 #define MUX_PA23A_USART1_SCK1 _L_(0) /**< USART1 signal line function value: SCK1 */ 2015 #define PIO_PA23A_USART1_SCK1 (_UL_(1) << 23) 2016 2017 #define PIN_PB4D_USART1_TXD1 _L_(36) /**< USART1 signal: TXD1 on PB4 mux D*/ 2018 #define MUX_PB4D_USART1_TXD1 _L_(3) /**< USART1 signal line function value: TXD1 */ 2019 #define PIO_PB4D_USART1_TXD1 (_UL_(1) << 4) 2020 2021 /* ========== PIO definition for USART2 peripheral ========== */ 2022 #define PIN_PD19B_USART2_CTS2 _L_(115) /**< USART2 signal: CTS2 on PD19 mux B*/ 2023 #define MUX_PD19B_USART2_CTS2 _L_(1) /**< USART2 signal line function value: CTS2 */ 2024 #define PIO_PD19B_USART2_CTS2 (_UL_(1) << 19) 2025 2026 #define PIN_PD4D_USART2_DCD2 _L_(100) /**< USART2 signal: DCD2 on PD4 mux D*/ 2027 #define MUX_PD4D_USART2_DCD2 _L_(3) /**< USART2 signal line function value: DCD2 */ 2028 #define PIO_PD4D_USART2_DCD2 (_UL_(1) << 4) 2029 2030 #define PIN_PD6D_USART2_DSR2 _L_(102) /**< USART2 signal: DSR2 on PD6 mux D*/ 2031 #define MUX_PD6D_USART2_DSR2 _L_(3) /**< USART2 signal line function value: DSR2 */ 2032 #define PIO_PD6D_USART2_DSR2 (_UL_(1) << 6) 2033 2034 #define PIN_PD5D_USART2_DTR2 _L_(101) /**< USART2 signal: DTR2 on PD5 mux D*/ 2035 #define MUX_PD5D_USART2_DTR2 _L_(3) /**< USART2 signal line function value: DTR2 */ 2036 #define PIO_PD5D_USART2_DTR2 (_UL_(1) << 5) 2037 2038 #define PIN_PD7D_USART2_RI2 _L_(103) /**< USART2 signal: RI2 on PD7 mux D*/ 2039 #define MUX_PD7D_USART2_RI2 _L_(3) /**< USART2 signal line function value: RI2 */ 2040 #define PIO_PD7D_USART2_RI2 (_UL_(1) << 7) 2041 2042 #define PIN_PD18B_USART2_RTS2 _L_(114) /**< USART2 signal: RTS2 on PD18 mux B*/ 2043 #define MUX_PD18B_USART2_RTS2 _L_(1) /**< USART2 signal line function value: RTS2 */ 2044 #define PIO_PD18B_USART2_RTS2 (_UL_(1) << 18) 2045 2046 #define PIN_PD15B_USART2_RXD2 _L_(111) /**< USART2 signal: RXD2 on PD15 mux B*/ 2047 #define MUX_PD15B_USART2_RXD2 _L_(1) /**< USART2 signal line function value: RXD2 */ 2048 #define PIO_PD15B_USART2_RXD2 (_UL_(1) << 15) 2049 2050 #define PIN_PD17B_USART2_SCK2 _L_(113) /**< USART2 signal: SCK2 on PD17 mux B*/ 2051 #define MUX_PD17B_USART2_SCK2 _L_(1) /**< USART2 signal line function value: SCK2 */ 2052 #define PIO_PD17B_USART2_SCK2 (_UL_(1) << 17) 2053 2054 #define PIN_PD16B_USART2_TXD2 _L_(112) /**< USART2 signal: TXD2 on PD16 mux B*/ 2055 #define MUX_PD16B_USART2_TXD2 _L_(1) /**< USART2 signal line function value: TXD2 */ 2056 #define PIO_PD16B_USART2_TXD2 (_UL_(1) << 16) 2057 2058 /* ========== PIO definition for EBI peripheral ========== */ 2059 #define PIN_PC18A_EBI_A0 _L_(82) /**< EBI signal: A0 on PC18 mux A*/ 2060 #define MUX_PC18A_EBI_A0 _L_(0) /**< EBI signal line function value: A0 */ 2061 #define PIO_PC18A_EBI_A0 (_UL_(1) << 18) 2062 2063 #define PIN_PC18A_EBI_NBS0 _L_(82) /**< EBI signal: NBS0 on PC18 mux A*/ 2064 #define MUX_PC18A_EBI_NBS0 _L_(0) /**< EBI signal line function value: NBS0 */ 2065 #define PIO_PC18A_EBI_NBS0 (_UL_(1) << 18) 2066 2067 #define PIN_PC19A_EBI_A1 _L_(83) /**< EBI signal: A1 on PC19 mux A*/ 2068 #define MUX_PC19A_EBI_A1 _L_(0) /**< EBI signal line function value: A1 */ 2069 #define PIO_PC19A_EBI_A1 (_UL_(1) << 19) 2070 2071 #define PIN_PC20A_EBI_A2 _L_(84) /**< EBI signal: A2 on PC20 mux A*/ 2072 #define MUX_PC20A_EBI_A2 _L_(0) /**< EBI signal line function value: A2 */ 2073 #define PIO_PC20A_EBI_A2 (_UL_(1) << 20) 2074 2075 #define PIN_PC21A_EBI_A3 _L_(85) /**< EBI signal: A3 on PC21 mux A*/ 2076 #define MUX_PC21A_EBI_A3 _L_(0) /**< EBI signal line function value: A3 */ 2077 #define PIO_PC21A_EBI_A3 (_UL_(1) << 21) 2078 2079 #define PIN_PC22A_EBI_A4 _L_(86) /**< EBI signal: A4 on PC22 mux A*/ 2080 #define MUX_PC22A_EBI_A4 _L_(0) /**< EBI signal line function value: A4 */ 2081 #define PIO_PC22A_EBI_A4 (_UL_(1) << 22) 2082 2083 #define PIN_PC23A_EBI_A5 _L_(87) /**< EBI signal: A5 on PC23 mux A*/ 2084 #define MUX_PC23A_EBI_A5 _L_(0) /**< EBI signal line function value: A5 */ 2085 #define PIO_PC23A_EBI_A5 (_UL_(1) << 23) 2086 2087 #define PIN_PC24A_EBI_A6 _L_(88) /**< EBI signal: A6 on PC24 mux A*/ 2088 #define MUX_PC24A_EBI_A6 _L_(0) /**< EBI signal line function value: A6 */ 2089 #define PIO_PC24A_EBI_A6 (_UL_(1) << 24) 2090 2091 #define PIN_PC25A_EBI_A7 _L_(89) /**< EBI signal: A7 on PC25 mux A*/ 2092 #define MUX_PC25A_EBI_A7 _L_(0) /**< EBI signal line function value: A7 */ 2093 #define PIO_PC25A_EBI_A7 (_UL_(1) << 25) 2094 2095 #define PIN_PC26A_EBI_A8 _L_(90) /**< EBI signal: A8 on PC26 mux A*/ 2096 #define MUX_PC26A_EBI_A8 _L_(0) /**< EBI signal line function value: A8 */ 2097 #define PIO_PC26A_EBI_A8 (_UL_(1) << 26) 2098 2099 #define PIN_PC27A_EBI_A9 _L_(91) /**< EBI signal: A9 on PC27 mux A*/ 2100 #define MUX_PC27A_EBI_A9 _L_(0) /**< EBI signal line function value: A9 */ 2101 #define PIO_PC27A_EBI_A9 (_UL_(1) << 27) 2102 2103 #define PIN_PC28A_EBI_A10 _L_(92) /**< EBI signal: A10 on PC28 mux A*/ 2104 #define MUX_PC28A_EBI_A10 _L_(0) /**< EBI signal line function value: A10 */ 2105 #define PIO_PC28A_EBI_A10 (_UL_(1) << 28) 2106 2107 #define PIN_PC29A_EBI_A11 _L_(93) /**< EBI signal: A11 on PC29 mux A*/ 2108 #define MUX_PC29A_EBI_A11 _L_(0) /**< EBI signal line function value: A11 */ 2109 #define PIO_PC29A_EBI_A11 (_UL_(1) << 29) 2110 2111 #define PIN_PC30A_EBI_A12 _L_(94) /**< EBI signal: A12 on PC30 mux A*/ 2112 #define MUX_PC30A_EBI_A12 _L_(0) /**< EBI signal line function value: A12 */ 2113 #define PIO_PC30A_EBI_A12 (_UL_(1) << 30) 2114 2115 #define PIN_PC31A_EBI_A13 _L_(95) /**< EBI signal: A13 on PC31 mux A*/ 2116 #define MUX_PC31A_EBI_A13 _L_(0) /**< EBI signal line function value: A13 */ 2117 #define PIO_PC31A_EBI_A13 (_UL_(1) << 31) 2118 2119 #define PIN_PA18C_EBI_A14 _L_(18) /**< EBI signal: A14 on PA18 mux C*/ 2120 #define MUX_PA18C_EBI_A14 _L_(2) /**< EBI signal line function value: A14 */ 2121 #define PIO_PA18C_EBI_A14 (_UL_(1) << 18) 2122 2123 #define PIN_PA19C_EBI_A15 _L_(19) /**< EBI signal: A15 on PA19 mux C*/ 2124 #define MUX_PA19C_EBI_A15 _L_(2) /**< EBI signal line function value: A15 */ 2125 #define PIO_PA19C_EBI_A15 (_UL_(1) << 19) 2126 2127 #define PIN_PA20C_EBI_A16 _L_(20) /**< EBI signal: A16 on PA20 mux C*/ 2128 #define MUX_PA20C_EBI_A16 _L_(2) /**< EBI signal line function value: A16 */ 2129 #define PIO_PA20C_EBI_A16 (_UL_(1) << 20) 2130 2131 #define PIN_PA20C_EBI_BA0 _L_(20) /**< EBI signal: BA0 on PA20 mux C*/ 2132 #define MUX_PA20C_EBI_BA0 _L_(2) /**< EBI signal line function value: BA0 */ 2133 #define PIO_PA20C_EBI_BA0 (_UL_(1) << 20) 2134 2135 #define PIN_PA0C_EBI_A17 _L_(0) /**< EBI signal: A17 on PA0 mux C*/ 2136 #define MUX_PA0C_EBI_A17 _L_(2) /**< EBI signal line function value: A17 */ 2137 #define PIO_PA0C_EBI_A17 (_UL_(1) << 0) 2138 2139 #define PIN_PA0C_EBI_BA1 _L_(0) /**< EBI signal: BA1 on PA0 mux C*/ 2140 #define MUX_PA0C_EBI_BA1 _L_(2) /**< EBI signal line function value: BA1 */ 2141 #define PIO_PA0C_EBI_BA1 (_UL_(1) << 0) 2142 2143 #define PIN_PA1C_EBI_A18 _L_(1) /**< EBI signal: A18 on PA1 mux C*/ 2144 #define MUX_PA1C_EBI_A18 _L_(2) /**< EBI signal line function value: A18 */ 2145 #define PIO_PA1C_EBI_A18 (_UL_(1) << 1) 2146 2147 #define PIN_PA23C_EBI_A19 _L_(23) /**< EBI signal: A19 on PA23 mux C*/ 2148 #define MUX_PA23C_EBI_A19 _L_(2) /**< EBI signal line function value: A19 */ 2149 #define PIO_PA23C_EBI_A19 (_UL_(1) << 23) 2150 2151 #define PIN_PA24C_EBI_A20 _L_(24) /**< EBI signal: A20 on PA24 mux C*/ 2152 #define MUX_PA24C_EBI_A20 _L_(2) /**< EBI signal line function value: A20 */ 2153 #define PIO_PA24C_EBI_A20 (_UL_(1) << 24) 2154 2155 #define PIN_PC16A_EBI_A21 _L_(80) /**< EBI signal: A21 on PC16 mux A*/ 2156 #define MUX_PC16A_EBI_A21 _L_(0) /**< EBI signal line function value: A21 */ 2157 #define PIO_PC16A_EBI_A21 (_UL_(1) << 16) 2158 2159 #define PIN_PC16A_EBI_NANDALE _L_(80) /**< EBI signal: NANDALE on PC16 mux A*/ 2160 #define MUX_PC16A_EBI_NANDALE _L_(0) /**< EBI signal line function value: NANDALE */ 2161 #define PIO_PC16A_EBI_NANDALE (_UL_(1) << 16) 2162 2163 #define PIN_PC17A_EBI_A22 _L_(81) /**< EBI signal: A22 on PC17 mux A*/ 2164 #define MUX_PC17A_EBI_A22 _L_(0) /**< EBI signal line function value: A22 */ 2165 #define PIO_PC17A_EBI_A22 (_UL_(1) << 17) 2166 2167 #define PIN_PC17A_EBI_NANDCLE _L_(81) /**< EBI signal: NANDCLE on PC17 mux A*/ 2168 #define MUX_PC17A_EBI_NANDCLE _L_(0) /**< EBI signal line function value: NANDCLE */ 2169 #define PIO_PC17A_EBI_NANDCLE (_UL_(1) << 17) 2170 2171 #define PIN_PA25C_EBI_A23 _L_(25) /**< EBI signal: A23 on PA25 mux C*/ 2172 #define MUX_PA25C_EBI_A23 _L_(2) /**< EBI signal line function value: A23 */ 2173 #define PIO_PA25C_EBI_A23 (_UL_(1) << 25) 2174 2175 #define PIN_PD17C_EBI_CAS _L_(113) /**< EBI signal: CAS on PD17 mux C*/ 2176 #define MUX_PD17C_EBI_CAS _L_(2) /**< EBI signal line function value: CAS */ 2177 #define PIO_PD17C_EBI_CAS (_UL_(1) << 17) 2178 2179 #define PIN_PC0A_EBI_D0 _L_(64) /**< EBI signal: D0 on PC0 mux A*/ 2180 #define MUX_PC0A_EBI_D0 _L_(0) /**< EBI signal line function value: D0 */ 2181 #define PIO_PC0A_EBI_D0 (_UL_(1) << 0) 2182 2183 #define PIN_PC1A_EBI_D1 _L_(65) /**< EBI signal: D1 on PC1 mux A*/ 2184 #define MUX_PC1A_EBI_D1 _L_(0) /**< EBI signal line function value: D1 */ 2185 #define PIO_PC1A_EBI_D1 (_UL_(1) << 1) 2186 2187 #define PIN_PC2A_EBI_D2 _L_(66) /**< EBI signal: D2 on PC2 mux A*/ 2188 #define MUX_PC2A_EBI_D2 _L_(0) /**< EBI signal line function value: D2 */ 2189 #define PIO_PC2A_EBI_D2 (_UL_(1) << 2) 2190 2191 #define PIN_PC3A_EBI_D3 _L_(67) /**< EBI signal: D3 on PC3 mux A*/ 2192 #define MUX_PC3A_EBI_D3 _L_(0) /**< EBI signal line function value: D3 */ 2193 #define PIO_PC3A_EBI_D3 (_UL_(1) << 3) 2194 2195 #define PIN_PC4A_EBI_D4 _L_(68) /**< EBI signal: D4 on PC4 mux A*/ 2196 #define MUX_PC4A_EBI_D4 _L_(0) /**< EBI signal line function value: D4 */ 2197 #define PIO_PC4A_EBI_D4 (_UL_(1) << 4) 2198 2199 #define PIN_PC5A_EBI_D5 _L_(69) /**< EBI signal: D5 on PC5 mux A*/ 2200 #define MUX_PC5A_EBI_D5 _L_(0) /**< EBI signal line function value: D5 */ 2201 #define PIO_PC5A_EBI_D5 (_UL_(1) << 5) 2202 2203 #define PIN_PC6A_EBI_D6 _L_(70) /**< EBI signal: D6 on PC6 mux A*/ 2204 #define MUX_PC6A_EBI_D6 _L_(0) /**< EBI signal line function value: D6 */ 2205 #define PIO_PC6A_EBI_D6 (_UL_(1) << 6) 2206 2207 #define PIN_PC7A_EBI_D7 _L_(71) /**< EBI signal: D7 on PC7 mux A*/ 2208 #define MUX_PC7A_EBI_D7 _L_(0) /**< EBI signal line function value: D7 */ 2209 #define PIO_PC7A_EBI_D7 (_UL_(1) << 7) 2210 2211 #define PIN_PE0A_EBI_D8 _L_(128) /**< EBI signal: D8 on PE0 mux A*/ 2212 #define MUX_PE0A_EBI_D8 _L_(0) /**< EBI signal line function value: D8 */ 2213 #define PIO_PE0A_EBI_D8 (_UL_(1) << 0) 2214 2215 #define PIN_PE1A_EBI_D9 _L_(129) /**< EBI signal: D9 on PE1 mux A*/ 2216 #define MUX_PE1A_EBI_D9 _L_(0) /**< EBI signal line function value: D9 */ 2217 #define PIO_PE1A_EBI_D9 (_UL_(1) << 1) 2218 2219 #define PIN_PE2A_EBI_D10 _L_(130) /**< EBI signal: D10 on PE2 mux A*/ 2220 #define MUX_PE2A_EBI_D10 _L_(0) /**< EBI signal line function value: D10 */ 2221 #define PIO_PE2A_EBI_D10 (_UL_(1) << 2) 2222 2223 #define PIN_PE3A_EBI_D11 _L_(131) /**< EBI signal: D11 on PE3 mux A*/ 2224 #define MUX_PE3A_EBI_D11 _L_(0) /**< EBI signal line function value: D11 */ 2225 #define PIO_PE3A_EBI_D11 (_UL_(1) << 3) 2226 2227 #define PIN_PE4A_EBI_D12 _L_(132) /**< EBI signal: D12 on PE4 mux A*/ 2228 #define MUX_PE4A_EBI_D12 _L_(0) /**< EBI signal line function value: D12 */ 2229 #define PIO_PE4A_EBI_D12 (_UL_(1) << 4) 2230 2231 #define PIN_PE5A_EBI_D13 _L_(133) /**< EBI signal: D13 on PE5 mux A*/ 2232 #define MUX_PE5A_EBI_D13 _L_(0) /**< EBI signal line function value: D13 */ 2233 #define PIO_PE5A_EBI_D13 (_UL_(1) << 5) 2234 2235 #define PIN_PA15A_EBI_D14 _L_(15) /**< EBI signal: D14 on PA15 mux A*/ 2236 #define MUX_PA15A_EBI_D14 _L_(0) /**< EBI signal line function value: D14 */ 2237 #define PIO_PA15A_EBI_D14 (_UL_(1) << 15) 2238 2239 #define PIN_PA16A_EBI_D15 _L_(16) /**< EBI signal: D15 on PA16 mux A*/ 2240 #define MUX_PA16A_EBI_D15 _L_(0) /**< EBI signal line function value: D15 */ 2241 #define PIO_PA16A_EBI_D15 (_UL_(1) << 16) 2242 2243 #define PIN_PC9A_EBI_NANDOE _L_(73) /**< EBI signal: NANDOE on PC9 mux A*/ 2244 #define MUX_PC9A_EBI_NANDOE _L_(0) /**< EBI signal line function value: NANDOE */ 2245 #define PIO_PC9A_EBI_NANDOE (_UL_(1) << 9) 2246 2247 #define PIN_PC10A_EBI_NANDWE _L_(74) /**< EBI signal: NANDWE on PC10 mux A*/ 2248 #define MUX_PC10A_EBI_NANDWE _L_(0) /**< EBI signal line function value: NANDWE */ 2249 #define PIO_PC10A_EBI_NANDWE (_UL_(1) << 10) 2250 2251 #define PIN_PC14A_EBI_NCS0 _L_(78) /**< EBI signal: NCS0 on PC14 mux A*/ 2252 #define MUX_PC14A_EBI_NCS0 _L_(0) /**< EBI signal line function value: NCS0 */ 2253 #define PIO_PC14A_EBI_NCS0 (_UL_(1) << 14) 2254 2255 #define PIN_PC15A_EBI_NCS1 _L_(79) /**< EBI signal: NCS1 on PC15 mux A*/ 2256 #define MUX_PC15A_EBI_NCS1 _L_(0) /**< EBI signal line function value: NCS1 */ 2257 #define PIO_PC15A_EBI_NCS1 (_UL_(1) << 15) 2258 2259 #define PIN_PC15A_EBI_SDCS _L_(79) /**< EBI signal: SDCS on PC15 mux A*/ 2260 #define MUX_PC15A_EBI_SDCS _L_(0) /**< EBI signal line function value: SDCS */ 2261 #define PIO_PC15A_EBI_SDCS (_UL_(1) << 15) 2262 2263 #define PIN_PD18A_EBI_NCS1 _L_(114) /**< EBI signal: NCS1 on PD18 mux A*/ 2264 #define MUX_PD18A_EBI_NCS1 _L_(0) /**< EBI signal line function value: NCS1 */ 2265 #define PIO_PD18A_EBI_NCS1 (_UL_(1) << 18) 2266 2267 #define PIN_PD18A_EBI_SDCS _L_(114) /**< EBI signal: SDCS on PD18 mux A*/ 2268 #define MUX_PD18A_EBI_SDCS _L_(0) /**< EBI signal line function value: SDCS */ 2269 #define PIO_PD18A_EBI_SDCS (_UL_(1) << 18) 2270 2271 #define PIN_PA22C_EBI_NCS2 _L_(22) /**< EBI signal: NCS2 on PA22 mux C*/ 2272 #define MUX_PA22C_EBI_NCS2 _L_(2) /**< EBI signal line function value: NCS2 */ 2273 #define PIO_PA22C_EBI_NCS2 (_UL_(1) << 22) 2274 2275 #define PIN_PC12A_EBI_NCS3 _L_(76) /**< EBI signal: NCS3 on PC12 mux A*/ 2276 #define MUX_PC12A_EBI_NCS3 _L_(0) /**< EBI signal line function value: NCS3 */ 2277 #define PIO_PC12A_EBI_NCS3 (_UL_(1) << 12) 2278 2279 #define PIN_PD19A_EBI_NCS3 _L_(115) /**< EBI signal: NCS3 on PD19 mux A*/ 2280 #define MUX_PD19A_EBI_NCS3 _L_(0) /**< EBI signal line function value: NCS3 */ 2281 #define PIO_PD19A_EBI_NCS3 (_UL_(1) << 19) 2282 2283 #define PIN_PC11A_EBI_NRD _L_(75) /**< EBI signal: NRD on PC11 mux A*/ 2284 #define MUX_PC11A_EBI_NRD _L_(0) /**< EBI signal line function value: NRD */ 2285 #define PIO_PC11A_EBI_NRD (_UL_(1) << 11) 2286 2287 #define PIN_PC13A_EBI_NWAIT _L_(77) /**< EBI signal: NWAIT on PC13 mux A*/ 2288 #define MUX_PC13A_EBI_NWAIT _L_(0) /**< EBI signal line function value: NWAIT */ 2289 #define PIO_PC13A_EBI_NWAIT (_UL_(1) << 13) 2290 2291 #define PIN_PC8A_EBI_NWR0 _L_(72) /**< EBI signal: NWR0 on PC8 mux A*/ 2292 #define MUX_PC8A_EBI_NWR0 _L_(0) /**< EBI signal line function value: NWR0 */ 2293 #define PIO_PC8A_EBI_NWR0 (_UL_(1) << 8) 2294 2295 #define PIN_PC8A_EBI_NWE _L_(72) /**< EBI signal: NWE on PC8 mux A*/ 2296 #define MUX_PC8A_EBI_NWE _L_(0) /**< EBI signal line function value: NWE */ 2297 #define PIO_PC8A_EBI_NWE (_UL_(1) << 8) 2298 2299 #define PIN_PD15C_EBI_NWR1 _L_(111) /**< EBI signal: NWR1 on PD15 mux C*/ 2300 #define MUX_PD15C_EBI_NWR1 _L_(2) /**< EBI signal line function value: NWR1 */ 2301 #define PIO_PD15C_EBI_NWR1 (_UL_(1) << 15) 2302 2303 #define PIN_PD15C_EBI_NBS1 _L_(111) /**< EBI signal: NBS1 on PD15 mux C*/ 2304 #define MUX_PD15C_EBI_NBS1 _L_(2) /**< EBI signal line function value: NBS1 */ 2305 #define PIO_PD15C_EBI_NBS1 (_UL_(1) << 15) 2306 2307 #define PIN_PD16C_EBI_RAS _L_(112) /**< EBI signal: RAS on PD16 mux C*/ 2308 #define MUX_PD16C_EBI_RAS _L_(2) /**< EBI signal line function value: RAS */ 2309 #define PIO_PD16C_EBI_RAS (_UL_(1) << 16) 2310 2311 #define PIN_PC13C_EBI_SDA10 _L_(77) /**< EBI signal: SDA10 on PC13 mux C*/ 2312 #define MUX_PC13C_EBI_SDA10 _L_(2) /**< EBI signal line function value: SDA10 */ 2313 #define PIO_PC13C_EBI_SDA10 (_UL_(1) << 13) 2314 2315 #define PIN_PD13C_EBI_SDA10 _L_(109) /**< EBI signal: SDA10 on PD13 mux C*/ 2316 #define MUX_PD13C_EBI_SDA10 _L_(2) /**< EBI signal line function value: SDA10 */ 2317 #define PIO_PD13C_EBI_SDA10 (_UL_(1) << 13) 2318 2319 #define PIN_PD23C_EBI_SDCK _L_(119) /**< EBI signal: SDCK on PD23 mux C*/ 2320 #define MUX_PD23C_EBI_SDCK _L_(2) /**< EBI signal line function value: SDCK */ 2321 #define PIO_PD23C_EBI_SDCK (_UL_(1) << 23) 2322 2323 #define PIN_PD14C_EBI_SDCKE _L_(110) /**< EBI signal: SDCKE on PD14 mux C*/ 2324 #define MUX_PD14C_EBI_SDCKE _L_(2) /**< EBI signal line function value: SDCKE */ 2325 #define PIO_PD14C_EBI_SDCKE (_UL_(1) << 14) 2326 2327 #define PIN_PD29C_EBI_SDWE _L_(125) /**< EBI signal: SDWE on PD29 mux C*/ 2328 #define MUX_PD29C_EBI_SDWE _L_(2) /**< EBI signal line function value: SDWE */ 2329 #define PIO_PD29C_EBI_SDWE (_UL_(1) << 29) 2330 2331 2332 #endif /* _SAMV71Q21_PIO_H_ */ 2333
