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21 * distributed under the License is distributed on an "AS IS" BASIS,
385 #define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: ADTRG on PA8 mux…
389 #define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AD0 on PD30 mux …
392 #define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AD1 on PA21 mux …
395 #define PIN_PA21X1_AFEC0_PIODCEN2 _L_(21) /**< AFEC0 signal: PIODCEN2 on PA21…
398 #define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AD2 on PB3 mux X…
401 #define PIN_PB3X1_AFEC0_WKUP12 _L_(35) /**< AFEC0 signal: WKUP12 on PB3 mu…
404 #define PIN_PE5X1_AFEC0_AD3 _L_(133) /**< AFEC0 signal: AD3 on PE5 mux X…
407 #define PIN_PE4X1_AFEC0_AD4 _L_(132) /**< AFEC0 signal: AD4 on PE4 mux X…
410 #define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AD5 on PB2 mux X…
413 #define PIN_PA17X1_AFEC0_AD6 _L_(17) /**< AFEC0 signal: AD6 on PA17 mux …
416 #define PIN_PA18X1_AFEC0_AD7 _L_(18) /**< AFEC0 signal: AD7 on PA18 mux …
419 #define PIN_PA19X1_AFEC0_AD8 _L_(19) /**< AFEC0 signal: AD8 on PA19 mux …
422 #define PIN_PA19X1_AFEC0_WKUP9 _L_(19) /**< AFEC0 signal: WKUP9 on PA19 mu…
425 #define PIN_PA20X1_AFEC0_AD9 _L_(20) /**< AFEC0 signal: AD9 on PA20 mux …
428 #define PIN_PA20X1_AFEC0_WKUP10 _L_(20) /**< AFEC0 signal: WKUP10 on PA20 m…
431 #define PIN_PB0X1_AFEC0_AD10 _L_(32) /**< AFEC0 signal: AD10 on PB0 mux …
434 #define PIN_PB0X1_AFEC0_RTCOUT0 _L_(32) /**< AFEC0 signal: RTCOUT0 on PB0 m…
438 #define PIN_PD9C_AFEC1_ADTRG _L_(105) /**< AFEC1 signal: ADTRG on PD9 mux…
442 #define PIN_PB1X1_AFEC1_AD0 _L_(33) /**< AFEC1 signal: AD0 on PB1 mux X…
445 #define PIN_PB1X1_AFEC1_RTCOUT1 _L_(33) /**< AFEC1 signal: RTCOUT1 on PB1 m…
448 #define PIN_PC13X1_AFEC1_AD1 _L_(77) /**< AFEC1 signal: AD1 on PC13 mux …
451 #define PIN_PC15X1_AFEC1_AD2 _L_(79) /**< AFEC1 signal: AD2 on PC15 mux …
454 #define PIN_PC12X1_AFEC1_AD3 _L_(76) /**< AFEC1 signal: AD3 on PC12 mux …
457 #define PIN_PC29X1_AFEC1_AD4 _L_(93) /**< AFEC1 signal: AD4 on PC29 mux …
460 #define PIN_PC30X1_AFEC1_AD5 _L_(94) /**< AFEC1 signal: AD5 on PC30 mux …
463 #define PIN_PC31X1_AFEC1_AD6 _L_(95) /**< AFEC1 signal: AD6 on PC31 mux …
466 #define PIN_PC26X1_AFEC1_AD7 _L_(90) /**< AFEC1 signal: AD7 on PC26 mux …
469 #define PIN_PC27X1_AFEC1_AD8 _L_(91) /**< AFEC1 signal: AD8 on PC27 mux …
472 #define PIN_PC0X1_AFEC1_AD9 _L_(64) /**< AFEC1 signal: AD9 on PC0 mux X…
475 #define PIN_PE3X1_AFEC1_AD10 _L_(131) /**< AFEC1 signal: AD10 on PE3 mux …
478 #define PIN_PE0X1_AFEC1_AD11 _L_(128) /**< AFEC1 signal: AD11 on PE0 mux …
482 #define PIN_PB13X1_DACC_DAC0 _L_(45) /**< DACC signal: DAC0 on PB13 mux …
485 #define PIN_PD0X1_DACC_DAC1 _L_(96) /**< DACC signal: DAC1 on PD0 mux X…
488 #define PIN_PA2C_DACC_DATRG _L_(2) /**< DACC signal: DATRG on PA2 mux …
493 #define PIN_PD13A_GMAC_GCOL _L_(109) /**< GMAC signal: GCOL on PD13 mux …
497 #define PIN_PD10A_GMAC_GCRS _L_(106) /**< GMAC signal: GCRS on PD10 mux …
501 #define PIN_PD8A_GMAC_GMDC _L_(104) /**< GMAC signal: GMDC on PD8 mux A…
505 #define PIN_PD9A_GMAC_GMDIO _L_(105) /**< GMAC signal: GMDIO on PD9 mux …
509 #define PIN_PD14A_GMAC_GRXCK _L_(110) /**< GMAC signal: GRXCK on PD14 mux…
513 #define PIN_PD4A_GMAC_GRXDV _L_(100) /**< GMAC signal: GRXDV on PD4 mux …
517 #define PIN_PD7A_GMAC_GRXER _L_(103) /**< GMAC signal: GRXER on PD7 mux …
521 #define PIN_PD5A_GMAC_GRX0 _L_(101) /**< GMAC signal: GRX0 on PD5 mux A…
525 #define PIN_PD6A_GMAC_GRX1 _L_(102) /**< GMAC signal: GRX1 on PD6 mux A…
529 #define PIN_PD11A_GMAC_GRX2 _L_(107) /**< GMAC signal: GRX2 on PD11 mux …
533 #define PIN_PD12A_GMAC_GRX3 _L_(108) /**< GMAC signal: GRX3 on PD12 mux …
537 #define PIN_PB1B_GMAC_GTSUCOMP _L_(33) /**< GMAC signal: GTSUCOMP on PB1 m…
541 #define PIN_PB12B_GMAC_GTSUCOMP _L_(44) /**< GMAC signal: GTSUCOMP on PB12 …
545 #define PIN_PD11C_GMAC_GTSUCOMP _L_(107) /**< GMAC signal: GTSUCOMP on PD11 …
549 #define PIN_PD20C_GMAC_GTSUCOMP _L_(116) /**< GMAC signal: GTSUCOMP on PD20 …
553 #define PIN_PD0A_GMAC_GTXCK _L_(96) /**< GMAC signal: GTXCK on PD0 mux …
557 #define PIN_PD1A_GMAC_GTXEN _L_(97) /**< GMAC signal: GTXEN on PD1 mux …
561 #define PIN_PD17A_GMAC_GTXER _L_(113) /**< GMAC signal: GTXER on PD17 mux…
565 #define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GTX0 on PD2 mux A…
569 #define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A…
573 #define PIN_PD15A_GMAC_GTX2 _L_(111) /**< GMAC signal: GTX2 on PD15 mux …
577 #define PIN_PD16A_GMAC_GTX3 _L_(112) /**< GMAC signal: GTX3 on PD16 mux …
582 #define PIN_PA28C_HSMCI_MCCDA _L_(28) /**< HSMCI signal: MCCDA on PA28 mu…
586 #define PIN_PA25D_HSMCI_MCCK _L_(25) /**< HSMCI signal: MCCK on PA25 mux…
590 #define PIN_PA30C_HSMCI_MCDA0 _L_(30) /**< HSMCI signal: MCDA0 on PA30 mu…
594 #define PIN_PA31C_HSMCI_MCDA1 _L_(31) /**< HSMCI signal: MCDA1 on PA31 mu…
598 #define PIN_PA26C_HSMCI_MCDA2 _L_(26) /**< HSMCI signal: MCDA2 on PA26 mu…
602 #define PIN_PA27C_HSMCI_MCDA3 _L_(27) /**< HSMCI signal: MCDA3 on PA27 mu…
607 #define PIN_PD22D_ISI_D0 _L_(118) /**< ISI signal: D0 on PD22 mux D*/
611 #define PIN_PD21D_ISI_D1 _L_(117) /**< ISI signal: D1 on PD21 mux D*/
615 #define PIN_PB3D_ISI_D2 _L_(35) /**< ISI signal: D2 on PB3 mux D*/
619 #define PIN_PA9B_ISI_D3 _L_(9) /**< ISI signal: D3 on PA9 mux B*/
623 #define PIN_PA5B_ISI_D4 _L_(5) /**< ISI signal: D4 on PA5 mux B*/
627 #define PIN_PD11D_ISI_D5 _L_(107) /**< ISI signal: D5 on PD11 mux D*/
631 #define PIN_PD12D_ISI_D6 _L_(108) /**< ISI signal: D6 on PD12 mux D*/
635 #define PIN_PA27D_ISI_D7 _L_(27) /**< ISI signal: D7 on PA27 mux D*/
639 #define PIN_PD27D_ISI_D8 _L_(123) /**< ISI signal: D8 on PD27 mux D*/
643 #define PIN_PD28D_ISI_D9 _L_(124) /**< ISI signal: D9 on PD28 mux D*/
647 #define PIN_PD30D_ISI_D10 _L_(126) /**< ISI signal: D10 on PD30 mux D*/
651 #define PIN_PD31D_ISI_D11 _L_(127) /**< ISI signal: D11 on PD31 mux D*/
655 #define PIN_PD24D_ISI_HSYNC _L_(120) /**< ISI signal: HSYNC on PD24 mux …
659 #define PIN_PA24D_ISI_PCK _L_(24) /**< ISI signal: PCK on PA24 mux D*/
663 #define PIN_PD25D_ISI_VSYNC _L_(121) /**< ISI signal: VSYNC on PD25 mux …
668 #define PIN_PB3A_MCAN0_CANRX0 _L_(35) /**< MCAN0 signal: CANRX0 on PB3 mu…
672 #define PIN_PB2A_MCAN0_CANTX0 _L_(34) /**< MCAN0 signal: CANTX0 on PB2 mu…
677 #define PIN_PC12C_MCAN1_CANRX1 _L_(76) /**< MCAN1 signal: CANRX1 on PC12 m…
681 #define PIN_PD28B_MCAN1_CANRX1 _L_(124) /**< MCAN1 signal: CANRX1 on PD28 m…
685 #define PIN_PC14C_MCAN1_CANTX1 _L_(78) /**< MCAN1 signal: CANTX1 on PC14 m…
689 #define PIN_PD12B_MCAN1_CANTX1 _L_(108) /**< MCAN1 signal: CANTX1 on PD12 m…
694 #define PIN_PA6B_PMC_PCK0 _L_(6) /**< PMC signal: PCK0 on PA6 mux B*/
698 #define PIN_PB12D_PMC_PCK0 _L_(44) /**< PMC signal: PCK0 on PB12 mux D…
702 #define PIN_PB13B_PMC_PCK0 _L_(45) /**< PMC signal: PCK0 on PB13 mux B…
706 #define PIN_PA17B_PMC_PCK1 _L_(17) /**< PMC signal: PCK1 on PA17 mux B…
710 #define PIN_PA21B_PMC_PCK1 _L_(21) /**< PMC signal: PCK1 on PA21 mux B…
714 #define PIN_PA3C_PMC_PCK2 _L_(3) /**< PMC signal: PCK2 on PA3 mux C*/
718 #define PIN_PA18B_PMC_PCK2 _L_(18) /**< PMC signal: PCK2 on PA18 mux B…
722 #define PIN_PA31B_PMC_PCK2 _L_(31) /**< PMC signal: PCK2 on PA31 mux B…
726 #define PIN_PB3B_PMC_PCK2 _L_(35) /**< PMC signal: PCK2 on PB3 mux B*/
730 #define PIN_PD31C_PMC_PCK2 _L_(127) /**< PMC signal: PCK2 on PD31 mux C…
735 #define PIN_PA10B_PWM0_PWMEXTRG0 _L_(10) /**< PWM0 signal: PWMEXTRG0 on PA10…
739 #define PIN_PA22B_PWM0_PWMEXTRG1 _L_(22) /**< PWM0 signal: PWMEXTRG1 on PA22…
743 #define PIN_PA9C_PWM0_PWMFI0 _L_(9) /**< PWM0 signal: PWMFI0 on PA9 mux…
747 #define PIN_PD8B_PWM0_PWMFI1 _L_(104) /**< PWM0 signal: PWMFI1 on PD8 mux…
751 #define PIN_PD9B_PWM0_PWMFI2 _L_(105) /**< PWM0 signal: PWMFI2 on PD9 mux…
755 #define PIN_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal: PWMH0 on PA0 mux …
759 #define PIN_PA11B_PWM0_PWMH0 _L_(11) /**< PWM0 signal: PWMH0 on PA11 mux…
763 #define PIN_PA23B_PWM0_PWMH0 _L_(23) /**< PWM0 signal: PWMH0 on PA23 mux…
767 #define PIN_PB0A_PWM0_PWMH0 _L_(32) /**< PWM0 signal: PWMH0 on PB0 mux …
771 #define PIN_PD11B_PWM0_PWMH0 _L_(107) /**< PWM0 signal: PWMH0 on PD11 mux…
775 #define PIN_PD20A_PWM0_PWMH0 _L_(116) /**< PWM0 signal: PWMH0 on PD20 mux…
779 #define PIN_PA2A_PWM0_PWMH1 _L_(2) /**< PWM0 signal: PWMH1 on PA2 mux …
783 #define PIN_PA12B_PWM0_PWMH1 _L_(12) /**< PWM0 signal: PWMH1 on PA12 mux…
787 #define PIN_PA24B_PWM0_PWMH1 _L_(24) /**< PWM0 signal: PWMH1 on PA24 mux…
791 #define PIN_PB1A_PWM0_PWMH1 _L_(33) /**< PWM0 signal: PWMH1 on PB1 mux …
795 #define PIN_PD21A_PWM0_PWMH1 _L_(117) /**< PWM0 signal: PWMH1 on PD21 mux…
799 #define PIN_PA13B_PWM0_PWMH2 _L_(13) /**< PWM0 signal: PWMH2 on PA13 mux…
803 #define PIN_PA25B_PWM0_PWMH2 _L_(25) /**< PWM0 signal: PWMH2 on PA25 mux…
807 #define PIN_PB4B_PWM0_PWMH2 _L_(36) /**< PWM0 signal: PWMH2 on PB4 mux …
811 #define PIN_PC19B_PWM0_PWMH2 _L_(83) /**< PWM0 signal: PWMH2 on PC19 mux…
815 #define PIN_PD22A_PWM0_PWMH2 _L_(118) /**< PWM0 signal: PWMH2 on PD22 mux…
819 #define PIN_PA7B_PWM0_PWMH3 _L_(7) /**< PWM0 signal: PWMH3 on PA7 mux …
823 #define PIN_PA14B_PWM0_PWMH3 _L_(14) /**< PWM0 signal: PWMH3 on PA14 mux…
827 #define PIN_PA17C_PWM0_PWMH3 _L_(17) /**< PWM0 signal: PWMH3 on PA17 mux…
831 #define PIN_PC13B_PWM0_PWMH3 _L_(77) /**< PWM0 signal: PWMH3 on PC13 mux…
835 #define PIN_PC21B_PWM0_PWMH3 _L_(85) /**< PWM0 signal: PWMH3 on PC21 mux…
839 #define PIN_PD23A_PWM0_PWMH3 _L_(119) /**< PWM0 signal: PWMH3 on PD23 mux…
843 #define PIN_PA1A_PWM0_PWML0 _L_(1) /**< PWM0 signal: PWML0 on PA1 mux …
847 #define PIN_PA19B_PWM0_PWML0 _L_(19) /**< PWM0 signal: PWML0 on PA19 mux…
851 #define PIN_PB5B_PWM0_PWML0 _L_(37) /**< PWM0 signal: PWML0 on PB5 mux …
855 #define PIN_PC0B_PWM0_PWML0 _L_(64) /**< PWM0 signal: PWML0 on PC0 mux …
859 #define PIN_PD10B_PWM0_PWML0 _L_(106) /**< PWM0 signal: PWML0 on PD10 mux…
863 #define PIN_PD24A_PWM0_PWML0 _L_(120) /**< PWM0 signal: PWML0 on PD24 mux…
867 #define PIN_PA20B_PWM0_PWML1 _L_(20) /**< PWM0 signal: PWML1 on PA20 mux…
871 #define PIN_PB12A_PWM0_PWML1 _L_(44) /**< PWM0 signal: PWML1 on PB12 mux…
875 #define PIN_PC1B_PWM0_PWML1 _L_(65) /**< PWM0 signal: PWML1 on PC1 mux …
879 #define PIN_PC18B_PWM0_PWML1 _L_(82) /**< PWM0 signal: PWML1 on PC18 mux…
883 #define PIN_PD25A_PWM0_PWML1 _L_(121) /**< PWM0 signal: PWML1 on PD25 mux…
887 #define PIN_PA16C_PWM0_PWML2 _L_(16) /**< PWM0 signal: PWML2 on PA16 mux…
891 #define PIN_PA30A_PWM0_PWML2 _L_(30) /**< PWM0 signal: PWML2 on PA30 mux…
895 #define PIN_PB13A_PWM0_PWML2 _L_(45) /**< PWM0 signal: PWML2 on PB13 mux…
899 #define PIN_PC2B_PWM0_PWML2 _L_(66) /**< PWM0 signal: PWML2 on PC2 mux …
903 #define PIN_PC20B_PWM0_PWML2 _L_(84) /**< PWM0 signal: PWML2 on PC20 mux…
907 #define PIN_PD26A_PWM0_PWML2 _L_(122) /**< PWM0 signal: PWML2 on PD26 mux…
911 #define PIN_PA15C_PWM0_PWML3 _L_(15) /**< PWM0 signal: PWML3 on PA15 mux…
915 #define PIN_PC3B_PWM0_PWML3 _L_(67) /**< PWM0 signal: PWML3 on PC3 mux …
919 #define PIN_PC15B_PWM0_PWML3 _L_(79) /**< PWM0 signal: PWML3 on PC15 mux…
923 #define PIN_PC22B_PWM0_PWML3 _L_(86) /**< PWM0 signal: PWML3 on PC22 mux…
927 #define PIN_PD27A_PWM0_PWML3 _L_(123) /**< PWM0 signal: PWML3 on PD27 mux…
932 #define PIN_PA30B_PWM1_PWMEXTRG0 _L_(30) /**< PWM1 signal: PWMEXTRG0 on PA30…
936 #define PIN_PA18A_PWM1_PWMEXTRG1 _L_(18) /**< PWM1 signal: PWMEXTRG1 on PA18…
940 #define PIN_PA21C_PWM1_PWMFI0 _L_(21) /**< PWM1 signal: PWMFI0 on PA21 mu…
944 #define PIN_PA26D_PWM1_PWMFI1 _L_(26) /**< PWM1 signal: PWMFI1 on PA26 mu…
948 #define PIN_PA28D_PWM1_PWMFI2 _L_(28) /**< PWM1 signal: PWMFI2 on PA28 mu…
952 #define PIN_PA12C_PWM1_PWMH0 _L_(12) /**< PWM1 signal: PWMH0 on PA12 mux…
956 #define PIN_PD1B_PWM1_PWMH0 _L_(97) /**< PWM1 signal: PWMH0 on PD1 mux …
960 #define PIN_PA14C_PWM1_PWMH1 _L_(14) /**< PWM1 signal: PWMH1 on PA14 mux…
964 #define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux …
968 #define PIN_PA31D_PWM1_PWMH2 _L_(31) /**< PWM1 signal: PWMH2 on PA31 mux…
972 #define PIN_PD5B_PWM1_PWMH2 _L_(101) /**< PWM1 signal: PWMH2 on PD5 mux …
976 #define PIN_PA8A_PWM1_PWMH3 _L_(8) /**< PWM1 signal: PWMH3 on PA8 mux …
980 #define PIN_PD7B_PWM1_PWMH3 _L_(103) /**< PWM1 signal: PWMH3 on PD7 mux …
984 #define PIN_PA11C_PWM1_PWML0 _L_(11) /**< PWM1 signal: PWML0 on PA11 mux…
988 #define PIN_PD0B_PWM1_PWML0 _L_(96) /**< PWM1 signal: PWML0 on PD0 mux …
992 #define PIN_PA13C_PWM1_PWML1 _L_(13) /**< PWM1 signal: PWML1 on PA13 mux…
996 #define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWML1 on PD2 mux …
1000 #define PIN_PA23D_PWM1_PWML2 _L_(23) /**< PWM1 signal: PWML2 on PA23 mux…
1004 #define PIN_PD4B_PWM1_PWML2 _L_(100) /**< PWM1 signal: PWML2 on PD4 mux …
1008 #define PIN_PA5A_PWM1_PWML3 _L_(5) /**< PWM1 signal: PWML3 on PA5 mux …
1012 #define PIN_PD6B_PWM1_PWML3 _L_(102) /**< PWM1 signal: PWML3 on PD6 mux …
1017 #define PIN_PA11A_QSPI_QCS _L_(11) /**< QSPI signal: QCS on PA11 mux A…
1021 #define PIN_PA13A_QSPI_QIO0 _L_(13) /**< QSPI signal: QIO0 on PA13 mux …
1025 #define PIN_PA12A_QSPI_QIO1 _L_(12) /**< QSPI signal: QIO1 on PA12 mux …
1029 #define PIN_PA17A_QSPI_QIO2 _L_(17) /**< QSPI signal: QIO2 on PA17 mux …
1033 #define PIN_PD31A_QSPI_QIO3 _L_(127) /**< QSPI signal: QIO3 on PD31 mux …
1037 #define PIN_PA14A_QSPI_QSCK _L_(14) /**< QSPI signal: QSCK on PA14 mux …
1042 #define PIN_PC18A_SDRAMC_A0 _L_(82) /**< SDRAMC signal: A0 on PC18 mux …
1046 #define PIN_PC18A_SDRAMC_NBS0 _L_(82) /**< SDRAMC signal: NBS0 on PC18 mu…
1050 #define PIN_PC19A_SDRAMC_A1 _L_(83) /**< SDRAMC signal: A1 on PC19 mux …
1054 #define PIN_PC20A_SDRAMC_A2 _L_(84) /**< SDRAMC signal: A2 on PC20 mux …
1058 #define PIN_PC21A_SDRAMC_A3 _L_(85) /**< SDRAMC signal: A3 on PC21 mux …
1062 #define PIN_PC22A_SDRAMC_A4 _L_(86) /**< SDRAMC signal: A4 on PC22 mux …
1066 #define PIN_PC23A_SDRAMC_A5 _L_(87) /**< SDRAMC signal: A5 on PC23 mux …
1070 #define PIN_PC24A_SDRAMC_A6 _L_(88) /**< SDRAMC signal: A6 on PC24 mux …
1074 #define PIN_PC25A_SDRAMC_A7 _L_(89) /**< SDRAMC signal: A7 on PC25 mux …
1078 #define PIN_PC26A_SDRAMC_A8 _L_(90) /**< SDRAMC signal: A8 on PC26 mux …
1082 #define PIN_PC27A_SDRAMC_A9 _L_(91) /**< SDRAMC signal: A9 on PC27 mux …
1086 #define PIN_PC28A_SDRAMC_A10 _L_(92) /**< SDRAMC signal: A10 on PC28 mux…
1090 #define PIN_PC29A_SDRAMC_A11 _L_(93) /**< SDRAMC signal: A11 on PC29 mux…
1094 #define PIN_PC30A_SDRAMC_A12 _L_(94) /**< SDRAMC signal: A12 on PC30 mux…
1098 #define PIN_PC31A_SDRAMC_A13 _L_(95) /**< SDRAMC signal: A13 on PC31 mux…
1102 #define PIN_PA18C_SDRAMC_A14 _L_(18) /**< SDRAMC signal: A14 on PA18 mux…
1106 #define PIN_PA19C_SDRAMC_A15 _L_(19) /**< SDRAMC signal: A15 on PA19 mux…
1110 #define PIN_PA20C_SDRAMC_A16 _L_(20) /**< SDRAMC signal: A16 on PA20 mux…
1114 #define PIN_PA20C_SDRAMC_BA0 _L_(20) /**< SDRAMC signal: BA0 on PA20 mux…
1118 #define PIN_PA0C_SDRAMC_A17 _L_(0) /**< SDRAMC signal: A17 on PA0 mux …
1122 #define PIN_PA0C_SDRAMC_BA1 _L_(0) /**< SDRAMC signal: BA1 on PA0 mux …
1126 #define PIN_PA1C_SDRAMC_A18 _L_(1) /**< SDRAMC signal: A18 on PA1 mux …
1130 #define PIN_PA23C_SDRAMC_A19 _L_(23) /**< SDRAMC signal: A19 on PA23 mux…
1134 #define PIN_PA24C_SDRAMC_A20 _L_(24) /**< SDRAMC signal: A20 on PA24 mux…
1138 #define PIN_PC16A_SDRAMC_A21 _L_(80) /**< SDRAMC signal: A21 on PC16 mux…
1142 #define PIN_PC16A_SDRAMC_NANDALE _L_(80) /**< SDRAMC signal: NANDALE on PC16…
1146 #define PIN_PC17A_SDRAMC_A22 _L_(81) /**< SDRAMC signal: A22 on PC17 mux…
1150 #define PIN_PC17A_SDRAMC_NANDCLE _L_(81) /**< SDRAMC signal: NANDCLE on PC17…
1154 #define PIN_PA25C_SDRAMC_A23 _L_(25) /**< SDRAMC signal: A23 on PA25 mux…
1158 #define PIN_PD17C_SDRAMC_CAS _L_(113) /**< SDRAMC signal: CAS on PD17 mux…
1162 #define PIN_PC0A_SDRAMC_D0 _L_(64) /**< SDRAMC signal: D0 on PC0 mux A…
1166 #define PIN_PC1A_SDRAMC_D1 _L_(65) /**< SDRAMC signal: D1 on PC1 mux A…
1170 #define PIN_PC2A_SDRAMC_D2 _L_(66) /**< SDRAMC signal: D2 on PC2 mux A…
1174 #define PIN_PC3A_SDRAMC_D3 _L_(67) /**< SDRAMC signal: D3 on PC3 mux A…
1178 #define PIN_PC4A_SDRAMC_D4 _L_(68) /**< SDRAMC signal: D4 on PC4 mux A…
1182 #define PIN_PC5A_SDRAMC_D5 _L_(69) /**< SDRAMC signal: D5 on PC5 mux A…
1186 #define PIN_PC6A_SDRAMC_D6 _L_(70) /**< SDRAMC signal: D6 on PC6 mux A…
1190 #define PIN_PC7A_SDRAMC_D7 _L_(71) /**< SDRAMC signal: D7 on PC7 mux A…
1194 #define PIN_PE0A_SDRAMC_D8 _L_(128) /**< SDRAMC signal: D8 on PE0 mux A…
1198 #define PIN_PE1A_SDRAMC_D9 _L_(129) /**< SDRAMC signal: D9 on PE1 mux A…
1202 #define PIN_PE2A_SDRAMC_D10 _L_(130) /**< SDRAMC signal: D10 on PE2 mux …
1206 #define PIN_PE3A_SDRAMC_D11 _L_(131) /**< SDRAMC signal: D11 on PE3 mux …
1210 #define PIN_PE4A_SDRAMC_D12 _L_(132) /**< SDRAMC signal: D12 on PE4 mux …
1214 #define PIN_PE5A_SDRAMC_D13 _L_(133) /**< SDRAMC signal: D13 on PE5 mux …
1218 #define PIN_PA15A_SDRAMC_D14 _L_(15) /**< SDRAMC signal: D14 on PA15 mux…
1222 #define PIN_PA16A_SDRAMC_D15 _L_(16) /**< SDRAMC signal: D15 on PA16 mux…
1226 #define PIN_PC9A_SDRAMC_NANDOE _L_(73) /**< SDRAMC signal: NANDOE on PC9 m…
1230 #define PIN_PC10A_SDRAMC_NANDWE _L_(74) /**< SDRAMC signal: NANDWE on PC10 …
1234 #define PIN_PC14A_SDRAMC_NCS0 _L_(78) /**< SDRAMC signal: NCS0 on PC14 mu…
1238 #define PIN_PC15A_SDRAMC_NCS1 _L_(79) /**< SDRAMC signal: NCS1 on PC15 mu…
1242 #define PIN_PC15A_SDRAMC_SDCS _L_(79) /**< SDRAMC signal: SDCS on PC15 mu…
1246 #define PIN_PD18A_SDRAMC_NCS1 _L_(114) /**< SDRAMC signal: NCS1 on PD18 mu…
1250 #define PIN_PD18A_SDRAMC_SDCS _L_(114) /**< SDRAMC signal: SDCS on PD18 mu…
1254 #define PIN_PA22C_SDRAMC_NCS2 _L_(22) /**< SDRAMC signal: NCS2 on PA22 mu…
1258 #define PIN_PC12A_SDRAMC_NCS3 _L_(76) /**< SDRAMC signal: NCS3 on PC12 mu…
1262 #define PIN_PD19A_SDRAMC_NCS3 _L_(115) /**< SDRAMC signal: NCS3 on PD19 mu…
1266 #define PIN_PC11A_SDRAMC_NRD _L_(75) /**< SDRAMC signal: NRD on PC11 mux…
1270 #define PIN_PC13A_SDRAMC_NWAIT _L_(77) /**< SDRAMC signal: NWAIT on PC13 m…
1274 #define PIN_PC8A_SDRAMC_NWR0 _L_(72) /**< SDRAMC signal: NWR0 on PC8 mux…
1278 #define PIN_PC8A_SDRAMC_NWE _L_(72) /**< SDRAMC signal: NWE on PC8 mux …
1282 #define PIN_PD15C_SDRAMC_NWR1 _L_(111) /**< SDRAMC signal: NWR1 on PD15 mu…
1286 #define PIN_PD15C_SDRAMC_NBS1 _L_(111) /**< SDRAMC signal: NBS1 on PD15 mu…
1290 #define PIN_PD16C_SDRAMC_RAS _L_(112) /**< SDRAMC signal: RAS on PD16 mux…
1294 #define PIN_PC13C_SDRAMC_SDA10 _L_(77) /**< SDRAMC signal: SDA10 on PC13 m…
1298 #define PIN_PD13C_SDRAMC_SDA10 _L_(109) /**< SDRAMC signal: SDA10 on PD13 m…
1302 #define PIN_PD23C_SDRAMC_SDCK _L_(119) /**< SDRAMC signal: SDCK on PD23 mu…
1306 #define PIN_PD14C_SDRAMC_SDCKE _L_(110) /**< SDRAMC signal: SDCKE on PD14 m…
1310 #define PIN_PD29C_SDRAMC_SDWE _L_(125) /**< SDRAMC signal: SDWE on PD29 mu…
1315 #define PIN_PC18A_SMC_A0 _L_(82) /**< SMC signal: A0 on PC18 mux A*/
1319 #define PIN_PC18A_SMC_NBS0 _L_(82) /**< SMC signal: NBS0 on PC18 mux A…
1323 #define PIN_PC19A_SMC_A1 _L_(83) /**< SMC signal: A1 on PC19 mux A*/
1327 #define PIN_PC20A_SMC_A2 _L_(84) /**< SMC signal: A2 on PC20 mux A*/
1331 #define PIN_PC21A_SMC_A3 _L_(85) /**< SMC signal: A3 on PC21 mux A*/
1335 #define PIN_PC22A_SMC_A4 _L_(86) /**< SMC signal: A4 on PC22 mux A*/
1339 #define PIN_PC23A_SMC_A5 _L_(87) /**< SMC signal: A5 on PC23 mux A*/
1343 #define PIN_PC24A_SMC_A6 _L_(88) /**< SMC signal: A6 on PC24 mux A*/
1347 #define PIN_PC25A_SMC_A7 _L_(89) /**< SMC signal: A7 on PC25 mux A*/
1351 #define PIN_PC26A_SMC_A8 _L_(90) /**< SMC signal: A8 on PC26 mux A*/
1355 #define PIN_PC27A_SMC_A9 _L_(91) /**< SMC signal: A9 on PC27 mux A*/
1359 #define PIN_PC28A_SMC_A10 _L_(92) /**< SMC signal: A10 on PC28 mux A*/
1363 #define PIN_PC29A_SMC_A11 _L_(93) /**< SMC signal: A11 on PC29 mux A*/
1367 #define PIN_PC30A_SMC_A12 _L_(94) /**< SMC signal: A12 on PC30 mux A*/
1371 #define PIN_PC31A_SMC_A13 _L_(95) /**< SMC signal: A13 on PC31 mux A*/
1375 #define PIN_PA18C_SMC_A14 _L_(18) /**< SMC signal: A14 on PA18 mux C*/
1379 #define PIN_PA19C_SMC_A15 _L_(19) /**< SMC signal: A15 on PA19 mux C*/
1383 #define PIN_PA20C_SMC_A16 _L_(20) /**< SMC signal: A16 on PA20 mux C*/
1387 #define PIN_PA20C_SMC_BA0 _L_(20) /**< SMC signal: BA0 on PA20 mux C*/
1391 #define PIN_PA0C_SMC_A17 _L_(0) /**< SMC signal: A17 on PA0 mux C*/
1395 #define PIN_PA0C_SMC_BA1 _L_(0) /**< SMC signal: BA1 on PA0 mux C*/
1399 #define PIN_PA1C_SMC_A18 _L_(1) /**< SMC signal: A18 on PA1 mux C*/
1403 #define PIN_PA23C_SMC_A19 _L_(23) /**< SMC signal: A19 on PA23 mux C*/
1407 #define PIN_PA24C_SMC_A20 _L_(24) /**< SMC signal: A20 on PA24 mux C*/
1411 #define PIN_PC16A_SMC_A21 _L_(80) /**< SMC signal: A21 on PC16 mux A*/
1415 #define PIN_PC16A_SMC_NANDALE _L_(80) /**< SMC signal: NANDALE on PC16 mu…
1419 #define PIN_PC17A_SMC_A22 _L_(81) /**< SMC signal: A22 on PC17 mux A*/
1423 #define PIN_PC17A_SMC_NANDCLE _L_(81) /**< SMC signal: NANDCLE on PC17 mu…
1427 #define PIN_PA25C_SMC_A23 _L_(25) /**< SMC signal: A23 on PA25 mux C*/
1431 #define PIN_PD17C_SMC_CAS _L_(113) /**< SMC signal: CAS on PD17 mux C*/
1435 #define PIN_PC0A_SMC_D0 _L_(64) /**< SMC signal: D0 on PC0 mux A*/
1439 #define PIN_PC1A_SMC_D1 _L_(65) /**< SMC signal: D1 on PC1 mux A*/
1443 #define PIN_PC2A_SMC_D2 _L_(66) /**< SMC signal: D2 on PC2 mux A*/
1447 #define PIN_PC3A_SMC_D3 _L_(67) /**< SMC signal: D3 on PC3 mux A*/
1451 #define PIN_PC4A_SMC_D4 _L_(68) /**< SMC signal: D4 on PC4 mux A*/
1455 #define PIN_PC5A_SMC_D5 _L_(69) /**< SMC signal: D5 on PC5 mux A*/
1459 #define PIN_PC6A_SMC_D6 _L_(70) /**< SMC signal: D6 on PC6 mux A*/
1463 #define PIN_PC7A_SMC_D7 _L_(71) /**< SMC signal: D7 on PC7 mux A*/
1467 #define PIN_PE0A_SMC_D8 _L_(128) /**< SMC signal: D8 on PE0 mux A*/
1471 #define PIN_PE1A_SMC_D9 _L_(129) /**< SMC signal: D9 on PE1 mux A*/
1475 #define PIN_PE2A_SMC_D10 _L_(130) /**< SMC signal: D10 on PE2 mux A*/
1479 #define PIN_PE3A_SMC_D11 _L_(131) /**< SMC signal: D11 on PE3 mux A*/
1483 #define PIN_PE4A_SMC_D12 _L_(132) /**< SMC signal: D12 on PE4 mux A*/
1487 #define PIN_PE5A_SMC_D13 _L_(133) /**< SMC signal: D13 on PE5 mux A*/
1491 #define PIN_PA15A_SMC_D14 _L_(15) /**< SMC signal: D14 on PA15 mux A*/
1495 #define PIN_PA16A_SMC_D15 _L_(16) /**< SMC signal: D15 on PA16 mux A*/
1499 #define PIN_PC9A_SMC_NANDOE _L_(73) /**< SMC signal: NANDOE on PC9 mux …
1503 #define PIN_PC10A_SMC_NANDWE _L_(74) /**< SMC signal: NANDWE on PC10 mux…
1507 #define PIN_PC14A_SMC_NCS0 _L_(78) /**< SMC signal: NCS0 on PC14 mux A…
1511 #define PIN_PC15A_SMC_NCS1 _L_(79) /**< SMC signal: NCS1 on PC15 mux A…
1515 #define PIN_PC15A_SMC_SDCS _L_(79) /**< SMC signal: SDCS on PC15 mux A…
1519 #define PIN_PD18A_SMC_NCS1 _L_(114) /**< SMC signal: NCS1 on PD18 mux A…
1523 #define PIN_PD18A_SMC_SDCS _L_(114) /**< SMC signal: SDCS on PD18 mux A…
1527 #define PIN_PA22C_SMC_NCS2 _L_(22) /**< SMC signal: NCS2 on PA22 mux C…
1531 #define PIN_PC12A_SMC_NCS3 _L_(76) /**< SMC signal: NCS3 on PC12 mux A…
1535 #define PIN_PD19A_SMC_NCS3 _L_(115) /**< SMC signal: NCS3 on PD19 mux A…
1539 #define PIN_PC11A_SMC_NRD _L_(75) /**< SMC signal: NRD on PC11 mux A*/
1543 #define PIN_PC13A_SMC_NWAIT _L_(77) /**< SMC signal: NWAIT on PC13 mux …
1547 #define PIN_PC8A_SMC_NWR0 _L_(72) /**< SMC signal: NWR0 on PC8 mux A*/
1551 #define PIN_PC8A_SMC_NWE _L_(72) /**< SMC signal: NWE on PC8 mux A*/
1555 #define PIN_PD15C_SMC_NWR1 _L_(111) /**< SMC signal: NWR1 on PD15 mux C…
1559 #define PIN_PD15C_SMC_NBS1 _L_(111) /**< SMC signal: NBS1 on PD15 mux C…
1563 #define PIN_PD16C_SMC_RAS _L_(112) /**< SMC signal: RAS on PD16 mux C*/
1567 #define PIN_PC13C_SMC_SDA10 _L_(77) /**< SMC signal: SDA10 on PC13 mux …
1571 #define PIN_PD13C_SMC_SDA10 _L_(109) /**< SMC signal: SDA10 on PD13 mux …
1575 #define PIN_PD23C_SMC_SDCK _L_(119) /**< SMC signal: SDCK on PD23 mux C…
1579 #define PIN_PD14C_SMC_SDCKE _L_(110) /**< SMC signal: SDCKE on PD14 mux …
1583 #define PIN_PD29C_SMC_SDWE _L_(125) /**< SMC signal: SDWE on PD29 mux C…
1588 #define PIN_PD20B_SPI0_MISO _L_(116) /**< SPI0 signal: MISO on PD20 mux …
1592 #define PIN_PD21B_SPI0_MOSI _L_(117) /**< SPI0 signal: MOSI on PD21 mux …
1596 #define PIN_PB2D_SPI0_NPCS0 _L_(34) /**< SPI0 signal: NPCS0 on PB2 mux …
1600 #define PIN_PA31A_SPI0_NPCS1 _L_(31) /**< SPI0 signal: NPCS1 on PA31 mux…
1604 #define PIN_PD25B_SPI0_NPCS1 _L_(121) /**< SPI0 signal: NPCS1 on PD25 mux…
1608 #define PIN_PD12C_SPI0_NPCS2 _L_(108) /**< SPI0 signal: NPCS2 on PD12 mux…
1612 #define PIN_PD27B_SPI0_NPCS3 _L_(123) /**< SPI0 signal: NPCS3 on PD27 mux…
1616 #define PIN_PD22B_SPI0_SPCK _L_(118) /**< SPI0 signal: SPCK on PD22 mux …
1621 #define PIN_PC26C_SPI1_MISO _L_(90) /**< SPI1 signal: MISO on PC26 mux …
1625 #define PIN_PC27C_SPI1_MOSI _L_(91) /**< SPI1 signal: MOSI on PC27 mux …
1629 #define PIN_PC25C_SPI1_NPCS0 _L_(89) /**< SPI1 signal: NPCS0 on PC25 mux…
1633 #define PIN_PC28C_SPI1_NPCS1 _L_(92) /**< SPI1 signal: NPCS1 on PC28 mux…
1637 #define PIN_PD0C_SPI1_NPCS1 _L_(96) /**< SPI1 signal: NPCS1 on PD0 mux …
1641 #define PIN_PC29C_SPI1_NPCS2 _L_(93) /**< SPI1 signal: NPCS2 on PC29 mux…
1645 #define PIN_PD1C_SPI1_NPCS2 _L_(97) /**< SPI1 signal: NPCS2 on PD1 mux …
1649 #define PIN_PC30C_SPI1_NPCS3 _L_(94) /**< SPI1 signal: NPCS3 on PC30 mux…
1653 #define PIN_PD2C_SPI1_NPCS3 _L_(98) /**< SPI1 signal: NPCS3 on PD2 mux …
1657 #define PIN_PC24C_SPI1_SPCK _L_(88) /**< SPI1 signal: SPCK on PC24 mux …
1662 #define PIN_PA10C_SSC_RD _L_(10) /**< SSC signal: RD on PA10 mux C*/
1666 #define PIN_PD24B_SSC_RF _L_(120) /**< SSC signal: RF on PD24 mux B*/
1670 #define PIN_PA22A_SSC_RK _L_(22) /**< SSC signal: RK on PA22 mux A*/
1674 #define PIN_PB5D_SSC_TD _L_(37) /**< SSC signal: TD on PB5 mux D*/
1678 #define PIN_PD10C_SSC_TD _L_(106) /**< SSC signal: TD on PD10 mux C*/
1682 #define PIN_PD26B_SSC_TD _L_(122) /**< SSC signal: TD on PD26 mux B*/
1686 #define PIN_PB0D_SSC_TF _L_(32) /**< SSC signal: TF on PB0 mux D*/
1690 #define PIN_PB1D_SSC_TK _L_(33) /**< SSC signal: TK on PB1 mux D*/
1695 #define PIN_PA4B_TC0_TCLK0 _L_(4) /**< TC0 signal: TCLK0 on PA4 mux B…
1699 #define PIN_PA28B_TC0_TCLK1 _L_(28) /**< TC0 signal: TCLK1 on PA28 mux …
1703 #define PIN_PA29B_TC0_TCLK2 _L_(29) /**< TC0 signal: TCLK2 on PA29 mux …
1707 #define PIN_PA0B_TC0_TIOA0 _L_(0) /**< TC0 signal: TIOA0 on PA0 mux B…
1711 #define PIN_PA15B_TC0_TIOA1 _L_(15) /**< TC0 signal: TIOA1 on PA15 mux …
1715 #define PIN_PA26B_TC0_TIOA2 _L_(26) /**< TC0 signal: TIOA2 on PA26 mux …
1719 #define PIN_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal: TIOB0 on PA1 mux B…
1723 #define PIN_PA16B_TC0_TIOB1 _L_(16) /**< TC0 signal: TIOB1 on PA16 mux …
1727 #define PIN_PA27B_TC0_TIOB2 _L_(27) /**< TC0 signal: TIOB2 on PA27 mux …
1732 #define PIN_PC25B_TC1_TCLK3 _L_(89) /**< TC1 signal: TCLK3 on PC25 mux …
1736 #define PIN_PC28B_TC1_TCLK4 _L_(92) /**< TC1 signal: TCLK4 on PC28 mux …
1740 #define PIN_PC31B_TC1_TCLK5 _L_(95) /**< TC1 signal: TCLK5 on PC31 mux …
1744 #define PIN_PC23B_TC1_TIOA3 _L_(87) /**< TC1 signal: TIOA3 on PC23 mux …
1748 #define PIN_PC26B_TC1_TIOA4 _L_(90) /**< TC1 signal: TIOA4 on PC26 mux …
1752 #define PIN_PC29B_TC1_TIOA5 _L_(93) /**< TC1 signal: TIOA5 on PC29 mux …
1756 #define PIN_PC24B_TC1_TIOB3 _L_(88) /**< TC1 signal: TIOB3 on PC24 mux …
1760 #define PIN_PC27B_TC1_TIOB4 _L_(91) /**< TC1 signal: TIOB4 on PC27 mux …
1764 #define PIN_PC30B_TC1_TIOB5 _L_(94) /**< TC1 signal: TIOB5 on PC30 mux …
1769 #define PIN_PC7B_TC2_TCLK6 _L_(71) /**< TC2 signal: TCLK6 on PC7 mux B…
1773 #define PIN_PC10B_TC2_TCLK7 _L_(74) /**< TC2 signal: TCLK7 on PC10 mux …
1777 #define PIN_PC14B_TC2_TCLK8 _L_(78) /**< TC2 signal: TCLK8 on PC14 mux …
1781 #define PIN_PC5B_TC2_TIOA6 _L_(69) /**< TC2 signal: TIOA6 on PC5 mux B…
1785 #define PIN_PC8B_TC2_TIOA7 _L_(72) /**< TC2 signal: TIOA7 on PC8 mux B…
1789 #define PIN_PC11B_TC2_TIOA8 _L_(75) /**< TC2 signal: TIOA8 on PC11 mux …
1793 #define PIN_PC6B_TC2_TIOB6 _L_(70) /**< TC2 signal: TIOB6 on PC6 mux B…
1797 #define PIN_PC9B_TC2_TIOB7 _L_(73) /**< TC2 signal: TIOB7 on PC9 mux B…
1801 #define PIN_PC12B_TC2_TIOB8 _L_(76) /**< TC2 signal: TIOB8 on PC12 mux …
1806 #define PIN_PE2B_TC3_TCLK9 _L_(130) /**< TC3 signal: TCLK9 on PE2 mux B…
1810 #define PIN_PE5B_TC3_TCLK10 _L_(133) /**< TC3 signal: TCLK10 on PE5 mux …
1814 #define PIN_PD24C_TC3_TCLK11 _L_(120) /**< TC3 signal: TCLK11 on PD24 mux…
1818 #define PIN_PE0B_TC3_TIOA9 _L_(128) /**< TC3 signal: TIOA9 on PE0 mux B…
1822 #define PIN_PE3B_TC3_TIOA10 _L_(131) /**< TC3 signal: TIOA10 on PE3 mux …
1826 #define PIN_PD21C_TC3_TIOA11 _L_(117) /**< TC3 signal: TIOA11 on PD21 mux…
1830 #define PIN_PE1B_TC3_TIOB9 _L_(129) /**< TC3 signal: TIOB9 on PE1 mux B…
1834 #define PIN_PE4B_TC3_TIOB10 _L_(132) /**< TC3 signal: TIOB10 on PE4 mux …
1838 #define PIN_PD22C_TC3_TIOB11 _L_(118) /**< TC3 signal: TIOB11 on PD22 mux…
1843 #define PIN_PA4A_TWIHS0_TWCK0 _L_(4) /**< TWIHS0 signal: TWCK0 on PA4 mu…
1847 #define PIN_PA3A_TWIHS0_TWD0 _L_(3) /**< TWIHS0 signal: TWD0 on PA3 mux…
1852 #define PIN_PB5A_TWIHS1_TWCK1 _L_(37) /**< TWIHS1 signal: TWCK1 on PB5 mu…
1856 #define PIN_PB4A_TWIHS1_TWD1 _L_(36) /**< TWIHS1 signal: TWD1 on PB4 mux…
1861 #define PIN_PD28C_TWIHS2_TWCK2 _L_(124) /**< TWIHS2 signal: TWCK2 on PD28 m…
1865 #define PIN_PD27C_TWIHS2_TWD2 _L_(123) /**< TWIHS2 signal: TWD2 on PD27 mu…
1870 #define PIN_PA9A_UART0_URXD0 _L_(9) /**< UART0 signal: URXD0 on PA9 mux…
1874 #define PIN_PA10A_UART0_UTXD0 _L_(10) /**< UART0 signal: UTXD0 on PA10 mu…
1879 #define PIN_PA5C_UART1_URXD1 _L_(5) /**< UART1 signal: URXD1 on PA5 mux…
1883 #define PIN_PA4C_UART1_UTXD1 _L_(4) /**< UART1 signal: UTXD1 on PA4 mux…
1887 #define PIN_PA6C_UART1_UTXD1 _L_(6) /**< UART1 signal: UTXD1 on PA6 mux…
1891 #define PIN_PD26D_UART1_UTXD1 _L_(122) /**< UART1 signal: UTXD1 on PD26 mu…
1896 #define PIN_PD25C_UART2_URXD2 _L_(121) /**< UART2 signal: URXD2 on PD25 mu…
1900 #define PIN_PD26C_UART2_UTXD2 _L_(122) /**< UART2 signal: UTXD2 on PD26 mu…
1905 #define PIN_PD28A_UART3_URXD3 _L_(124) /**< UART3 signal: URXD3 on PD28 mu…
1909 #define PIN_PD30A_UART3_UTXD3 _L_(126) /**< UART3 signal: UTXD3 on PD30 mu…
1913 #define PIN_PD31B_UART3_UTXD3 _L_(127) /**< UART3 signal: UTXD3 on PD31 mu…
1918 #define PIN_PD18C_UART4_URXD4 _L_(114) /**< UART4 signal: URXD4 on PD18 mu…
1922 #define PIN_PD3C_UART4_UTXD4 _L_(99) /**< UART4 signal: UTXD4 on PD3 mux…
1926 #define PIN_PD19C_UART4_UTXD4 _L_(115) /**< UART4 signal: UTXD4 on PD19 mu…
1931 #define PIN_PB2C_USART0_CTS0 _L_(34) /**< USART0 signal: CTS0 on PB2 mux…
1935 #define PIN_PD0D_USART0_DCD0 _L_(96) /**< USART0 signal: DCD0 on PD0 mux…
1939 #define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: DSR0 on PD2 mux…
1943 #define PIN_PD1D_USART0_DTR0 _L_(97) /**< USART0 signal: DTR0 on PD1 mux…
1947 #define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux …
1951 #define PIN_PB3C_USART0_RTS0 _L_(35) /**< USART0 signal: RTS0 on PB3 mux…
1955 #define PIN_PB0C_USART0_RXD0 _L_(32) /**< USART0 signal: RXD0 on PB0 mux…
1959 #define PIN_PB13C_USART0_SCK0 _L_(45) /**< USART0 signal: SCK0 on PB13 mu…
1963 #define PIN_PB1C_USART0_TXD0 _L_(33) /**< USART0 signal: TXD0 on PB1 mux…
1968 #define PIN_PA25A_USART1_CTS1 _L_(25) /**< USART1 signal: CTS1 on PA25 mu…
1972 #define PIN_PA26A_USART1_DCD1 _L_(26) /**< USART1 signal: DCD1 on PA26 mu…
1976 #define PIN_PA28A_USART1_DSR1 _L_(28) /**< USART1 signal: DSR1 on PA28 mu…
1980 #define PIN_PA27A_USART1_DTR1 _L_(27) /**< USART1 signal: DTR1 on PA27 mu…
1984 #define PIN_PA3B_USART1_LONCOL1 _L_(3) /**< USART1 signal: LONCOL1 on PA3 …
1988 #define PIN_PA29A_USART1_RI1 _L_(29) /**< USART1 signal: RI1 on PA29 mux…
1992 #define PIN_PA24A_USART1_RTS1 _L_(24) /**< USART1 signal: RTS1 on PA24 mu…
1996 #define PIN_PA21A_USART1_RXD1 _L_(21) /**< USART1 signal: RXD1 on PA21 mu…
2000 #define PIN_PA23A_USART1_SCK1 _L_(23) /**< USART1 signal: SCK1 on PA23 mu…
2004 #define PIN_PB4D_USART1_TXD1 _L_(36) /**< USART1 signal: TXD1 on PB4 mux…
2009 #define PIN_PD19B_USART2_CTS2 _L_(115) /**< USART2 signal: CTS2 on PD19 mu…
2013 #define PIN_PD4D_USART2_DCD2 _L_(100) /**< USART2 signal: DCD2 on PD4 mux…
2017 #define PIN_PD6D_USART2_DSR2 _L_(102) /**< USART2 signal: DSR2 on PD6 mux…
2021 #define PIN_PD5D_USART2_DTR2 _L_(101) /**< USART2 signal: DTR2 on PD5 mux…
2025 #define PIN_PD7D_USART2_RI2 _L_(103) /**< USART2 signal: RI2 on PD7 mux …
2029 #define PIN_PD18B_USART2_RTS2 _L_(114) /**< USART2 signal: RTS2 on PD18 mu…
2033 #define PIN_PD15B_USART2_RXD2 _L_(111) /**< USART2 signal: RXD2 on PD15 mu…
2037 #define PIN_PD17B_USART2_SCK2 _L_(113) /**< USART2 signal: SCK2 on PD17 mu…
2041 #define PIN_PD16B_USART2_TXD2 _L_(112) /**< USART2 signal: TXD2 on PD16 mu…
2046 #define PIN_PC18A_EBI_A0 _L_(82) /**< EBI signal: A0 on PC18 mux A*/
2050 #define PIN_PC18A_EBI_NBS0 _L_(82) /**< EBI signal: NBS0 on PC18 mux A…
2054 #define PIN_PC19A_EBI_A1 _L_(83) /**< EBI signal: A1 on PC19 mux A*/
2058 #define PIN_PC20A_EBI_A2 _L_(84) /**< EBI signal: A2 on PC20 mux A*/
2062 #define PIN_PC21A_EBI_A3 _L_(85) /**< EBI signal: A3 on PC21 mux A*/
2066 #define PIN_PC22A_EBI_A4 _L_(86) /**< EBI signal: A4 on PC22 mux A*/
2070 #define PIN_PC23A_EBI_A5 _L_(87) /**< EBI signal: A5 on PC23 mux A*/
2074 #define PIN_PC24A_EBI_A6 _L_(88) /**< EBI signal: A6 on PC24 mux A*/
2078 #define PIN_PC25A_EBI_A7 _L_(89) /**< EBI signal: A7 on PC25 mux A*/
2082 #define PIN_PC26A_EBI_A8 _L_(90) /**< EBI signal: A8 on PC26 mux A*/
2086 #define PIN_PC27A_EBI_A9 _L_(91) /**< EBI signal: A9 on PC27 mux A*/
2090 #define PIN_PC28A_EBI_A10 _L_(92) /**< EBI signal: A10 on PC28 mux A*/
2094 #define PIN_PC29A_EBI_A11 _L_(93) /**< EBI signal: A11 on PC29 mux A*/
2098 #define PIN_PC30A_EBI_A12 _L_(94) /**< EBI signal: A12 on PC30 mux A*/
2102 #define PIN_PC31A_EBI_A13 _L_(95) /**< EBI signal: A13 on PC31 mux A*/
2106 #define PIN_PA18C_EBI_A14 _L_(18) /**< EBI signal: A14 on PA18 mux C*/
2110 #define PIN_PA19C_EBI_A15 _L_(19) /**< EBI signal: A15 on PA19 mux C*/
2114 #define PIN_PA20C_EBI_A16 _L_(20) /**< EBI signal: A16 on PA20 mux C*/
2118 #define PIN_PA20C_EBI_BA0 _L_(20) /**< EBI signal: BA0 on PA20 mux C*/
2122 #define PIN_PA0C_EBI_A17 _L_(0) /**< EBI signal: A17 on PA0 mux C*/
2126 #define PIN_PA0C_EBI_BA1 _L_(0) /**< EBI signal: BA1 on PA0 mux C*/
2130 #define PIN_PA1C_EBI_A18 _L_(1) /**< EBI signal: A18 on PA1 mux C*/
2134 #define PIN_PA23C_EBI_A19 _L_(23) /**< EBI signal: A19 on PA23 mux C*/
2138 #define PIN_PA24C_EBI_A20 _L_(24) /**< EBI signal: A20 on PA24 mux C*/
2142 #define PIN_PC16A_EBI_A21 _L_(80) /**< EBI signal: A21 on PC16 mux A*/
2146 #define PIN_PC16A_EBI_NANDALE _L_(80) /**< EBI signal: NANDALE on PC16 mu…
2150 #define PIN_PC17A_EBI_A22 _L_(81) /**< EBI signal: A22 on PC17 mux A*/
2154 #define PIN_PC17A_EBI_NANDCLE _L_(81) /**< EBI signal: NANDCLE on PC17 mu…
2158 #define PIN_PA25C_EBI_A23 _L_(25) /**< EBI signal: A23 on PA25 mux C*/
2162 #define PIN_PD17C_EBI_CAS _L_(113) /**< EBI signal: CAS on PD17 mux C*/
2166 #define PIN_PC0A_EBI_D0 _L_(64) /**< EBI signal: D0 on PC0 mux A*/
2170 #define PIN_PC1A_EBI_D1 _L_(65) /**< EBI signal: D1 on PC1 mux A*/
2174 #define PIN_PC2A_EBI_D2 _L_(66) /**< EBI signal: D2 on PC2 mux A*/
2178 #define PIN_PC3A_EBI_D3 _L_(67) /**< EBI signal: D3 on PC3 mux A*/
2182 #define PIN_PC4A_EBI_D4 _L_(68) /**< EBI signal: D4 on PC4 mux A*/
2186 #define PIN_PC5A_EBI_D5 _L_(69) /**< EBI signal: D5 on PC5 mux A*/
2190 #define PIN_PC6A_EBI_D6 _L_(70) /**< EBI signal: D6 on PC6 mux A*/
2194 #define PIN_PC7A_EBI_D7 _L_(71) /**< EBI signal: D7 on PC7 mux A*/
2198 #define PIN_PE0A_EBI_D8 _L_(128) /**< EBI signal: D8 on PE0 mux A*/
2202 #define PIN_PE1A_EBI_D9 _L_(129) /**< EBI signal: D9 on PE1 mux A*/
2206 #define PIN_PE2A_EBI_D10 _L_(130) /**< EBI signal: D10 on PE2 mux A*/
2210 #define PIN_PE3A_EBI_D11 _L_(131) /**< EBI signal: D11 on PE3 mux A*/
2214 #define PIN_PE4A_EBI_D12 _L_(132) /**< EBI signal: D12 on PE4 mux A*/
2218 #define PIN_PE5A_EBI_D13 _L_(133) /**< EBI signal: D13 on PE5 mux A*/
2222 #define PIN_PA15A_EBI_D14 _L_(15) /**< EBI signal: D14 on PA15 mux A*/
2226 #define PIN_PA16A_EBI_D15 _L_(16) /**< EBI signal: D15 on PA16 mux A*/
2230 #define PIN_PC9A_EBI_NANDOE _L_(73) /**< EBI signal: NANDOE on PC9 mux …
2234 #define PIN_PC10A_EBI_NANDWE _L_(74) /**< EBI signal: NANDWE on PC10 mux…
2238 #define PIN_PC14A_EBI_NCS0 _L_(78) /**< EBI signal: NCS0 on PC14 mux A…
2242 #define PIN_PC15A_EBI_NCS1 _L_(79) /**< EBI signal: NCS1 on PC15 mux A…
2246 #define PIN_PC15A_EBI_SDCS _L_(79) /**< EBI signal: SDCS on PC15 mux A…
2250 #define PIN_PD18A_EBI_NCS1 _L_(114) /**< EBI signal: NCS1 on PD18 mux A…
2254 #define PIN_PD18A_EBI_SDCS _L_(114) /**< EBI signal: SDCS on PD18 mux A…
2258 #define PIN_PA22C_EBI_NCS2 _L_(22) /**< EBI signal: NCS2 on PA22 mux C…
2262 #define PIN_PC12A_EBI_NCS3 _L_(76) /**< EBI signal: NCS3 on PC12 mux A…
2266 #define PIN_PD19A_EBI_NCS3 _L_(115) /**< EBI signal: NCS3 on PD19 mux A…
2270 #define PIN_PC11A_EBI_NRD _L_(75) /**< EBI signal: NRD on PC11 mux A*/
2274 #define PIN_PC13A_EBI_NWAIT _L_(77) /**< EBI signal: NWAIT on PC13 mux …
2278 #define PIN_PC8A_EBI_NWR0 _L_(72) /**< EBI signal: NWR0 on PC8 mux A*/
2282 #define PIN_PC8A_EBI_NWE _L_(72) /**< EBI signal: NWE on PC8 mux A*/
2286 #define PIN_PD15C_EBI_NWR1 _L_(111) /**< EBI signal: NWR1 on PD15 mux C…
2290 #define PIN_PD15C_EBI_NBS1 _L_(111) /**< EBI signal: NBS1 on PD15 mux C…
2294 #define PIN_PD16C_EBI_RAS _L_(112) /**< EBI signal: RAS on PD16 mux C*/
2298 #define PIN_PC13C_EBI_SDA10 _L_(77) /**< EBI signal: SDA10 on PC13 mux …
2302 #define PIN_PD13C_EBI_SDA10 _L_(109) /**< EBI signal: SDA10 on PD13 mux …
2306 #define PIN_PD23C_EBI_SDCK _L_(119) /**< EBI signal: SDCK on PD23 mux C…
2310 #define PIN_PD14C_EBI_SDCKE _L_(110) /**< EBI signal: SDCKE on PD14 mux …
2314 #define PIN_PD29C_EBI_SDWE _L_(125) /**< EBI signal: SDWE on PD29 mux C…