| /Zephyr-latest/arch/arm/core/cortex_m/ |
| D | irq_manage.c | 2 * Copyright (c) 2013-2014 Wind River Systems, Inc.
4 * SPDX-License-Identifier: Apache-2.0
9 * @brief ARM Cortex-M interrupt management
12 * Interrupt management: enabling/disabling and dynamic ISR
49 return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq)); in arch_irq_is_enabled()
55 * @brief Set an interrupt's priority
77 /* Use caller supplied prio level as-is */ in z_arm_irq_priority_set()
86 * reduced set of priorities, like Cortex-M0/M0+). in z_arm_irq_priority_set()
88 __ASSERT(prio <= (BIT(NUM_IRQ_PRIO_BITS) - 1), in z_arm_irq_priority_set()
90 prio - _IRQ_PRIO_OFFSET, irq, in z_arm_irq_priority_set()
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| /Zephyr-latest/samples/drivers/watchdog/boards/ |
| D | cc26x2r1_launchxl.overlay | 2 /* uncomment to use Non-Maskable interrupt instead of the normal one */
3 /* interrupt-nmi; */
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| D | cc1352r1_launchxl.overlay | 2 /* uncomment to use Non-Maskable interrupt instead of the normal one */
3 /* interrupt-nmi; */
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| D | cc1352r1_sensortag.overlay | 2 /* uncomment to use Non-Maskable interrupt instead of the normal one */
3 /* interrupt-nmi; */
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| /Zephyr-latest/drivers/interrupt_controller/ |
| D | intc_nuclei_eclic.S | 4 * SPDX-License-Identifier: Apache-2.0
8 * @brief Assembler-hooks specific to Nuclei's Extended Core Interrupt Controller
18 * In non-vectored mode, interrupts are cleared when writing the mnxti register (done in
34 * This function services and clears all pending interrupts for an ECLIC in non-vectored mode.
37 addi sp, sp, -16
40 /* Read and clear mnxti to get highest current interrupt and enable interrupts. Will return
41 * original interrupt if no others appear. */
43 beqz a0, irq_done /* Check if original interrupt vanished. */
52 * the mtvt, sw irq table is 2-pointer wide -> shift by one. */
72 /* Read and clear mnxti to get highest current interrupt and enable interrupts. */
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| D | Kconfig.gic | 1 # ARM Generic Interrupt Controller (GIC) configuration
4 # SPDX-License-Identifier: Apache-2.0
15 The ARM Generic Interrupt Controller v1 (e.g. PL390) works with the
16 ARM Cortex-family processors.
22 The ARM Generic Interrupt Controller v2 (e.g. GIC-400) works with the
23 ARM Cortex-family processors.
29 The ARM Generic Interrupt Controller v3 (e.g. GIC-500 and GIC-600)
30 works with the ARM Cortex-family processors.
43 Some ARM Cortex-family processors only supports single security
55 bool "GIC v3 Interrupt Translation Service"
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| D | intc_nuclei_eclic.c | 4 * SPDX-License-Identifier: Apache-2.0
8 * @brief Driver for Nuclie's Extended Core Interrupt Controller
24 /** number of interrupt level bits */
51 /** Interrupt Pending */
60 /** Interrupt Enabled */
69 /** 0: non-vectored 1:vectored */
103 return (val << (8U - shift)); in leftalign8()
108 return ((1 << len) - 1) & 0xFFFFU; in mask8()
112 * @brief Enable interrupt
120 * @brief Disable interrupt
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| D | intc_esp32.c | 4 * SPDX-License-Identifier: Apache-2.0
39 * Define this to debug the choices made when allocating the interrupt. This leads to much debugging
40 * output within a critical region, which can lead to weird effects like e.g. the interrupt watchdog
49 /* Typedef for C-callable interrupt handler function */
67 * Interrupt handler table and unhandled interrupt routine. Duplicated
80 esp_rom_printf("Unhandled interrupt %d on cpu %d!\n", (int)arg, esp_cpu_get_core_id()); in default_intr_handler()
111 if (vd->cpu > to_insert->cpu) { in insert_vector_desc()
114 if (vd->cpu == to_insert->cpu && vd->intno >= to_insert->intno) { in insert_vector_desc()
118 vd = vd->next; in insert_vector_desc()
122 to_insert->next = vd; in insert_vector_desc()
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| /Zephyr-latest/arch/arm64/ |
| D | Kconfig | 3 # Copyright (c) 2014-2015 Wind River Systems, Inc.
4 # SPDX-License-Identifier: Apache-2.0
21 non-GIC) interrupt controller.
23 A number of Cortex-A and Cortex-R cores (Cortex-A5, Cortex-R4/5, ...)
24 allow interfacing to a custom external interrupt controller and this
25 option must be selected when such cores are connected to an interrupt
26 controller that is not the ARM Generic Interrupt Controller (GIC).
28 When this option is selected, the architecture interrupt control
29 functions are mapped to the SoC interrupt control interface, which is
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| /Zephyr-latest/dts/bindings/watchdog/ |
| D | ti,cc13xx-cc26xx-watchdog.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "ti,cc13xx-cc26xx-watchdog"
17 interrupt-nmi:
20 Whether the watchdog triggers a Non-Maskable Interrupt or a standard one
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| /Zephyr-latest/soc/intel/intel_adsp/ace/ |
| D | _soc_inthandlers.h | 2 * SPDX-License-Identifier: Apache-2.0
9 * declared to be associated with a given interrupt level. Each
10 * dispatcher will handle exactly one flagged interrupt, in numerical
16 #include <xtensa/config/core-isa.h>
21 #error core-isa.h interrupt level does not match dispatcher!
24 #error core-isa.h interrupt level does not match dispatcher!
27 #error core-isa.h interrupt level does not match dispatcher!
30 #error core-isa.h interrupt level does not match dispatcher!
33 #error core-isa.h interrupt level does not match dispatcher!
36 #error core-isa.h interrupt level does not match dispatcher!
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| D | comm_widget.h | 2 * SPDX-License-Identifier: Apache-2.0
103 * 0: 16-bit address
104 * 1: 48-bit address
170 * 10: Non-posted message
182 * Interrupt GENMASK
185 * Interrupt GENMASK register for message received interrupt. When set to 1 interrupt
186 * is not generated to DSP Core. GENMASK does not affect interrupt status bit.
194 * Message received interrupt status register. Set by HW when message is received,
227 * Completion data received for upstream non-posted read.
237 * Completion SAI received for upstream non-posted message.
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| /Zephyr-latest/dts/bindings/pcie/host/ |
| D | pci-host-ecam-generic.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "pci-host-ecam-generic"
8 include: pcie-controller.yaml
14 msi-parent:
21 As described in IEEE Std 1275-1994, but must provide at least a
22 definition of non-prefetchable memory. One or both of prefetchable Memory
25 interrupt-map-mask:
28 interrupt-map:
31 bus-range:
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| /Zephyr-latest/dts/bindings/arm/ |
| D | arm,ethos-u.yaml | 1 # Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com>
3 # SPDX-License-Identifier: Apache-2.0
6 The Arm Ethos-U is a micro NPU that enables neural networks to be hardware
7 accelerated on embedded devices. The Ethos-U NPU driver is provided as a
12 map address and interrupt line, and is therefore expected to be included
15 compatible: "arm,ethos-u"
26 secure-enable:
28 description: Configure Ethos-U NPU to operate in secure- or non-secure mode
30 privilege-enable:
32 description: Configure Ethos-U NPU to operate in privileged- or non-privileged mode
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| /Zephyr-latest/soc/arm/musca/b1/ |
| D | system_cmsdk_musca_b1.h | 2 * Copyright (c) 2017-2019 Arm Limited
4 * SPDX-License-Identifier: Apache-2.0
19 /* ================ Interrupt Number Definition …
23 /* =========================================== Core Specific Interrupt Numbers ==================…
24 …NonMaskableInt_IRQn = -14, /* -14 Non Maskable Interrupt …
25 …HardFault_IRQn = -13, /* -13 HardFault Interrupt …
26 …MemoryManagement_IRQn = -12, /* -12 Memory Management Interrupt …
27 …BusFault_IRQn = -11, /* -11 Bus Fault Interrupt …
28 …UsageFault_IRQn = -10, /* -10 Usage Fault Interrupt …
29 …SecureFault_IRQn = -9, /* -9 Secure Fault Interrupt …
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| /Zephyr-latest/soc/arm/musca/s1/ |
| D | system_cmsdk_musca_s1.h | 2 * Copyright (c) 2017-2020 Arm Limited
4 * SPDX-License-Identifier: Apache-2.0
19 /* ================ Interrupt Number Definition …
23 /* =========================================== Core Specific Interrupt Numbers ==================…
24 …NonMaskableInt_IRQn = -14, /* -14 Non Maskable Interrupt …
25 …HardFault_IRQn = -13, /* -13 HardFault Interrupt …
26 …MemoryManagement_IRQn = -12, /* -12 Memory Management Interrupt …
27 …BusFault_IRQn = -11, /* -11 Bus Fault Interrupt …
28 …UsageFault_IRQn = -10, /* -10 Usage Fault Interrupt …
29 …SecureFault_IRQn = -9, /* -9 Secure Fault Interrupt …
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| /Zephyr-latest/include/zephyr/drivers/interrupt_controller/ |
| D | intc_esp32.h | 4 * SPDX-License-Identifier: Apache-2.0
17 * Interrupt allocation flags - These flags can be used to specify
18 * which interrupt qualities the code calling esp_intr_alloc* needs.
30 #define ESP_INTR_FLAG_SHARED (1<<8) /* Interrupt can be shared between ISRs */
31 #define ESP_INTR_FLAG_EDGE (1<<9) /* Edge-triggered interrupt */
33 #define ESP_INTR_FLAG_INTRDISABLED (1<<11) /* Return with this interrupt disabled */
48 * Get the interrupt flags from the supplied priority.
54 * Check interrupt flags from input and filter unallowed values.
60 * are routed through the interrupt mux. Apart from these sources, each core also has some internal
61 * sources that do not pass through the interrupt mux. To allocate an interrupt for these sources,
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| /Zephyr-latest/boards/digilent/arty_a7/dts/bindings/ |
| D | arm,daplink-qspi-mux.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "arm,daplink-qspi-mux"
14 IRQ line connected to the level-detect non-interrupt DAPLink shield
17 mux-gpios:
18 type: phandle-array
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| /Zephyr-latest/drivers/gpio/ |
| D | gpio_pca_series.c | 4 * SPDX-License-Identifier: Apache-2.0
8 * @file Driver for PCA(L)xxxx SERIES I2C-based GPIO expander.
70 * - Type 0: PCA953X, PCA955X
71 * - Type 1: PCAL953X, PCAL955X, PCAL64XXA
72 * - Type 2: PCA957X
73 * - Type 3: PCAL65XX
103 * port-level "pin output configuration" register.
132 * @brief interrupt config for interrupt_edge register
144 uint8_t port_no; /* number of 8-pin ports on device */
162 struct gpio_dt_spec gpio_int; /** device interrupt gpio */
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| /Zephyr-latest/subsys/lorawan/nvm/ |
| D | lorawan_nvm.h | 4 * SPDX-License-Identifier: Apache-2.0
13 * @brief Hook function called when an interrupt related to NVM
18 * @param flags OR'ed flags received with the interrupt
32 * @brief Restores all the relevant LoRaWAN data from the Non-Volatile Memory.
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| /Zephyr-latest/doc/services/debugging/ |
| D | debugmon.rst | 3 Cortex-M Debug Monitor
6 Monitor mode debugging is a Cortex-M feature, that provides a non-halting approach to
7 debugging. With this it's possible to continue the execution of high-priority interrupts,
9 This strategy makes it possible to debug time-sensitive software, that would
14 It also contains a ready implementation of the interrupt, which can be used with
15 SEGGER J-Link debuggers.
23 requires an implementation of debug monitor interrupt that will be executed
26 With a SEGGER debug probe, it's possible to use a ready, SEGGER-provided implementation
27 of the interrupt.
29 * :kconfig:option:`CONFIG_SEGGER_DEBUGMON`: enables SEGGER debug monitor interrupt. Can be
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| /Zephyr-latest/boards/native/native_posix/ |
| D | cpu_wait.c | 4 * SPDX-License-Identifier: Apache-2.0
28 * programming a dedicated timer which will raise a non-maskable interrupt,
51 * Very similar to arch_busy_wait(), but if an interrupt or context switch
54 * time would be spent on interrupt handling or possible switched-in tasks.
66 * cpu_hold in interrupt handlers in posix_cpu_hold()
71 to_wait -= hwm_get_time() - time_start; in posix_cpu_hold()
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| /Zephyr-latest/boards/native/native_sim/ |
| D | cpu_wait.c | 5 * SPDX-License-Identifier: Apache-2.0
31 * programming a dedicated timer which will raise a non-maskable interrupt,
54 * Very similar to arch_busy_wait(), but if an interrupt or context switch
57 * time would be spent on interrupt handling or possible switched-in tasks.
69 * cpu_hold in interrupt handlers in posix_cpu_hold()
74 to_wait -= nsi_hws_get_time() - time_start; in posix_cpu_hold()
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| /Zephyr-latest/arch/arm/include/cortex_m/ |
| D | exception.h | 2 * Copyright (c) 2013-2014 Wind River Systems, Inc.
4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Exception/interrupt context helpers for Cortex-M CPUs
11 * Exception/interrupt context helpers.
68 * integer only stack frame or an extended floating-point stack frame.
82 /* bit[6]: Secure or Non-secure stack. Indicates whether a Secure or
83 * Non-secure stack is used to restore stack frame on exception return.
92 * IRQs and system exceptions are considered as interrupt context.
108 * - The function shall only be called from ISR context.
109 * - We do not use ARM processor state flags to determine
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| /Zephyr-latest/arch/ |
| D | Kconfig | 3 # Copyright (c) 2014-2015 Wind River Systems, Inc.
6 # SPDX-License-Identifier: Apache-2.0
18 # Should be 'select'ed by low-level symbols like SOC_SERIES_* or, lacking that,
37 # is really only necessary for Cortex-M with ARM MPU!
173 symbols above. See the top-level CMakeLists.txt.
180 module-str = arch
186 This option tells the build system that the target system is big-endian.
187 Little-endian architecture is the default and should leave this option
195 # Hidden Kconfig option representing the default little-endian architecture
196 # This is just the opposite of BIG_ENDIAN and is used for non-negative
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