Lines Matching +full:non +full:- +full:interrupt
2 * SPDX-License-Identifier: Apache-2.0
103 * 0: 16-bit address
104 * 1: 48-bit address
170 * 10: Non-posted message
182 * Interrupt GENMASK
185 * Interrupt GENMASK register for message received interrupt. When set to 1 interrupt
186 * is not generated to DSP Core. GENMASK does not affect interrupt status bit.
194 * Message received interrupt status register. Set by HW when message is received,
227 * Completion data received for upstream non-posted read.
237 * Completion SAI received for upstream non-posted message.
251 * Completion status received for upstream non-posted message
267 * Completion EH present indication received for upstream non-posted message.
278 * Interrupt GENMASK
281 * Interrupt GENMASK register for completion received interrupt. When set to 1
282 * interrupt is not generated to DSP Core. GENMASK does not affect interrupt status
309 * This is OR of posted SM and non-posted SM busy signals.
317 * Upstream message sent interrupt status. Set by HW when upstream message has been
343 * hardware if opcode is 0x20 - 0x2F.
362 * 0: Transaction will be non-posted
368 * Interrupt Enable
371 * Interrupt enable register for message sent interrupt. When cleared to 0 interrupt
372 * is not generated to DSP Core. Enable does not affect interrupt status bit.
421 * 0: 16-bit address
422 * 1: 48-bit address
542 * Completion data to be sent for downstream non-posted read.
556 * Completion status to be sent for downstream non-posted message.
574 * SB completion transaction if original downstream request is non-posted. If
590 * Completion SAI to be sent for downstream non-posted message. Reset value is
634 * 0-based value.
655 * 0: Clk is un-gated
694 * Note: boot prep handling is an artifact of re-using the component from ISH. There is no usage
720 * Note: boot prep handling is an artifact of re-using the component from ISH. There is no usage
804 * @brief Interrupt enable / disable for message sent interrupt.
806 * @param enable Interrupt state
837 * @brief Clear message send interrupt status