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/Zephyr-latest/dts/bindings/pcie/host/
Dpci-host-ecam-generic.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "pci-host-ecam-generic"
8 include: pcie-controller.yaml
14 msi-parent:
21 As described in IEEE Std 1275-1994, but must provide at least a
22 definition of non-prefetchable memory. One or both of prefetchable Memory
25 interrupt-map-mask:
28 interrupt-map:
31 bus-range:
/Zephyr-latest/dts/arm64/qemu/
Dqemu-virt-arm64.dtsi4 * SPDX-License-Identifier: Apache-2.0
10 * qemu-system-aarch64 -machine virt,gic-version=host,accel=kvm
11 * -cpu cortex-a53 -nographic -machine dumpdtb=virt.dtb
13 * dtc -I dtb -O dts virt.dtb
17 #include <arm64/armv8-a.dtsi>
18 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
19 #include <zephyr/dt-bindings/pcie/pcie.h>
22 #address-cells = <2>;
23 #size-cells = <2>;
26 #address-cells = <1>;
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Dqemu-virt-a53.dtsi4 * SPDX-License-Identifier: Apache-2.0
10 * qemu-system-aarch64 -machine virt -cpu cortex-a53 -nographic
11 * -machine dumpdtb=virt.dtb
13 * dtc -I dtb -O dts virt.dtb
17 #include <arm64/armv8-a.dtsi>
18 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
19 #include <zephyr/dt-bindings/pcie/pcie.h>
22 #address-cells = <2>;
23 #size-cells = <2>;
26 #address-cells = <1>;
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/Zephyr-latest/dts/arm64/intel/
Dintel_socfpga_agilex5.dtsi2 * SPDX-License-Identifier: Apache-2.0
8 #include <arm64/armv8-a.dtsi>
9 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
10 #include <zephyr/dt-bindings/reset/intel_socfpga_reset.h>
11 #include <zephyr/dt-bindings/clock/intel_socfpga_clock.h>
16 #address-cells = <1>;
17 #size-cells= <0>;
21 compatible = "arm,cortex-a55";
22 enable-method = "psci";
28 compatible = "arm,cortex-a55";
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/Zephyr-latest/boards/arm/fvp_base_revc_2xaemv8a/
Dfvp_base_revc_2xaemv8a.dts3 * SPDX-License-Identifier: Apache-2.0
6 /dts-v1/;
9 #include <arm64/armv8-a.dtsi>
10 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
23 zephyr,shell-uart = &uart0;
27 compatible = "arm,psci-0.2";
32 #address-cells = <1>;
33 #size-cells = <0>;
37 compatible = "arm,cortex-a53";
43 compatible = "arm,cortex-a53";
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/Zephyr-latest/dts/arm/st/wl/
Dstm32wl.dtsi2 * Copyright (c) 2020-2024 STMicroelectronics
4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/clock/stm32wl_clock.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/lora/sx126x.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include <zephyr/dt-bindings/adc/adc.h>
14 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
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/Zephyr-latest/doc/releases/
Drelease-notes-2.0.rst12 * The kernel now supports both 32- and 64-bit architectures.
17 * We added support for :ref:`Point-to-Point Protocol (PPP) <ppp>`. PPP is a
20 * We added support for UpdateHub, an end-to-end solution for large scale
21 over-the-air device updates.
22 * We added support for ARM Cortex-R Architecture (Experimental).
32 * Fixes CVE-2019-9506: The Bluetooth BR/EDR specification up to and
35 negotiation. This allows practical brute-force attacks (aka "KNOB")
42 * New kernel API for per-thread disabling of Floating Point Services for
43 ARC, ARM Cortex-M, and x86 architectures.
45 * Additional support for compatibility with 64-bit architectures.
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Drelease-notes-3.3.rst14 * Introduced :ref:`USB-C <usbc_api>` device stack with PD (power delivery)
17 CMSIS-DSP as the default backend.
30 * CVE-2023-0359: Under embargo until 2023-04-20
32 * CVE-2023-0779: Under embargo until 2023-04-22
66 removed in favor of new :dtcompatible:`zephyr,flash-disk` devicetree binding.
71 * Starting from this release ``zephyr-`` prefixed tags won't be created
82 image states). Use of a truncated hash or non-sha256 hash will still work
88 registration function at boot-up. If applications register this then
93 application code, these will now automatically be registered at boot-up (this
129 This may cause out-of-tree scripts or commands to fail if they have relied
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