Lines Matching +full:msi +full:- +full:parent
4 * SPDX-License-Identifier: Apache-2.0
10 * qemu-system-aarch64 -machine virt,gic-version=host,accel=kvm
11 * -cpu cortex-a53 -nographic -machine dumpdtb=virt.dtb
13 * dtc -I dtb -O dts virt.dtb
17 #include <arm64/armv8-a.dtsi>
18 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
19 #include <zephyr/dt-bindings/pcie/pcie.h>
22 #address-cells = <2>;
23 #size-cells = <2>;
26 #address-cells = <1>;
27 #size-cells = <0>;
31 compatible = "arm,cortex-virt";
37 compatible = "arm,cortex-virt";
43 compatible = "arm,armv8-timer";
44 interrupt-parent = <&gic>;
55 uartclk: apb-pclk {
56 compatible = "fixed-clock";
57 clock-frequency = <24000000>;
58 #clock-cells = <0>;
62 #address-cells = <2>;
63 #size-cells = <2>;
66 interrupt-parent = <&gic>;
68 gic: interrupt-controller@8000000 {
69 compatible = "arm,gic-v3", "arm,gic";
72 interrupt-controller;
73 #interrupt-cells = <4>;
75 #size-cells = <0x02>;
76 #address-cells = <0x02>;
79 compatible = "arm,gic-v3-its";
81 msi-controller;
90 interrupt-names = "irq_0";
95 compatible = "cfi-flash";
96 bank-width = <4>;
105 compatible = "pci-host-ecam-generic";
108 #size-cells = <0x02>;
109 #address-cells = <0x03>;
113 #interrupt-cells = <0x01>;
114 interrupt-map-mask = <0x1800 0x00 0x00 0x07>;
115 interrupt-map = <0x00 0x00 0x00 1 &gic 0 0 GIC_SPI
150 msi-parent = <&its>;
151 bus-range = <0x00 0xff>;