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/Zephyr-latest/soc/nordic/common/
Dmram_latency.h8 * nRF SoC specific public APIs for MRAM latency management
24 /** @brief Request MRAM operations without latency.
27 * an operation to request the MRAM low latency. If initiation of the
37 * with the MRAM latency service.
38 * @retval -EIO if MRAM latency service returned error.
44 /** @brief Request MRAM operations without latency.
50 * @retval -EIO if MRAM latency service returned error.
56 * @brief Safely cancel a request for MRAM operations without latency.
72 * @retval -EIO if MRAM latency service returned error.
78 * @brief Release a request for MRAM operations without latency.
[all …]
DKconfig15 bool "MRAM latency manager"
29 bool "Request MRAM without latency at start"
31 When enabled then MRAM configuration without latency is requested
/Zephyr-latest/drivers/flash/
DKconfig.nrf_mram8 bool "Nordic Semiconductor flash driver for MRAM"
16 Enables Nordic Semiconductor flash driver for MRAM in direct write mode.
18 Note that MRAM words are auto-erased when written to, but writing to a
DKconfig.ambiq5 bool "Ambiq flash driver on MRAM or flash"
14 Enables Ambiq flash driver on MRAM (e.g. Apollo4x) or
Dsoc_flash_nrf_mram.c28 BUILD_ASSERT(MRAM_START > 0, "nordic,mram: start address expected to be non-zero");
35 * @param[in] must_align Require MRAM word alignment, if applicable.
37 * @return Absolute address in MRAM, or NULL if @p offset or @p len are not
59 * @param[in] addr_end Last modified MRAM address (not inclusive).
67 /* Our last operation was MRAM word-aligned, so we're done. in commit_changes()
74 /* Get the most significant byte (MSB) of the last MRAM word we were modifying. in commit_changes()
75 * Writing to this byte makes the MRAM controller commit other pending writes to that word. in commit_changes()
/Zephyr-latest/dts/bindings/mtd/
Dnordic,mram.yaml4 description: Nordic MRAM
6 compatible: nordic,mram
Dnordic,owned-partitions.yaml20 mram1x: mram@e000000 {
21 compatible = "nordic,mram";
/Zephyr-latest/drivers/can/
Dcan_sam.c23 mem_addr_t mram; member
52 return can_mcan_sys_read_mram(sam_config->mram, offset, dst, len); in can_sam_read_mram()
61 return can_mcan_sys_write_mram(sam_config->mram, offset, src, len); in can_sam_write_mram()
69 return can_mcan_sys_clear_mram(sam_config->mram, offset, len); in can_sam_clear_mram()
106 uint32_t mrba = sam_cfg->mram & 0xFFFF0000; in can_sam_init()
111 ret = can_mcan_configure_mram(dev, mrba, sam_cfg->mram); in can_sam_init()
179 .mram = (mem_addr_t)POINTER_TO_UINT(&can_sam_mram_##inst), \
Dcan_nrf.c29 uint32_t mram; member
106 return can_mcan_sys_read_mram(config->mram, offset, dst, len); in can_nrf_read_mram()
115 return can_mcan_sys_write_mram(config->mram, offset, src, len); in can_nrf_write_mram()
123 return can_mcan_sys_clear_mram(config->mram, offset, len); in can_nrf_clear_mram()
161 ret = can_mcan_configure_mram(dev, config->mrba, config->mram); in can_nrf_init()
188 .mram = CAN_MCAN_DT_INST_MRAM_ADDR(n), \
Dcan_mcux_mcan.c26 mem_addr_t mram; member
55 return can_mcan_sys_read_mram(mcux_config->mram, offset, dst, len); in mcux_mcan_read_mram()
64 return can_mcan_sys_write_mram(mcux_config->mram, offset, src, len); in mcux_mcan_write_mram()
72 return can_mcan_sys_clear_mram(mcux_config->mram, offset, len); in mcux_mcan_clear_mram()
88 const uintptr_t mrba = mcux_config->mram & MCUX_MCAN_MRBA_BA; in mcux_mcan_init()
122 err = can_mcan_configure_mram(dev, mrba, mcux_config->mram); in mcux_mcan_init()
206 .mram = (mem_addr_t)POINTER_TO_UINT(&mcux_mcan_mram_##n), \
Dcan_sam0.c24 mem_addr_t mram; member
68 return can_mcan_sys_read_mram(sam_config->mram, offset, dst, len); in can_sam0_read_mram()
77 return can_mcan_sys_write_mram(sam_config->mram, offset, src, len); in can_sam0_write_mram()
85 return can_mcan_sys_clear_mram(sam_config->mram, offset, len); in can_sam0_clear_mram()
147 ret = can_mcan_configure_mram(dev, 0U, sam_cfg->mram); in can_sam0_init()
213 .mram = (mem_addr_t)POINTER_TO_UINT(&can_sam0_mram_##inst), \
Dcan_numaker.c35 mem_addr_t mram; member
115 rc = can_mcan_configure_mram(dev, config->mrba, config->mram); in can_numaker_init_unlocked()
209 return can_mcan_sys_read_mram(numaker_cfg->mram, offset, dst, len); in can_numaker_read_mram()
218 return can_mcan_sys_write_mram(numaker_cfg->mram, offset, src, len); in can_numaker_write_mram()
226 return can_mcan_sys_clear_mram(numaker_cfg->mram, offset, len); in can_numaker_clear_mram()
268 .mram = CAN_MCAN_DT_INST_MRAM_ADDR(inst), \
Dcan_stm32h7_fdcan.c36 mem_addr_t mram; member
65 return can_mcan_sys_read_mram(stm32h7_cfg->mram, offset, dst, len); in can_stm32h7_read_mram()
74 return can_mcan_sys_write_mram(stm32h7_cfg->mram, offset, src, len); in can_stm32h7_write_mram()
82 return can_mcan_sys_clear_mram(stm32h7_cfg->mram, offset, len); in can_stm32h7_clear_mram()
182 ret = can_mcan_configure_mram(dev, stm32h7_cfg->mrba, stm32h7_cfg->mram); in can_stm32h7_init()
258 .mram = CAN_MCAN_DT_INST_MRAM_ADDR(n), \
/Zephyr-latest/dts/arm/atmel/
Dsame5x.dtsi41 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
54 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
Dsamc21.dtsi60 bosch,mram-cfg = <0x0 28 8 3 3 0 1 1>;
73 bosch,mram-cfg = <0x0 28 8 3 3 0 1 1>;
/Zephyr-latest/boards/nordic/nrf9280pdk/
Dnrf9280pdk_nrf9280_cpuppr_xip.yaml5 name: nRF9280-DK-nRF9280-PPR (MRAM XIP)
/Zephyr-latest/boards/nordic/nrf54h20dk/
Dnrf54h20dk_nrf54h20_cpuflpr_xip_0_9_0.yaml5 name: nRF54H20-DK-nRF54H20-FLPR (MRAM XIP) (revision 0.9.0)
Dnrf54h20dk_nrf54h20_cpuppr_xip_0_9_0.yaml5 name: nRF54H20-DK-nRF54H20-PPR (MRAM XIP) (revision 0.9.0)
/Zephyr-latest/snippets/nordic-ppr-xip/
DREADME.rst10 (Peripheral Processor) from another core. PPR code is to be executed from MRAM,
/Zephyr-latest/boards/shields/tcan4550evm/
Dtcan4550evm.overlay30 bosch,mram-cfg = <0x0 15 15 7 7 0 10 10>;
/Zephyr-latest/dts/bindings/can/
Dbosch,m_can-base.yaml6 bosch,mram-cfg:
Dti,tcan4x5x.yaml18 bosch,mram-cfg = <0x0 15 15 5 5 0 10 10>;
/Zephyr-latest/modules/hal_nordic/nrfs/
DKconfig82 bool "MRAM latency service"
/Zephyr-latest/boards/arm/v2m_musca_s1/
Dv2m_musca_s1_musca_s1_ns.dts44 mram0: mram@a080000 {
/Zephyr-latest/dts/arm/st/g0/
Dstm32g0b1.dtsi42 bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>;
53 bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>;

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