Home
last modified time | relevance | path

Searched full:master (Results 1 – 25 of 574) sorted by relevance

12345678910>>...23

/Zephyr-latest/dts/bindings/misc/
Dnxp,s32-emios.yaml8 as a reference timebase (master bus) for other channels.
42 Node for eMIOS master bus. Each channel is capable to become a master bus has
44 the master bus, the devicetree node should be enabled and dts properties
66 Channel identifier for the master bus.
72 A channel mask for channels that by hardware design can use this master bus
73 as timebase for the operation, lsb is channel 0. The mask bit for this master bus
74 must always 0 because a master bus should not do other thing than a base timer.
88 Master bus type.
101 Master bus mode.
/Zephyr-latest/samples/subsys/ipc/rpmsg_service/
DREADME.rst51 serial port, one is master another is remote:
58 RPMsg Service [master] demo started
59 Master core received a message: 1
60 Master core received a message: 3
61 Master core received a message: 5
63 Master core received a message: 99
102 and network core images, the following messages (one for master and one for
110 RPMsg Service [master] demo started
111 Master core received a message: 1
112 Master core received a message: 3
[all …]
/Zephyr-latest/dts/xtensa/nxp/
Dnxp_imx8qxp.dtsi19 compatible = "nxp,irqsteer-master";
27 compatible = "nxp,irqsteer-master";
35 compatible = "nxp,irqsteer-master";
43 compatible = "nxp,irqsteer-master";
51 compatible = "nxp,irqsteer-master";
59 compatible = "nxp,irqsteer-master";
67 compatible = "nxp,irqsteer-master";
75 compatible = "nxp,irqsteer-master";
Dnxp_imx8qm.dtsi20 compatible = "nxp,irqsteer-master";
28 compatible = "nxp,irqsteer-master";
36 compatible = "nxp,irqsteer-master";
44 compatible = "nxp,irqsteer-master";
52 compatible = "nxp,irqsteer-master";
60 compatible = "nxp,irqsteer-master";
68 compatible = "nxp,irqsteer-master";
76 compatible = "nxp,irqsteer-master";
/Zephyr-latest/subsys/net/l2/ethernet/gptp/
Dgptp_data_set.h106 * This is used when determining the Grand Master.
176 /** Last Grand Master Frequency Change. */
182 /** Last Grand Master Frequency Change. */
188 /** Last Grand Master Phase Change. */
191 /** Last Grand Master Phase Change. */
203 /** Grand Master priority vector. */
206 /** Previous Grand Master priority vector. */
218 /** Grand Master Time Base Indicator. */
227 /** Steps removed from selected master. */
251 /** A Grand Master is present in the domain. */
[all …]
/Zephyr-latest/drivers/dai/nxp/sai/
DKconfig.sai19 of the master clock. Master clock configuration
20 refers to enabling/disabling the master clock,
22 the master clock output.
37 the SAI is FSYNC/BCLK master, one of the directions
/Zephyr-latest/doc/contribute/coding_guidelines/
Dindex.rst37 …- `Dir 1.1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_01_01.c>`_
44 …- `Dir 2.1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_02_01.c>`_
51 …- `Dir 3.1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_03_01.c>`_
58 …- `Dir 4.1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_04_01.c>`_
65 …- `Dir 4.2 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_04_02.c>`_
72 …- `Dir 4.4 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_04_04.c>`_
79 …- `Dir 4.5 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_04_05.c>`_
86 …- `Dir 4.6 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_04_06.c>`_
93 …- `Dir 4.7 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_04_07.c>`_
100 …example 1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_04_08_1.c>`_
[all …]
/Zephyr-latest/soc/intel/apollo_lake/doc/
Dsupported_features.txt19 configuration. The UARTs are fed a master clock which is fed into a PLL which
20 in turn outputs the baud master clock. The PLL is controlled by a per-UART
30 The resulting baud master clock frequency is ``(n/m)`` * master.
32 Typically, the master clock is 100MHz, and the firmware by default sets
34 results in the de-facto standard 1.8432MHz master clock and a max baud rate
36 Zephyr what the resulting master clock is.
56 and ``clock-frequency`` (the resulting baud master clock). The meaning of
/Zephyr-latest/samples/drivers/i2c/custom_target/src/
Dmain.c15 * @brief Callback which is called when a write request is received from the master.
25 * @brief Callback which is called when a write is received from the master.
27 * @param val The byte received from the master.
37 * @brief Callback which is called when a read request is received from the master.
39 * @param val Pointer to the byte to be sent to the master.
49 * @brief Callback which is called when a read is processed from the master.
51 * @param val Pointer to the next byte to be sent to the master.
61 * @brief Callback which is called when the master sends a stop condition.
/Zephyr-latest/drivers/w1/
DKconfig.ds24851 # Configuration options for the Zephyr DS2485 1-Wire master driver
7 bool "DS2485 1-wire master driver"
13 Enable the ds2485 w1 master driver.
DKconfig.max325 bool "MAX32xxx MCUs 1-Wire master driver"
10 This option enables the 1-Wire master driver for MAX32xxx MCUs
/Zephyr-latest/soc/nxp/lpc/lpc54xxx/gcc/
Dstartup_LPC54114_cm4.S34 * Determine if the core executing this code is the master or
58 mov r4, r5 /* Set flag for master core (1) */
60 /* Determine if M4 core is the master or slave */
66 ands r3, r3, r5 /* r3 = (Bit 0: 1 = M4 is master, 0 = M4 is slave) */
68 /* Select boot based on selected master core and core ID */
71 eors r3, r3, r4 /* r4 = (Bit 0: 0 = master, 1 = slave) */
93 /* Slave isn't yet setup for system boot from the master */
94 /* so sleep until the master sets it up and then reboots it */
98 wfi /* Sleep forever until master reboots */
/Zephyr-latest/dts/bindings/pwm/
Dnxp,s32-emios-pwm.yaml8 require to use a reference timebase from a master bus.
25 master-bus = <&emios1_bus_a>;
32 master-bus = <&emios1_bus_b>;
45 OPWMB and OPWMCB modes use reference timebase, the master bus is chosen over
46 phandle 'master-bus'. Please notice that the devicetree node for master bus
79 master-bus:
82 A phandle to master-bus node that will be used as external timebase
84 for PWM operation. A master bus must be used exclusively, such as if
86 master bus as a timebase for generate PWM pulse.
/Zephyr-latest/dts/bindings/ethernet/
Dnxp,tja1103.yaml20 master-slave:
24 100BASE-T1 Specifies that either phy has to run in master / slave mode
28 - "master"
/Zephyr-latest/include/zephyr/net/
Ddsa.h47 * master.
53 * - 0 if ok (packet sent via master iface), < 0 if error
86 * @param iface Network interface (master)
94 * @brief Pointer to master interface send function
99 * @brief DSA helper function to register transmit function for master
101 * @param iface Network interface (master)
102 * @param fn Pointer to master interface send method
110 * @brief DSA helper function to check if port is master
112 * @param iface Network interface (master)
131 /** Pointer to DSA master network interface */
[all …]
/Zephyr-latest/dts/bindings/w1/
Dzephyr,w1-serial.yaml4 # Properties for the serial 1-Wire master driver:
11 description: 1-Wire master over Zephyr uart
15 include: [uart-device.yaml, w1-master.yaml]
Dmaxim,ds2485.yaml4 # Properties for the DS2485 I2C 1-Wire master with memory driver:
7 This is a representation of the Maxim DS2485 I2C 1-Wire master w/ memory
Dmaxim,ds2482-800-channel.yaml4 description: DS4282-800, 8-Channel 1-Wire Master (Channel driver)
8 include: [w1-master.yaml]
/Zephyr-latest/dts/bindings/spi/
Dnordic,nrf-spi-common.yaml44 Optional bi-directional line that allows SPI master to indicate to SPI
51 master keeps the line in the low state
52 - when a transfer is to be performed, SPI master configures its WAKE
59 to SPI master that it can proceed with the transfer
61 and SPI master again keeps the line in the low state
/Zephyr-latest/dts/bindings/qspi/
Dnxp,s32-qspi-sfp-frad.yaml18 master-domain-acp-policy:
22 Selects the master domain access control policy, defined in dt-bindings/qspi/nxp-s32-qspi.h:
43 exclusive access owner master and disabling write permissions for other masters.
51 The domain master ID that owns the exclusive access lock.
/Zephyr-latest/drivers/i2c/
Di2c_rcar.c39 #define RCAR_I2C_ICMCR 0x04 /* Master Control Register */
41 #define RCAR_I2C_ICMIER 0x14 /* Master IRQ Enable */
43 #define RCAR_I2C_ICMSR 0x0c /* Master Status */
46 #define RCAR_I2C_ICMAR 0x20 /* Master Address Register */
51 #define RCAR_I2C_ICMCR_MDBS BIT(7) /* Master Data Buffer Select */
55 #define RCAR_I2C_ICMCR_MIE BIT(3) /* Master Interface Enable */
62 #define RCAR_I2C_MNR BIT(6) /* Master Nack Received */
63 #define RCAR_I2C_MAL BIT(5) /* Master Arbitration lost */
64 #define RCAR_I2C_MST BIT(4) /* Master Stop Transmitted */
65 #define RCAR_I2C_MDE BIT(3) /* Master Data Empty */
[all …]
/Zephyr-latest/dts/bindings/test/
Dvnd,w1.yaml4 description: Test W1 bus master node
8 include: [w1-master.yaml]
/Zephyr-latest/dts/bindings/interrupt-controller/
Dnxp,irqsteer-master.yaml1 description: i.MX IRQ_STEER master
3 compatible: "nxp,irqsteer-master"
/Zephyr-latest/soc/atmel/sam/sam4e/
Dsoc.c28 * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot.
36 /* Switch MCK (Master Clock) to the main clock */ in clock_init()
61 * Set FWS (Flash Wait State) value before increasing Master Clock in clock_init()
77 * Final setup of the Master Clock in clock_init()
83 /* Select PLL as Master Clock source. */ in clock_init()
/Zephyr-latest/drivers/spi/
DKconfig.esp327 bool "ESP32 SPI Master driver"
11 Enables support for ESP32 SPI Master driver.

12345678910>>...23