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/Zephyr-latest/dts/bindings/clock/
Dmicrochip,xec-pcr.yaml23 default value is 480 for 100 kHz.
28 description: 32 KHz clock source for PLL
33 description: 32 KHz clock source for peripherals
43 32KHz clock monitor minimum valid 32KHz period in 48MHz units
49 32KHz clock monitor maximum valid 32KHz period in 48MHz units
56 the measured 32KHz high and low pulse widths.
62 Minimum number of consecutive 32KHz pulses that pass all monitor tests
86 If the internal silicon 32KHz oscillator is not chosen as the source
87 for PLL and Periheral devices then disable the internal 32KHz
Dst,stm32u5-msi-clock.yaml33 - 11 # range 11 around 768 KHz
34 - 12 # range 12 around 400 KHz
35 - 13 # range 13 around 200 KHz
36 - 14 # range 14 around 133 KHz
37 - 15 # range 14 around 100 KHz
Dst,stm32l0-msi-clock.yaml21 - 0 # range 0, around 65.536 kHz
22 - 1 # range 1, around 131.072 kHz
23 - 2 # range 2, around 262.144 kHz
24 - 3 # range 3, around 524.288 kHz
Dst,stm32-msi-clock.yaml18 - 0 # range 0 around 100 kHz
19 - 1 # range 1 around 200 kHz
20 - 2 # range 2 around 400 kHz
21 - 3 # range 3 around 800 kHz
Despressif,esp32-rtc.yaml31 - 0: ESP32_RTC_SLOW_CLK_SRC_RC_SLOW - 136 KHz (C3/S3) - 90 kHz (S2) - 150 kHz (ESP32)
32 - 1: ESP32_RTC_SLOW_CLK_SRC_XTAL32K - 32,768U KHz
/Zephyr-latest/samples/drivers/clock_control_xec/
DREADME.rst9 This sample demonstrates configuring the 32KHz clock
22 Internal Silicon 32KHz Oscillator jumper configuration
28 Dual-ended 32KHz Crystal jumper configuration
36 Remove jumper on JP121 to prevent U15 32KHz 50% duty waveform
39 External single-ended 32KHz waveform to MEC172x XTAL2 input
43 Jumper on JP2 1-2 connect external 32KHz signal to XTAL2
47 Jumper on JP121 pins 3-4 connect U15 32KHz output to
50 External single-ended 32KHz waveform to MEC172x 32KHZ_IN pin
58 Jumper on JP121 pins 1-2 connect U15 32KHz output to
/Zephyr-latest/dts/bindings/pwm/
Dmicrochip,xec-pwmbbled.yaml31 Clock source selection: 32 KHz is available in deep sleep.
33 - PWM_BBLED_CLK_32K: Clock source is the 32KHz domain
52 - 32KHz Core clock (32.768KHz)
54 PCR(Power, Clock and Reset) block. But 32KHz Core clock will be available to BBLED.
56 Property "enable-low-power-32k" shall be used along with 32KHz clock to blink (or) not blink
/Zephyr-latest/soc/atmel/sam0/common/
DKconfig.samd5x7 bool "The external 32 kHz crystal oscillator"
9 Say y to enable the external 32 kHZ crystal oscillator at
15 hex "Startup time external 32 kHz crystal oscillator"
19 Selects the startup time for the external 32 kHz crystal oscillator.
DKconfig.samd2x13 bool "Internal 32.768 kHz RC oscillator"
15 Enable the internal 32.768 kHz RC oscillator at startup.
25 bool "External 32.768 kHz clock source"
27 Enable the external 32.768 kHz clock source at startup.
31 bool "External 32.768 kHz clock is a crystal oscillator"
DKconfig.saml2x19 bool "Internal 32.768 kHz RC oscillator"
21 Eable the internal 32.768 kHz RC oscillator at startup.
25 bool "External 32.768 kHz clock source"
27 Enable the external 32.768 kHz cloud source at startup.
31 bool "External 32.768 kHz clock is a crystal oscillator"
/Zephyr-latest/samples/drivers/clock_control_xec/src/
Dmain.c48 LOG_INF("32KHz clock source is XTAL"); in vbat_clock_regs()
51 " (external 32KHz waveform)"); in vbat_clock_regs()
57 LOG_INF("32KHz clock source is the Internal Silicon 32KHz OSC"); in vbat_clock_regs()
60 LOG_INF("32KHz clock domain uses the 32KHZ_IN pin(GPIO_0165 F1)"); in vbat_clock_regs()
62 LOG_INF("32KHz clock domain uses the 32KHz clock source"); in vbat_clock_regs()
65 LOG_INF("32KHz trim = 0x%08x", vbr->CKK32_TRIM); in vbat_clock_regs()
135 LOG_INF("PCR 32KHz Clock Monitor Pulse High Count register = 0x%x", r); in pcr_clock_regs()
138 LOG_INF("PCR 32KHz Clock Monitor Period Maximum Count register = 0x%x", r); in pcr_clock_regs()
141 LOG_INF("PCR 32KHz Clock Monitor Duty Cycle Variation register = 0x%x", r); in pcr_clock_regs()
144 LOG_INF("PCR 32KHz Clock Monitor Duty Cycle Variation Max register = 0x%x", r); in pcr_clock_regs()
[all …]
/Zephyr-latest/dts/bindings/adc/
Dtelink,b91-adc.yaml25 This property selects the ADC source frequency: 23 kHz, 48 kHz, or 96 kHz.
Drenesas,smartbond-sdadc.yaml25 - 0 # 250 kHz
26 - 1 # 500 kHz
/Zephyr-latest/dts/bindings/timer/
Dambiq,stimer.yaml25 2 - HFRC_DIV256 : 187.5KHz from the HFRC clock divider.
29 6 - LFRC_DIV1 : Approximately 1KHz from the LFRC oscillator (uncalibrated).
35 2 - HFRC_375KHZ : 375KHz from the HFRC clock divider.
39 6 - LFRC_1KHZ : Approximately 1KHz from the LFRC oscillator (uncalibrated).
Dmicrochip,mec5-ktimer.yaml6 the 32kHz 32-bit RTOS timer with 32-bit basic timer 5.
23 description: RTOS timer runs at fixed 32 KHz.
/Zephyr-latest/drivers/audio/
Dwm8904.h143 kWM8904_SampleRate8kHz = 0x0, /*!< 8 kHz */
144 kWM8904_SampleRate12kHz = 0x1, /*!< 12kHz */
145 kWM8904_SampleRate16kHz = 0x2, /*!< 16kHz */
146 kWM8904_SampleRate24kHz = 0x3, /*!< 24kHz */
147 kWM8904_SampleRate32kHz = 0x4, /*!< 32kHz */
148 kWM8904_SampleRate48kHz = 0x5, /*!< 48kHz */
149 kWM8904_SampleRate11025Hz = 0x6, /*!< 11.025kHz */
150 kWM8904_SampleRate22050Hz = 0x7, /*!< 22.05kHz */
151 kWM8904_SampleRate44100Hz = 0x8 /*!< 44.1kHz */
/Zephyr-latest/drivers/crypto/
DKconfig.ataes132a23 Standard bis speed of up to 100KHz.
28 Fast bus speed of up to 400KHz.
/Zephyr-latest/drivers/clock_control/
Dclock_control_mchp_xec.c30 * 32KHz period counter minimum for pass/fail: 16-bit
31 * 32KHz period counter maximum for pass/fail: 16-bit
32 * 32KHz duty cycle variation max for pass/fail: 16-bit
33 * 32KHz valid count minimum: 8-bit
37 * One 32KHz clock pulse = 1464.84 48 MHz counts.
156 #define XEC_CC_VBATR_CS_XTAL_SE BIT(9) /* crystal XTAL2 used as 32KHz input */
162 /* MEC172x Select source of peripheral 32KHz clock */
190 uint16_t period_min; /* mix and max 32KHz period range */
193 uint8_t xtal_se; /* External 32KHz square wave on XTAL2 pin */
194 uint8_t max_dc_va; /* 32KHz monitor maximum duty cycle variation */
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dmchp_xec_pcr.h10 /* PLL 32KHz clock source VTR rail ON. */
15 /* Peripheral 32KHz clock source for VTR rail ON and off(VBAT operation) */
/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_pcr.h117 /* PCR Slow Clock Control. Clock divider for 100KHz clock domain */
276 /* VTR Source 32 KHz Clock (Offset +8Ch) */
284 * Clock monitor 32KHz period counter (Offset +C0h, RO)
285 * Clock monitor 32KHz high counter (Offset +C4h, RO)
286 * Clock monitor 32KHz period counter minimum (Offset +C8h, RW)
287 * Clock monitor 32KHz period counter maximum (Offset +CCh, RW)
288 * Clock monitor 32KHz Duty Cycle variation counter (Offset +D0h, RO)
289 * Clock monitor 32KHz Duty Cycle variation counter maximum (Offset +D4h, RW)
294 * Clock monitor 32KHz Valid Count (Offset +0xD8, RO)
295 * Clock monitor 32KHz Valid Count minimum (Offset +0xDC, RW)
[all …]
/Zephyr-latest/boards/st/stm32g081b_eval/
Dstm32g081b_eval.dts170 * +-------+ @ 16 MHz +-------+ @ ~600 kHz +-----------+
177 * 1. hbit_clk ~= 600 kHz: 16 MHz / 600 kHz = 26.67
181 * hbit_clk = HSI_clk / 27 = 592.6 kHz = 1.687 uSec period
201 * +-------+ @ 16 MHz +-------+ @ ~600 kHz +-----------+
208 * 1. hbit_clk ~= 600 kHz: 16 MHz / 600 kHz = 26.67
212 * hbit_clk = HSI_clk / 27 = 592.6 kHz = 1.687 uSec period
/Zephyr-latest/dts/bindings/espi/
Dmicrochip,xec-espi-saf.yaml22 description: poll flash busy timeout in 32KHz periods
38 description: force suspended erase or program to resume in 32KHz periods
/Zephyr-latest/dts/bindings/rtc/
Dnxp,irtc.yaml24 0 <- 16.384 kHz
25 1 <- 32.768 kHz
/Zephyr-latest/dts/bindings/led_strip/
Dworldsemi,ws2812-rpi_pico-pio.yaml39 For example, T0=3, T1=3, T2=4 and the frequency is 800kHz case,
41 (1 / 800kHz) * (3/10) = 375ns
43 (1 / 800kHz) * ((4+3)/10) = 875ns
/Zephyr-latest/dts/bindings/watchdog/
Dgd,gd32-fwdgt.yaml30 the low-speed internal RC oscillator frequency is 32kHz or 40kHz.

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