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/Zephyr-latest/dts/bindings/serial/
Dns16550.yaml5 include: [uart-controller.yaml, pcie-device.yaml, pinctrl-device.yaml, reset-device.yaml]
8 reg-shift:
21 io-mapped:
23 description: specify registers are IO mapped or memory mapped
/Zephyr-latest/dts/bindings/adc/
Dinfineon,cat1-adc.yaml4 # SPDX-License-Identifier: Apache-2.0
9 manual (Section Port I/O functions) for the group/channel mapping to a specific port-pin on
10 the board. For example on the cy8cproto_062_4343w P10.0 is mapped to adc0,channel0 and
11 P10.1 is mapped to adc0,channel1.
13 compatible: "infineon,cat1-adc"
15 include: adc-controller.yaml
24 "#io-channel-cells":
27 io-channel-cells:
28 - input
Dinfineon,xmc4xxx-adc.yaml2 # SPDX-License-Identifier: Apache-2.0
7 (Section Port I/O functions) for the group/channel mapping to a specific port-pin on the board.
8 For example on the xmc45_relax_kit P14.0 is mapped to adc0,channel0 and P14.1 is mapped to
11 compatible: "infineon,xmc4xxx-adc"
13 include: adc-controller.yaml
22 vref-internal-mv:
28 "#io-channel-cells":
31 io-channel-cells:
32 - input
/Zephyr-latest/dts/x86/intel/
Datom.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
12 #address-cells = <1>;
13 #size-cells = <0>;
17 d-cache-line-size = <64>;
25 #address-cells = <1>;
26 #interrupt-cells = <3>;
28 interrupt-controller;
34 interrupt-controller;
35 #interrupt-cells = <3>;
[all …]
Draptor_lake_s.dtsi3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
8 #include <zephyr/dt-bindings/i2c/i2c.h>
9 #include <zephyr/dt-bindings/pcie/pcie.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "intel,raptor-lake", "intel,x86_64";
20 d-cache-line-size = <64>;
33 #address-cells = <1>;
[all …]
Dalder_lake.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/pcie/pcie.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "intel,alder-lake", "intel,x86_64";
22 d-cache-line-size = <64>;
28 compatible = "intel,alder-lake", "intel,x86_64";
[all …]
/Zephyr-latest/dts/arc/synopsys/
Darc_iot.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
24 intc: arcv2-intc {
25 compatible = "snps,arcv2-intc";
26 interrupt-controller;
27 #interrupt-cells = <2>;
31 compatible = "snps,arc-timer";
[all …]
/Zephyr-latest/dts/bindings/espi/
Dmicrochip,xec-espi-host-dev.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "microchip,xec-espi-host-dev"
10 on-bus: espi
30 host-io:
37 host-io-addr-mask:
42 alias address is mapped to in the 80h to 83h I/O range.
44 host-mem:
51 emi-mems:
61 "emi-mem-cells":
65 emi-mem-cells:
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/Zephyr-latest/dts/bindings/input/
Dzephyr,lvgl-keypad-input.yaml2 # SPDX-License-Identifier: Apache-2.0
5 LVGL keypad indev pseudo-device
10 The property input-codes can be used to setup a mapping of input codes
12 https://docs.lvgl.io/master/overview/indev.html#keys.
17 #include <zephyr/dt-bindings/lvgl/lvgl.h>
20 compatible = "zephyr,lvgl-keypad-input";
22 input-codes = <INPUT_KEY_1 INPUT_KEY_2>;
23 lvgl-codes = <LV_KEY_NEXT LV_KEY_PREV>;
26 compatible: "zephyr,lvgl-keypad-input"
28 include: zephyr,lvgl-common-input.yaml
[all …]
/Zephyr-latest/boards/qemu/x86/
Dqemu_x86_lakemont.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
25 uart-0 = &uart0;
31 zephyr,shell-uart = &uart0;
43 io-mapped;
44 clock-frequency = <1843200>;
46 interrupt-parent = <&intc>;
47 current-speed = <115200>;
48 reg-shift = <2>;
56 interrupt-parent = <&intc>;
/Zephyr-latest/samples/subsys/mgmt/updatehub/
Doverlay-ot.conf2 # SPDX-License-Identifier: Apache-2.0
28 # This follows https://openthread.io/guides/border-router guides
29 # It uses the default values from otbr-web page
55 # Mapped Address: 0:0:0:0:0:ffff:808:808
/Zephyr-latest/arch/x86/core/
Defi.c4 * SPDX-License-Identifier: Apache-2.0
27 return efi->acpi_rsdp; in efi_get_acpi_rsdp()
43 * as Zephyr has only mapped memory it uses and IO it knows about. In
47 * plays with the IO-MMU... the posibilities are endless). But
51 * system as-is; we already know it doesn't overlap with the EFI
56 * environment where it would be running on multi-gigabyte systems and
58 * the problem of the red zone -- SysV reserves 128 bytes of
69 * are also caller-save. Technically X/YMM0-5 are caller-save too,
73 * the caller as spill space for the 4 register-passed arguments (this
74 * ABI is so weird...). We also need two call-preserved scratch
[all …]
/Zephyr-latest/samples/subsys/display/lvgl/
DREADME.rst1 .. zephyr:code-sample:: lvgl
3 :relevant-api: display_interface input_interface
17 (:dtcompatible:`zephyr,lvgl-pointer-input`), a button widget is displayed
20 The button pseudo device (:dtcompatible:`zephyr,lvgl-button-input`) maps
22 of this sample, the coordinates are mapped to the center of the screen.
24 The encoder pseudo device (:dtcompatible:`zephyr,lvgl-encoder-input`)
29 The keypad pseudo device (:dtcompatible:`zephyr,lvgl-keypad-input`) can
41 - :ref:`adafruit_2_8_tft_touch_v2` and :ref:`nrf52840dk_nrf52840`
42 - :ref:`buydisplay_2_8_tft_touch_arduino` and :ref:`nrf52840dk_nrf52840`
43 - :ref:`ssd1306_128_shield` and :zephyr:board:`frdm_k64f`
[all …]
/Zephyr-latest/subsys/mgmt/updatehub/
DKconfig1 # Copyright (c) 2018-2023 O.S.Systems
2 # SPDX-License-Identifier: Apache-2.0
5 bool "UpdateHub Firmware Over-the-Air support"
23 UpdateHub is an enterprise-grade solution which makes simple to
25 handles all aspects related to sending Firmware Over-the-Air
56 Server (updatehub-ce) as alternative to the
57 updatehub.io enterprise server.
60 string "User address for the updatehub-ce-server"
104 0 - COAP_BLOCK_16
105 1 - COAP_BLOCK_32
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/Zephyr-latest/include/zephyr/sys/
Ddevice_mmio.h4 * SPDX-License-Identifier: Apache-2.0
13 * @defgroup device-mmio Device memory-mapped IO management
16 * Definitions and helper macros for managing driver memory-mapped
20 * including this separately may be needed for arch-level driver code
28 /* Storing MMIO addresses in RAM is a system-wide decision based on
31 * If we have an MMU enabled, all physical MMIO regions must be mapped into
34 * If we have PCIE enabled, this does mean that non-PCIE drivers may waste
85 * The mapped linear address will have read-write access to supervisor mode.
102 * read-write access. in device_map()
140 * @defgroup device-mmio-single Single MMIO region macros
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/Zephyr-latest/include/zephyr/acpi/
Dacpi.h4 * SPDX-License-Identifier: Apache-2.0
18 #define ACPI_MMIO_GET(res) (res)->reg_base[0].mmio
19 #define ACPI_IO_GET(res) (res)->reg_base[0].port
20 #define ACPI_RESOURCE_SIZE_GET(res) (res)->reg_base[0].length
21 #define ACPI_RESOURCE_TYPE_GET(res) (res)->reg_base[0].type
23 #define ACPI_MULTI_MMIO_GET(res, idx) (res)->reg_base[idx].mmio
24 #define ACPI_MULTI_IO_GET(res, idx) (res)->reg_base[idx].port
25 #define ACPI_MULTI_RESOURCE_SIZE_GET(res, idx) (res)->reg_base[idx].length
26 #define ACPI_MULTI_RESOURCE_TYPE_GET(res, idx) (res)->reg_base[idx].type
28 #define ACPI_RESOURCE_COUNT_GET(res) (res)->mmio_max
[all …]
/Zephyr-latest/drivers/pcie/host/
Dpcie_ecam.c4 * SPDX-License-Identifier: Apache-2.0
24 * - handle prefetchable regions
47 const struct pcie_ctrl_config *cfg = dev->config; in pcie_ecam_init()
48 struct pcie_ecam_data *data = dev->data; in pcie_ecam_init()
52 * Flags defined in the PCI Bus Binding to IEEE Std 1275-1994 : in pcie_ecam_init()
64 * t is 1 if the address is aliased (for non-relocatable I/O), below 1 MB (for Memory), in pcie_ecam_init()
69 * 10 denotes 32-bit-address Memory Space in pcie_ecam_init()
70 * 11 denotes 64-bit-address Memory Space in pcie_ecam_init()
71 * bbbbbbbb is the 8-bit Bus Number in pcie_ecam_init()
72 * ddddd is the 5-bit Device Number in pcie_ecam_init()
[all …]
/Zephyr-latest/drivers/serial/
Duart_ns16550.c1 /* ns16550.c - NS16550D serial driver */
6 * Copyright (c) 2010, 2012-2015 Wind River Systems, Inc.
7 * Copyright (c) 2020-2023 Intel Corp.
9 * SPDX-License-Identifier: Apache-2.0
72 /* If any node has property io-mapped set, we need to support IO port
76 * as io-mapped property is considered always exists and present,
78 * resort to the follow helper to see if any okay nodes have io-mapped
165 * RXRDY pin will go inactive when there are no more charac-
170 * reached, the RXRDY pin will go low active. Once it is acti-
175 * FIFO Mode (FCR0 = 1, FCR3 = 0) and there are no charac-
[all …]
/Zephyr-latest/boards/telink/tlsr9518adk80d/doc/
Dindex.rst17 The TLSR9518A SoC integrates a powerful 32-bit RISC-V MCU, DSP, AI Engine, 2.4 GHz ISM Radio, 256
19 stereo audio codec, 14 bit AUX ADC, analog and digital Microphone input, PWM, flexible IO interface…
28 - RF conducted antenna
29 - 1 MB External Flash memory with reset button
30 - Chip reset button
31 - Mini USB interface
32 - 4-wire JTAG
33 - 4 LEDs, Key matrix up to 4 keys
34 - 2 line-in function (Dual Analog microphone supported when switching jumper from microphone path)
35 - Dual Digital microphone
[all …]
/Zephyr-latest/doc/kernel/drivers/
Dindex.rst57 should support an interrupt-based implementation, rather than polling, unless
60 High-level calls accessed through device-specific APIs, such as
75 up for boot-time initialization.
98 split into read-only and runtime-mutable parts. At a high level we have:
100 .. code-block:: C
109 The ``config`` member is for read-only configuration data set at build time. For
110 example, base memory mapped IO addresses, IRQ line numbers, or other fixed
115 per-instance runtime housekeeping. For example, it may contain reference counts,
118 The ``api`` struct maps generic subsystem APIs to the device-specific
119 implementations in the driver. It is typically read-only and populated at
[all …]
/Zephyr-latest/include/zephyr/xen/public/
Dgrant_table.h1 /* SPDX-License-Identifier: MIT */
7 * page-ownership transfers.
40 * device drivers for block and network IO.
50 * This capability-based system allows shared-memory communications
62 /* Some rough guidelines on accessing and updating grant-table entries
63 * in a concurrency-safe manner. For more information, Linux contains a
65 …* http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=blob;f=drivers/xen/grant-table.c;…
67 * NB. WMB is a no-op on current-generation x86 processors. However, a
71 * 1. Write ent->domid.
72 * 2. Write ent->frame:
[all …]
/Zephyr-latest/arch/x86/
DKconfig3 # Copyright (c) 2014-2015 Wind River Systems, Inc.
4 # SPDX-License-Identifier: Apache-2.0
13 # CPU Families - the SoC configuration should select the right one.
70 # Configuration common to both IA32 and Intel64 sub-architectures.
74 bool "Run in 64-bit mode"
173 bool "Compiler-generated SSEx instructions for floating point math"
201 This value normally need to be page-aligned.
241 Selects the use of the memory-mapped PCI Express Extended
243 IO Port registers.
254 Hidden option to signal building for PC-compatible platforms
[all …]
/Zephyr-latest/drivers/flash/
Dflash_npcx_fiu_nor.c4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/flash_controller/npcx_fiu_qspi.h>
39 /* Mapped address for flash read via direct access */
43 /* Maximum chip erase time-out in ms */
56 /* Specific control operation for Quad-SPI Nor Flash */
82 const struct flash_npcx_nor_config *config = dev->config; in flash_npcx_uma_transceive()
83 struct flash_npcx_nor_data *data = dev->data; in flash_npcx_uma_transceive()
87 qspi_npcx_fiu_mutex_lock_configure(config->qspi_bus, &config->qspi_cfg, in flash_npcx_uma_transceive()
88 data->operation); in flash_npcx_uma_transceive()
91 ret = qspi_npcx_fiu_uma_transceive(config->qspi_bus, cfg, flags); in flash_npcx_uma_transceive()
[all …]
Dflash_stm32_xspi.c4 * SPDX-License-Identifier: Apache-2.0
23 #include <zephyr/dt-bindings/flash_controller/xspi.h>
59 struct flash_stm32_xspi_data *dev_data = dev->data; in xspi_lock_thread()
61 k_sem_take(&dev_data->sem, K_FOREVER); in xspi_lock_thread()
66 struct flash_stm32_xspi_data *dev_data = dev->data; in xspi_unlock_thread()
68 k_sem_give(&dev_data->sem); in xspi_unlock_thread()
73 struct flash_stm32_xspi_data *dev_data = dev->data; in xspi_send_cmd()
76 LOG_DBG("Instruction 0x%x", cmd->Instruction); in xspi_send_cmd()
78 dev_data->cmd_status = 0; in xspi_send_cmd()
80 hal_ret = HAL_XSPI_Command(&dev_data->hxspi, cmd, HAL_XSPI_TIMEOUT_DEFAULT_VALUE); in xspi_send_cmd()
[all …]
/Zephyr-latest/doc/develop/debug/
Dindex.rst11 This section is a quick hands-on reference to start debugging your
46 .. code-block:: bash
48 qemu -s -S <image>
54 * ``-S`` Do not start CPU at startup; rather, you must type 'c' in the
56 * ``-s`` Shorthand for :literal:`-gdb tcp::1234`: open a GDB server on
65 .. code-block:: console
70 :makevar:`${QEMU_PIPE}` via CMake, typically :file:`qemu-fifo` within the build
71 directory. You may monitor this file during the run with :command:`tail -f
72 qemu-fifo`.
79 .. code-block:: console
[all …]

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