1# Copyright (c) 2021, Microchip Technology Inc.
2# SPDX-License-Identifier: Apache-2.0
3
4description: Microchip XEC eSPI Host devices
5
6compatible: "microchip,xec-espi-host-dev"
7
8include: [base.yaml]
9
10on-bus: espi
11
12properties:
13  reg:
14    required: true
15
16  ldn:
17    type: int
18    required: true
19    description: logical device number
20
21  girqs:
22    type: array
23    description: array of GIRQ and bit positions
24
25  pcrs:
26    type: array
27    description: PCR sleep register index and bit position
28
29  # optional properties application to different host facing devices
30  host-io:
31    type: int
32    description: |
33      Logical device Host I/O (x86) base. Refer to SoC documentation for the
34      number of I/O decoders implemented by a device (1 or 2) and the fixed
35      I/O masks.
36
37  host-io-addr-mask:
38    type: int
39    description: |
40      Host I/O address mask. This value is fixed for all HW and is only
41      used by Port80 BIOS debug alias device to specify the byte lane the
42      alias address is mapped to in the 80h to 83h I/O range.
43
44  host-mem:
45    type: int
46    description: |
47      Logical device Host memory (x86) base address. Refer to SoC
48      documentation for which logical devices implement a memory decoder
49      and the fixed memory address masking.
50
51  emi-mems:
52    type: array
53    description: |
54      Each EMI host device supports Host access to two SoC data memory
55      regions. Each region requires three configuration parameters:
56      Base address in the SoC data memory, read limit, and write limit.
57      If bits[14:2] of the address written by the Host to the EC address
58      register is less than the limit value the access is allowed. Bit[15]
59      of the EC address selects which of the two memory regions is accessed.
60
61  "emi-mem-cells":
62    type: int
63    const: 3
64
65emi-mem-cells:
66  - base
67  - rdlimit
68  - wrlimit
69