1 /*
2 * Copyright (c) 2024 STMicroelectronics
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 /*
8 * **************************************************************************
9 * xSPI flash controller driver for stm32 serie with xSPI periherals
10 * This driver is based on the stm32Cube HAL XSPI driver
11 * with one xspi DTS NODE
12 * **************************************************************************
13 */
14 #define DT_DRV_COMPAT st_stm32_xspi_nor
15
16 #include <errno.h>
17 #include <zephyr/kernel.h>
18 #include <soc.h>
19 #include <zephyr/drivers/pinctrl.h>
20 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
21 #include <zephyr/drivers/clock_control.h>
22 #include <zephyr/drivers/flash.h>
23 #include <zephyr/dt-bindings/flash_controller/xspi.h>
24 #include <zephyr/drivers/gpio.h>
25 #include <zephyr/irq.h>
26
27 #include "spi_nor.h"
28 #include "jesd216.h"
29
30 #include <zephyr/logging/log.h>
31 LOG_MODULE_REGISTER(flash_stm32_xspi, CONFIG_FLASH_LOG_LEVEL);
32
33 #define STM32_XSPI_NODE DT_INST_PARENT(0)
34
35 #define DT_XSPI_IO_PORT_PROP_OR(prop, default_value) \
36 COND_CODE_1(DT_NODE_HAS_PROP(STM32_XSPI_NODE, prop), \
37 (_CONCAT(HAL_XSPIM_, DT_STRING_TOKEN(STM32_XSPI_NODE, prop))), \
38 ((default_value)))
39
40 /* Get the base address of the flash from the DTS node */
41 #define STM32_XSPI_BASE_ADDRESS DT_INST_REG_ADDR(0)
42
43 #define STM32_XSPI_RESET_GPIO DT_INST_NODE_HAS_PROP(0, reset_gpios)
44
45 #define STM32_XSPI_DLYB_BYPASSED DT_PROP(STM32_XSPI_NODE, dlyb_bypass)
46
47 #define STM32_XSPI_USE_DMA DT_NODE_HAS_PROP(STM32_XSPI_NODE, dmas)
48
49 #if STM32_XSPI_USE_DMA
50 #include <zephyr/drivers/dma/dma_stm32.h>
51 #include <zephyr/drivers/dma.h>
52 #include <stm32_ll_dma.h>
53 #endif /* STM32_XSPI_USE_DMA */
54
55 #include "flash_stm32_xspi.h"
56
xspi_lock_thread(const struct device * dev)57 static inline void xspi_lock_thread(const struct device *dev)
58 {
59 struct flash_stm32_xspi_data *dev_data = dev->data;
60
61 k_sem_take(&dev_data->sem, K_FOREVER);
62 }
63
xspi_unlock_thread(const struct device * dev)64 static inline void xspi_unlock_thread(const struct device *dev)
65 {
66 struct flash_stm32_xspi_data *dev_data = dev->data;
67
68 k_sem_give(&dev_data->sem);
69 }
70
xspi_send_cmd(const struct device * dev,XSPI_RegularCmdTypeDef * cmd)71 static int xspi_send_cmd(const struct device *dev, XSPI_RegularCmdTypeDef *cmd)
72 {
73 struct flash_stm32_xspi_data *dev_data = dev->data;
74 HAL_StatusTypeDef hal_ret;
75
76 LOG_DBG("Instruction 0x%x", cmd->Instruction);
77
78 dev_data->cmd_status = 0;
79
80 hal_ret = HAL_XSPI_Command(&dev_data->hxspi, cmd, HAL_XSPI_TIMEOUT_DEFAULT_VALUE);
81 if (hal_ret != HAL_OK) {
82 LOG_ERR("%d: Failed to send XSPI instruction", hal_ret);
83 return -EIO;
84 }
85 LOG_DBG("CCR 0x%x", dev_data->hxspi.Instance->CCR);
86
87 return dev_data->cmd_status;
88 }
89
xspi_read_access(const struct device * dev,XSPI_RegularCmdTypeDef * cmd,uint8_t * data,const size_t size)90 static int xspi_read_access(const struct device *dev, XSPI_RegularCmdTypeDef *cmd,
91 uint8_t *data, const size_t size)
92 {
93 struct flash_stm32_xspi_data *dev_data = dev->data;
94 HAL_StatusTypeDef hal_ret;
95
96 LOG_DBG("Instruction 0x%x", cmd->Instruction);
97
98 cmd->DataLength = size;
99
100 dev_data->cmd_status = 0;
101
102 hal_ret = HAL_XSPI_Command(&dev_data->hxspi, cmd, HAL_XSPI_TIMEOUT_DEFAULT_VALUE);
103 if (hal_ret != HAL_OK) {
104 LOG_ERR("%d: Failed to send XSPI instruction", hal_ret);
105 return -EIO;
106 }
107
108 #if STM32_XSPI_USE_DMA
109 hal_ret = HAL_XSPI_Receive_DMA(&dev_data->hxspi, data);
110 #else
111 hal_ret = HAL_XSPI_Receive_IT(&dev_data->hxspi, data);
112 #endif
113
114 if (hal_ret != HAL_OK) {
115 LOG_ERR("%d: Failed to read data", hal_ret);
116 return -EIO;
117 }
118
119 k_sem_take(&dev_data->sync, K_FOREVER);
120
121 return dev_data->cmd_status;
122 }
123
xspi_write_access(const struct device * dev,XSPI_RegularCmdTypeDef * cmd,const uint8_t * data,const size_t size)124 static int xspi_write_access(const struct device *dev, XSPI_RegularCmdTypeDef *cmd,
125 const uint8_t *data, const size_t size)
126 {
127 const struct flash_stm32_xspi_config *dev_cfg = dev->config;
128 struct flash_stm32_xspi_data *dev_data = dev->data;
129 HAL_StatusTypeDef hal_ret;
130
131 LOG_DBG("Instruction 0x%x", cmd->Instruction);
132
133 cmd->DataLength = size;
134
135 dev_data->cmd_status = 0;
136
137 /* in OPI/STR the 3-byte AddressWidth is not supported by the NOR flash */
138 if ((dev_cfg->data_mode == XSPI_OCTO_MODE) &&
139 (cmd->AddressWidth != HAL_XSPI_ADDRESS_32_BITS)) {
140 LOG_ERR("XSPI wr in OPI/STR mode is for 32bit address only");
141 return -EIO;
142 }
143
144 hal_ret = HAL_XSPI_Command(&dev_data->hxspi, cmd, HAL_XSPI_TIMEOUT_DEFAULT_VALUE);
145 if (hal_ret != HAL_OK) {
146 LOG_ERR("%d: Failed to send XSPI instruction", hal_ret);
147 return -EIO;
148 }
149
150 #if STM32_XSPI_USE_DMA
151 hal_ret = HAL_XSPI_Transmit_DMA(&dev_data->hxspi, (uint8_t *)data);
152 #else
153 hal_ret = HAL_XSPI_Transmit_IT(&dev_data->hxspi, (uint8_t *)data);
154 #endif
155
156 if (hal_ret != HAL_OK) {
157 LOG_ERR("%d: Failed to write data", hal_ret);
158 return -EIO;
159 }
160
161 k_sem_take(&dev_data->sync, K_FOREVER);
162
163 return dev_data->cmd_status;
164 }
165
166 /*
167 * Gives a XSPI_RegularCmdTypeDef with all parameters set
168 * except Instruction, Address, DummyCycles, NbData
169 */
xspi_prepare_cmd(const uint8_t transfer_mode,const uint8_t transfer_rate)170 static XSPI_RegularCmdTypeDef xspi_prepare_cmd(const uint8_t transfer_mode,
171 const uint8_t transfer_rate)
172 {
173 XSPI_RegularCmdTypeDef cmd_tmp = {
174 .OperationType = HAL_XSPI_OPTYPE_COMMON_CFG,
175 .InstructionWidth = ((transfer_mode == XSPI_OCTO_MODE)
176 ? HAL_XSPI_INSTRUCTION_16_BITS
177 : HAL_XSPI_INSTRUCTION_8_BITS),
178 .InstructionDTRMode = ((transfer_rate == XSPI_DTR_TRANSFER)
179 ? HAL_XSPI_INSTRUCTION_DTR_ENABLE
180 : HAL_XSPI_INSTRUCTION_DTR_DISABLE),
181 .AddressDTRMode = ((transfer_rate == XSPI_DTR_TRANSFER)
182 ? HAL_XSPI_ADDRESS_DTR_ENABLE
183 : HAL_XSPI_ADDRESS_DTR_DISABLE),
184 /* AddressWidth must be set to 32bits for init and mem config phase */
185 .AddressWidth = HAL_XSPI_ADDRESS_32_BITS,
186 .AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE,
187 .DataDTRMode = ((transfer_rate == XSPI_DTR_TRANSFER)
188 ? HAL_XSPI_DATA_DTR_ENABLE
189 : HAL_XSPI_DATA_DTR_DISABLE),
190 .DQSMode = (transfer_rate == XSPI_DTR_TRANSFER)
191 ? HAL_XSPI_DQS_ENABLE
192 : HAL_XSPI_DQS_DISABLE,
193 .SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD,
194 };
195
196 switch (transfer_mode) {
197 case XSPI_OCTO_MODE: {
198 cmd_tmp.InstructionMode = HAL_XSPI_INSTRUCTION_8_LINES;
199 cmd_tmp.AddressMode = HAL_XSPI_ADDRESS_8_LINES;
200 cmd_tmp.DataMode = HAL_XSPI_DATA_8_LINES;
201 break;
202 }
203 case XSPI_QUAD_MODE: {
204 cmd_tmp.InstructionMode = HAL_XSPI_INSTRUCTION_4_LINES;
205 cmd_tmp.AddressMode = HAL_XSPI_ADDRESS_4_LINES;
206 cmd_tmp.DataMode = HAL_XSPI_DATA_4_LINES;
207 break;
208 }
209 case XSPI_DUAL_MODE: {
210 cmd_tmp.InstructionMode = HAL_XSPI_INSTRUCTION_2_LINES;
211 cmd_tmp.AddressMode = HAL_XSPI_ADDRESS_2_LINES;
212 cmd_tmp.DataMode = HAL_XSPI_DATA_2_LINES;
213 break;
214 }
215 default: {
216 cmd_tmp.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE;
217 cmd_tmp.AddressMode = HAL_XSPI_ADDRESS_1_LINE;
218 cmd_tmp.DataMode = HAL_XSPI_DATA_1_LINE;
219 break;
220 }
221 }
222
223 return cmd_tmp;
224 }
225
stm32_xspi_hal_address_size(const struct device * dev)226 static uint32_t stm32_xspi_hal_address_size(const struct device *dev)
227 {
228 struct flash_stm32_xspi_data *dev_data = dev->data;
229
230 if (dev_data->address_width == 4U) {
231 return HAL_XSPI_ADDRESS_32_BITS;
232 }
233
234 return HAL_XSPI_ADDRESS_24_BITS;
235 }
236
237 #if defined(CONFIG_FLASH_JESD216_API)
238 /*
239 * Read the JEDEC ID data from the external Flash at init
240 * and store in the jedec_id Table of the flash_stm32_xspi_data
241 * The JEDEC ID is not given by a DTS property
242 */
stm32_xspi_read_jedec_id(const struct device * dev)243 static int stm32_xspi_read_jedec_id(const struct device *dev)
244 {
245 struct flash_stm32_xspi_data *dev_data = dev->data;
246
247 /* This is a SPI/STR command to issue to the external Flash device */
248 XSPI_RegularCmdTypeDef cmd = xspi_prepare_cmd(XSPI_SPI_MODE, XSPI_STR_TRANSFER);
249
250 cmd.Instruction = JESD216_CMD_READ_ID;
251 cmd.AddressWidth = stm32_xspi_hal_address_size(dev);
252 cmd.AddressMode = HAL_XSPI_ADDRESS_NONE;
253 cmd.DataLength = JESD216_READ_ID_LEN; /* 3 bytes in the READ ID */
254
255 HAL_StatusTypeDef hal_ret;
256
257 hal_ret = HAL_XSPI_Command(&dev_data->hxspi, &cmd,
258 HAL_XSPI_TIMEOUT_DEFAULT_VALUE);
259
260 if (hal_ret != HAL_OK) {
261 LOG_ERR("%d: Failed to send XSPI instruction", hal_ret);
262 return -EIO;
263 }
264
265 /* Place the received data directly into the jedec Table */
266 hal_ret = HAL_XSPI_Receive(&dev_data->hxspi, dev_data->jedec_id,
267 HAL_XSPI_TIMEOUT_DEFAULT_VALUE);
268 if (hal_ret != HAL_OK) {
269 LOG_ERR("%d: Failed to read data", hal_ret);
270 return -EIO;
271 }
272
273 LOG_DBG("Jedec ID = [%02x %02x %02x]",
274 dev_data->jedec_id[0], dev_data->jedec_id[1], dev_data->jedec_id[2]);
275
276 dev_data->cmd_status = 0;
277
278 return 0;
279 }
280
281 /*
282 * Read Serial Flash ID :
283 * just gives the values received by the external Flash
284 */
xspi_read_jedec_id(const struct device * dev,uint8_t * id)285 static int xspi_read_jedec_id(const struct device *dev, uint8_t *id)
286 {
287 struct flash_stm32_xspi_data *dev_data = dev->data;
288
289 /* Take jedec Id values from the table (issued from the octoFlash) */
290 memcpy(id, dev_data->jedec_id, JESD216_READ_ID_LEN);
291
292 LOG_INF("Manuf ID = %02x Memory Type = %02x Memory Density = %02x",
293 id[0], id[1], id[2]);
294
295 return 0;
296 }
297 #endif /* CONFIG_FLASH_JESD216_API */
298
299 /*
300 * Read Serial Flash Discovery Parameter from the external Flash at init :
301 * perform a read access over SPI bus for SDFP (DataMode is already set)
302 * The SFDP table is not given by a DTS property
303 */
stm32_xspi_read_sfdp(const struct device * dev,off_t addr,void * data,size_t size)304 static int stm32_xspi_read_sfdp(const struct device *dev, off_t addr,
305 void *data,
306 size_t size)
307 {
308 const struct flash_stm32_xspi_config *dev_cfg = dev->config;
309 struct flash_stm32_xspi_data *dev_data = dev->data;
310
311 XSPI_RegularCmdTypeDef cmd = xspi_prepare_cmd(dev_cfg->data_mode,
312 dev_cfg->data_rate);
313 if (dev_cfg->data_mode == XSPI_OCTO_MODE) {
314 cmd.Instruction = JESD216_OCMD_READ_SFDP;
315 cmd.DummyCycles = 20U;
316 cmd.AddressWidth = HAL_XSPI_ADDRESS_32_BITS;
317 } else {
318 cmd.Instruction = JESD216_CMD_READ_SFDP;
319 cmd.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE;
320 cmd.DataMode = HAL_XSPI_DATA_1_LINE;
321 cmd.AddressMode = HAL_XSPI_ADDRESS_1_LINE;
322 cmd.DummyCycles = 8U;
323 cmd.AddressWidth = HAL_XSPI_ADDRESS_24_BITS;
324 }
325 cmd.Address = addr;
326 cmd.DataLength = size;
327
328 HAL_StatusTypeDef hal_ret;
329
330 hal_ret = HAL_XSPI_Command(&dev_data->hxspi, &cmd, HAL_XSPI_TIMEOUT_DEFAULT_VALUE);
331 if (hal_ret != HAL_OK) {
332 LOG_ERR("%d: Failed to send XSPI instruction", hal_ret);
333 return -EIO;
334 }
335
336 hal_ret = HAL_XSPI_Receive(&dev_data->hxspi, (uint8_t *)data,
337 HAL_XSPI_TIMEOUT_DEFAULT_VALUE);
338 if (hal_ret != HAL_OK) {
339 LOG_ERR("%d: Failed to read data", hal_ret);
340 return -EIO;
341 }
342
343 dev_data->cmd_status = 0;
344
345 return 0;
346 }
347
348 /*
349 * Read Serial Flash Discovery Parameter :
350 * perform a read access over SPI bus for SDFP (DataMode is already set)
351 */
xspi_read_sfdp(const struct device * dev,off_t addr,void * data,size_t size)352 static int xspi_read_sfdp(const struct device *dev, off_t addr, void *data,
353 size_t size)
354 {
355 LOG_INF("Read SFDP from externalFlash");
356 /* Get the SFDP from the external Flash (no sfdp-bfp table in the DeviceTree) */
357 if (stm32_xspi_read_sfdp(dev, addr, data, size) == 0) {
358 /* If valid, then ignore any table from the DTS */
359 return 0;
360 }
361 LOG_INF("Error reading SFDP from external Flash and none in the DTS");
362 return -EINVAL;
363 }
364
xspi_address_is_valid(const struct device * dev,off_t addr,size_t size)365 static bool xspi_address_is_valid(const struct device *dev, off_t addr,
366 size_t size)
367 {
368 const struct flash_stm32_xspi_config *dev_cfg = dev->config;
369 size_t flash_size = dev_cfg->flash_size;
370
371 return (addr >= 0) && ((uint64_t)addr + (uint64_t)size <= flash_size);
372 }
373
stm32_xspi_wait_auto_polling(const struct device * dev,XSPI_AutoPollingTypeDef * s_config,uint32_t timeout_ms)374 static int stm32_xspi_wait_auto_polling(const struct device *dev,
375 XSPI_AutoPollingTypeDef *s_config, uint32_t timeout_ms)
376 {
377 struct flash_stm32_xspi_data *dev_data = dev->data;
378
379 dev_data->cmd_status = 0;
380
381 if (HAL_XSPI_AutoPolling_IT(&dev_data->hxspi, s_config) != HAL_OK) {
382 LOG_ERR("XSPI AutoPoll failed");
383 return -EIO;
384 }
385
386 if (k_sem_take(&dev_data->sync, K_MSEC(timeout_ms)) != 0) {
387 LOG_ERR("XSPI AutoPoll wait failed");
388 HAL_XSPI_Abort(&dev_data->hxspi);
389 k_sem_reset(&dev_data->sync);
390 return -EIO;
391 }
392
393 /* HAL_XSPI_AutoPolling_IT enables transfer error interrupt which sets
394 * cmd_status.
395 */
396 return dev_data->cmd_status;
397 }
398
399 /*
400 * This function Polls the WEL (write enable latch) bit to become to 0
401 * When the Chip Erase Cycle is completed, the Write Enable Latch (WEL) bit is cleared.
402 * in nor_mode SPI/OPI XSPI_SPI_MODE or XSPI_OCTO_MODE
403 * and nor_rate transfer STR/DTR XSPI_STR_TRANSFER or XSPI_DTR_TRANSFER
404 */
stm32_xspi_mem_erased(const struct device * dev)405 static int stm32_xspi_mem_erased(const struct device *dev)
406 {
407 const struct flash_stm32_xspi_config *dev_cfg = dev->config;
408 struct flash_stm32_xspi_data *dev_data = dev->data;
409 uint8_t nor_mode = dev_cfg->data_mode;
410 uint8_t nor_rate = dev_cfg->data_rate;
411
412 XSPI_AutoPollingTypeDef s_config = {0};
413 XSPI_RegularCmdTypeDef s_command = xspi_prepare_cmd(nor_mode, nor_rate);
414
415 /* Configure automatic polling mode command to wait for memory ready */
416 if (nor_mode == XSPI_OCTO_MODE) {
417 s_command.Instruction = SPI_NOR_OCMD_RDSR;
418 s_command.DummyCycles = (nor_rate == XSPI_DTR_TRANSFER)
419 ? SPI_NOR_DUMMY_REG_OCTAL_DTR
420 : SPI_NOR_DUMMY_REG_OCTAL;
421 } else {
422 s_command.Instruction = SPI_NOR_CMD_RDSR;
423 /* force 1-line InstructionMode for any non-OSPI transfer */
424 s_command.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE;
425 s_command.AddressMode = HAL_XSPI_ADDRESS_NONE;
426 /* force 1-line DataMode for any non-OSPI transfer */
427 s_command.DataMode = HAL_XSPI_DATA_1_LINE;
428 s_command.DummyCycles = 0;
429 }
430 s_command.DataLength = ((nor_rate == XSPI_DTR_TRANSFER) ? 2U : 1U);
431 s_command.Address = 0U;
432
433 /* Set the mask to 0x02 to mask all Status REG bits except WEL */
434 /* Set the match to 0x00 to check if the WEL bit is Reset */
435 s_config.MatchValue = SPI_NOR_WEL_MATCH;
436 s_config.MatchMask = SPI_NOR_WEL_MASK; /* Write Enable Latch */
437
438 s_config.MatchMode = HAL_XSPI_MATCH_MODE_AND;
439 s_config.IntervalTime = SPI_NOR_AUTO_POLLING_INTERVAL;
440 s_config.AutomaticStop = HAL_XSPI_AUTOMATIC_STOP_ENABLE;
441
442 if (HAL_XSPI_Command(&dev_data->hxspi, &s_command,
443 HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
444 LOG_ERR("XSPI AutoPoll command (WEL) failed");
445 return -EIO;
446 }
447
448 /* Start Automatic-Polling mode to wait until the memory is totally erased */
449 return stm32_xspi_wait_auto_polling(dev,
450 &s_config, STM32_XSPI_BULK_ERASE_MAX_TIME);
451 }
452
453 /*
454 * This function Polls the WIP(Write In Progress) bit to become to 0
455 * in nor_mode SPI/OPI XSPI_SPI_MODE or XSPI_OCTO_MODE
456 * and nor_rate transfer STR/DTR XSPI_STR_TRANSFER or XSPI_DTR_TRANSFER
457 */
stm32_xspi_mem_ready(const struct device * dev,uint8_t nor_mode,uint8_t nor_rate)458 static int stm32_xspi_mem_ready(const struct device *dev, uint8_t nor_mode,
459 uint8_t nor_rate)
460 {
461 struct flash_stm32_xspi_data *dev_data = dev->data;
462
463 XSPI_AutoPollingTypeDef s_config = {0};
464 XSPI_RegularCmdTypeDef s_command = xspi_prepare_cmd(nor_mode, nor_rate);
465
466 /* Configure automatic polling mode command to wait for memory ready */
467 if (nor_mode == XSPI_OCTO_MODE) {
468 s_command.Instruction = SPI_NOR_OCMD_RDSR;
469 s_command.DummyCycles = (nor_rate == XSPI_DTR_TRANSFER)
470 ? SPI_NOR_DUMMY_REG_OCTAL_DTR
471 : SPI_NOR_DUMMY_REG_OCTAL;
472 } else {
473 s_command.Instruction = SPI_NOR_CMD_RDSR;
474 /* force 1-line InstructionMode for any non-OSPI transfer */
475 s_command.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE;
476 s_command.AddressMode = HAL_XSPI_ADDRESS_NONE;
477 /* force 1-line DataMode for any non-OSPI transfer */
478 s_command.DataMode = HAL_XSPI_DATA_1_LINE;
479 s_command.DummyCycles = 0;
480 }
481 s_command.DataLength = ((nor_rate == XSPI_DTR_TRANSFER) ? 2U : 1U);
482 s_command.Address = 0U;
483
484 /* Set the mask to 0x01 to mask all Status REG bits except WIP */
485 /* Set the match to 0x00 to check if the WIP bit is Reset */
486 s_config.MatchValue = SPI_NOR_MEM_RDY_MATCH;
487 s_config.MatchMask = SPI_NOR_MEM_RDY_MASK; /* Write in progress */
488 s_config.MatchMode = HAL_XSPI_MATCH_MODE_AND;
489 s_config.IntervalTime = SPI_NOR_AUTO_POLLING_INTERVAL;
490 s_config.AutomaticStop = HAL_XSPI_AUTOMATIC_STOP_ENABLE;
491
492 if (HAL_XSPI_Command(&dev_data->hxspi, &s_command,
493 HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
494 LOG_ERR("XSPI AutoPoll command failed");
495 return -EIO;
496 }
497
498 /* Start Automatic-Polling mode to wait until the memory is ready WIP=0 */
499 return stm32_xspi_wait_auto_polling(dev, &s_config, HAL_XSPI_TIMEOUT_DEFAULT_VALUE);
500 }
501
502 /* Enables writing to the memory sending a Write Enable and wait it is effective */
stm32_xspi_write_enable(const struct device * dev,uint8_t nor_mode,uint8_t nor_rate)503 static int stm32_xspi_write_enable(const struct device *dev,
504 uint8_t nor_mode, uint8_t nor_rate)
505 {
506 struct flash_stm32_xspi_data *dev_data = dev->data;
507
508 XSPI_AutoPollingTypeDef s_config = {0};
509 XSPI_RegularCmdTypeDef s_command = xspi_prepare_cmd(nor_mode, nor_rate);
510
511 /* Initialize the write enable command */
512 if (nor_mode == XSPI_OCTO_MODE) {
513 s_command.Instruction = SPI_NOR_OCMD_WREN;
514 } else {
515 s_command.Instruction = SPI_NOR_CMD_WREN;
516 /* force 1-line InstructionMode for any non-OSPI transfer */
517 s_command.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE;
518 }
519 s_command.AddressMode = HAL_XSPI_ADDRESS_NONE;
520 s_command.DataMode = HAL_XSPI_DATA_NONE;
521 s_command.DummyCycles = 0U;
522
523 if (HAL_XSPI_Command(&dev_data->hxspi, &s_command,
524 HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
525 LOG_ERR("XSPI flash write enable cmd failed");
526 return -EIO;
527 }
528
529 /* New command to Configure automatic polling mode to wait for write enabling */
530 if (nor_mode == XSPI_OCTO_MODE) {
531 s_command.Instruction = SPI_NOR_OCMD_RDSR;
532 s_command.AddressMode = HAL_XSPI_ADDRESS_8_LINES;
533 s_command.DataMode = HAL_XSPI_DATA_8_LINES;
534 s_command.DummyCycles = (nor_rate == XSPI_DTR_TRANSFER)
535 ? SPI_NOR_DUMMY_REG_OCTAL_DTR
536 : SPI_NOR_DUMMY_REG_OCTAL;
537 } else {
538 s_command.Instruction = SPI_NOR_CMD_RDSR;
539 /* force 1-line DataMode for any non-OSPI transfer */
540 s_command.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE;
541 s_command.AddressMode = HAL_XSPI_ADDRESS_1_LINE;
542 s_command.DataMode = HAL_XSPI_DATA_1_LINE;
543 s_command.DummyCycles = 0;
544
545 /* DummyCycles remains 0 */
546 }
547 s_command.DataLength = (nor_rate == XSPI_DTR_TRANSFER) ? 2U : 1U;
548 s_command.Address = 0U;
549
550 if (HAL_XSPI_Command(&dev_data->hxspi, &s_command,
551 HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
552 LOG_ERR("XSPI config auto polling cmd failed");
553 return -EIO;
554 }
555
556 s_config.MatchValue = SPI_NOR_WREN_MATCH;
557 s_config.MatchMask = SPI_NOR_WREN_MASK;
558 s_config.MatchMode = HAL_XSPI_MATCH_MODE_AND;
559 s_config.IntervalTime = SPI_NOR_AUTO_POLLING_INTERVAL;
560 s_config.AutomaticStop = HAL_XSPI_AUTOMATIC_STOP_ENABLE;
561
562 return stm32_xspi_wait_auto_polling(dev, &s_config, HAL_XSPI_TIMEOUT_DEFAULT_VALUE);
563 }
564
565 /* Write Flash configuration register 2 with new dummy cycles */
stm32_xspi_write_cfg2reg_dummy(XSPI_HandleTypeDef * hxspi,uint8_t nor_mode,uint8_t nor_rate)566 static int stm32_xspi_write_cfg2reg_dummy(XSPI_HandleTypeDef *hxspi,
567 uint8_t nor_mode, uint8_t nor_rate)
568 {
569 uint8_t transmit_data = SPI_NOR_CR2_DUMMY_CYCLES_66MHZ;
570 XSPI_RegularCmdTypeDef s_command = xspi_prepare_cmd(nor_mode, nor_rate);
571
572 /* Initialize the writing of configuration register 2 */
573 s_command.Instruction = (nor_mode == XSPI_SPI_MODE)
574 ? SPI_NOR_CMD_WR_CFGREG2
575 : SPI_NOR_OCMD_WR_CFGREG2;
576 s_command.Address = SPI_NOR_REG2_ADDR3;
577 s_command.DummyCycles = 0U;
578 s_command.DataLength = (nor_mode == XSPI_SPI_MODE) ? 1U
579 : ((nor_rate == XSPI_DTR_TRANSFER) ? 2U : 1U);
580
581 if (HAL_XSPI_Command(hxspi, &s_command,
582 HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
583 LOG_ERR("XSPI transmit cmd");
584 return -EIO;
585 }
586
587 if (HAL_XSPI_Transmit(hxspi, &transmit_data,
588 HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
589 LOG_ERR("XSPI transmit ");
590 return -EIO;
591 }
592
593 return 0;
594 }
595
596 /* Write Flash configuration register 2 with new single or octal SPI protocol */
stm32_xspi_write_cfg2reg_io(XSPI_HandleTypeDef * hxspi,uint8_t nor_mode,uint8_t nor_rate,uint8_t op_enable)597 static int stm32_xspi_write_cfg2reg_io(XSPI_HandleTypeDef *hxspi,
598 uint8_t nor_mode, uint8_t nor_rate, uint8_t op_enable)
599 {
600 XSPI_RegularCmdTypeDef s_command = xspi_prepare_cmd(nor_mode, nor_rate);
601
602 /* Initialize the writing of configuration register 2 */
603 s_command.Instruction = (nor_mode == XSPI_SPI_MODE)
604 ? SPI_NOR_CMD_WR_CFGREG2
605 : SPI_NOR_OCMD_WR_CFGREG2;
606 s_command.Address = SPI_NOR_REG2_ADDR1;
607 s_command.DummyCycles = 0U;
608 s_command.DataLength = (nor_mode == XSPI_SPI_MODE) ? 1U
609 : ((nor_rate == XSPI_DTR_TRANSFER) ? 2U : 1U);
610
611 if (HAL_XSPI_Command(hxspi, &s_command,
612 HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
613 LOG_ERR("Write Flash configuration reg2 failed");
614 return -EIO;
615 }
616
617 if (HAL_XSPI_Transmit(hxspi, &op_enable,
618 HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
619 LOG_ERR("Write Flash configuration reg2 failed");
620 return -EIO;
621 }
622
623 return 0;
624 }
625
626 /* Read Flash configuration register 2 with new single or octal SPI protocol */
stm32_xspi_read_cfg2reg(XSPI_HandleTypeDef * hxspi,uint8_t nor_mode,uint8_t nor_rate,uint8_t * value)627 static int stm32_xspi_read_cfg2reg(XSPI_HandleTypeDef *hxspi,
628 uint8_t nor_mode, uint8_t nor_rate, uint8_t *value)
629 {
630 XSPI_RegularCmdTypeDef s_command = xspi_prepare_cmd(nor_mode, nor_rate);
631
632 /* Initialize the writing of configuration register 2 */
633 s_command.Instruction = (nor_mode == XSPI_SPI_MODE)
634 ? SPI_NOR_CMD_RD_CFGREG2
635 : SPI_NOR_OCMD_RD_CFGREG2;
636 s_command.Address = SPI_NOR_REG2_ADDR1;
637 s_command.DummyCycles = (nor_mode == XSPI_SPI_MODE)
638 ? 0U
639 : ((nor_rate == XSPI_DTR_TRANSFER)
640 ? SPI_NOR_DUMMY_REG_OCTAL_DTR
641 : SPI_NOR_DUMMY_REG_OCTAL);
642 s_command.DataLength = (nor_rate == XSPI_DTR_TRANSFER) ? 2U : 1U;
643
644 if (HAL_XSPI_Command(hxspi, &s_command, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
645 LOG_ERR("Write Flash configuration reg2 failed");
646 return -EIO;
647 }
648
649 if (HAL_XSPI_Receive(hxspi, value, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
650 LOG_ERR("Write Flash configuration reg2 failed");
651 return -EIO;
652 }
653
654 return 0;
655 }
656
657 /* Set the NOR Flash to desired Interface mode : SPI/OSPI and STR/DTR according to the DTS */
stm32_xspi_config_mem(const struct device * dev)658 static int stm32_xspi_config_mem(const struct device *dev)
659 {
660 const struct flash_stm32_xspi_config *dev_cfg = dev->config;
661 struct flash_stm32_xspi_data *dev_data = dev->data;
662 uint8_t reg[2];
663
664 /* Going to set the SPI mode and STR transfer rate : done */
665 if ((dev_cfg->data_mode != XSPI_OCTO_MODE)
666 && (dev_cfg->data_rate == XSPI_STR_TRANSFER)) {
667 LOG_INF("OSPI flash config is SPI|DUAL|QUAD / STR");
668 return 0;
669 }
670
671 /* Going to set the XPI mode (STR or DTR transfer rate) */
672 LOG_DBG("XSPI configuring Octo SPI mode");
673
674 if (stm32_xspi_write_enable(dev,
675 XSPI_SPI_MODE, XSPI_STR_TRANSFER) != 0) {
676 LOG_ERR("OSPI write Enable failed");
677 return -EIO;
678 }
679
680 /* Write Configuration register 2 (with new dummy cycles) */
681 if (stm32_xspi_write_cfg2reg_dummy(&dev_data->hxspi,
682 XSPI_SPI_MODE, XSPI_STR_TRANSFER) != 0) {
683 LOG_ERR("XSPI write CFGR2 failed");
684 return -EIO;
685 }
686 if (stm32_xspi_mem_ready(dev,
687 XSPI_SPI_MODE, XSPI_STR_TRANSFER) != 0) {
688 LOG_ERR("XSPI autopolling failed");
689 return -EIO;
690 }
691 if (stm32_xspi_write_enable(dev,
692 XSPI_SPI_MODE, XSPI_STR_TRANSFER) != 0) {
693 LOG_ERR("XSPI write Enable 2 failed");
694 return -EIO;
695 }
696
697 /* Write Configuration register 2 (with Octal I/O SPI protocol : choose STR or DTR) */
698 uint8_t mode_enable = ((dev_cfg->data_rate == XSPI_DTR_TRANSFER)
699 ? SPI_NOR_CR2_DTR_OPI_EN
700 : SPI_NOR_CR2_STR_OPI_EN);
701 if (stm32_xspi_write_cfg2reg_io(&dev_data->hxspi,
702 XSPI_SPI_MODE, XSPI_STR_TRANSFER, mode_enable) != 0) {
703 LOG_ERR("XSPI write CFGR2 failed");
704 return -EIO;
705 }
706
707 /* Wait that the configuration is effective and check that memory is ready */
708 k_busy_wait(STM32_XSPI_WRITE_REG_MAX_TIME * USEC_PER_MSEC);
709
710 /* Reconfigure the memory type of the peripheral */
711 dev_data->hxspi.Init.MemoryType = HAL_XSPI_MEMTYPE_MACRONIX;
712 dev_data->hxspi.Init.DelayHoldQuarterCycle = HAL_XSPI_DHQC_ENABLE;
713 if (HAL_XSPI_Init(&dev_data->hxspi) != HAL_OK) {
714 LOG_ERR("XSPI mem type MACRONIX failed");
715 return -EIO;
716 }
717
718 if (dev_cfg->data_rate == XSPI_STR_TRANSFER) {
719 if (stm32_xspi_mem_ready(dev,
720 XSPI_OCTO_MODE, XSPI_STR_TRANSFER) != 0) {
721 /* Check Flash busy ? */
722 LOG_ERR("XSPI flash busy failed");
723 return -EIO;
724 }
725
726 if (stm32_xspi_read_cfg2reg(&dev_data->hxspi,
727 XSPI_OCTO_MODE, XSPI_STR_TRANSFER, reg) != 0) {
728 /* Check the configuration has been correctly done on SPI_NOR_REG2_ADDR1 */
729 LOG_ERR("XSPI flash config read failed");
730 return -EIO;
731 }
732
733 LOG_INF("XSPI flash config is OCTO / STR");
734 }
735
736 if (dev_cfg->data_rate == XSPI_DTR_TRANSFER) {
737 if (stm32_xspi_mem_ready(dev,
738 XSPI_OCTO_MODE, XSPI_DTR_TRANSFER) != 0) {
739 /* Check Flash busy ? */
740 LOG_ERR("XSPI flash busy failed");
741 return -EIO;
742 }
743
744 LOG_INF("XSPI flash config is OCTO / DTR");
745 }
746
747 return 0;
748 }
749
750 /* gpio or send the different reset command to the NOR flash in SPI/OSPI and STR/DTR */
stm32_xspi_mem_reset(const struct device * dev)751 static int stm32_xspi_mem_reset(const struct device *dev)
752 {
753 struct flash_stm32_xspi_data *dev_data = dev->data;
754
755 #if STM32_XSPI_RESET_GPIO
756 const struct flash_stm32_xspi_config *dev_cfg = dev->config;
757
758 /* Generate RESETn pulse for the flash memory */
759 gpio_pin_configure_dt(&dev_cfg->reset, GPIO_OUTPUT_ACTIVE);
760 k_msleep(DT_INST_PROP(0, reset_gpios_duration));
761 gpio_pin_set_dt(&dev_cfg->reset, 0);
762 #else
763
764 /* Reset command sent sucessively for each mode SPI/OPS & STR/DTR */
765 XSPI_RegularCmdTypeDef s_command = {
766 .OperationType = HAL_XSPI_OPTYPE_COMMON_CFG,
767 .AddressMode = HAL_XSPI_ADDRESS_NONE,
768 .InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE,
769 .InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE,
770 .Instruction = SPI_NOR_CMD_RESET_EN,
771 .InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS,
772 .AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE,
773 .DataLength = HAL_XSPI_DATA_NONE,
774 .DummyCycles = 0U,
775 .DQSMode = HAL_XSPI_DQS_DISABLE,
776 .SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD,
777 };
778
779 /* Reset enable in SPI mode and STR transfer mode */
780 if (HAL_XSPI_Command(&dev_data->hxspi,
781 &s_command, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
782 LOG_ERR("XSPI reset enable (SPI/STR) failed");
783 return -EIO;
784 }
785
786 /* Reset memory in SPI mode and STR transfer mode */
787 s_command.Instruction = SPI_NOR_CMD_RESET_MEM;
788 if (HAL_XSPI_Command(&dev_data->hxspi,
789 &s_command, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
790 LOG_ERR("XSPI reset memory (SPI/STR) failed");
791 return -EIO;
792 }
793
794 /* Reset enable in OPI mode and STR transfer mode */
795 s_command.InstructionMode = HAL_XSPI_INSTRUCTION_8_LINES;
796 s_command.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE;
797 s_command.Instruction = SPI_NOR_OCMD_RESET_EN;
798 s_command.InstructionWidth = HAL_XSPI_INSTRUCTION_16_BITS;
799 if (HAL_XSPI_Command(&dev_data->hxspi,
800 &s_command, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
801 LOG_ERR("XSPI reset enable (OCTO/STR) failed");
802 return -EIO;
803 }
804
805 /* Reset memory in OPI mode and STR transfer mode */
806 s_command.Instruction = SPI_NOR_OCMD_RESET_MEM;
807 if (HAL_XSPI_Command(&dev_data->hxspi,
808 &s_command, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
809 LOG_ERR("XSPI reset memory (OCTO/STR) failed");
810 return -EIO;
811 }
812
813 /* Reset enable in OPI mode and DTR transfer mode */
814 s_command.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_ENABLE;
815 s_command.Instruction = SPI_NOR_OCMD_RESET_EN;
816 if (HAL_XSPI_Command(&dev_data->hxspi,
817 &s_command, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
818 LOG_ERR("XSPI reset enable (OCTO/DTR) failed");
819 return -EIO;
820 }
821
822 /* Reset memory in OPI mode and DTR transfer mode */
823 s_command.Instruction = SPI_NOR_OCMD_RESET_MEM;
824 if (HAL_XSPI_Command(&dev_data->hxspi,
825 &s_command, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
826 LOG_ERR("XSPI reset memory (OCTO/DTR) failed");
827 return -EIO;
828 }
829
830 #endif /* STM32_XSPI_RESET_GPIO */
831 /* Wait after SWreset CMD, in case SWReset occurred during erase operation */
832 k_busy_wait(STM32_XSPI_RESET_MAX_TIME * USEC_PER_MSEC);
833
834 return 0;
835 }
836
837 #ifdef CONFIG_STM32_MEMMAP
838 /* Function to configure the octoflash in MemoryMapped mode */
stm32_xspi_set_memorymap(const struct device * dev)839 static int stm32_xspi_set_memorymap(const struct device *dev)
840 {
841 HAL_StatusTypeDef ret;
842 const struct flash_stm32_xspi_config *dev_cfg = dev->config;
843 struct flash_stm32_xspi_data *dev_data = dev->data;
844 XSPI_RegularCmdTypeDef s_command = {0}; /* Non-zero values disturb the command */
845 XSPI_MemoryMappedTypeDef s_MemMappedCfg;
846
847 /* Configure octoflash in MemoryMapped mode */
848 if ((dev_cfg->data_mode == XSPI_SPI_MODE) &&
849 (stm32_xspi_hal_address_size(dev) == HAL_XSPI_ADDRESS_24_BITS)) {
850 /* OPI mode and 3-bytes address size not supported by memory */
851 LOG_ERR("XSPI_SPI_MODE in 3Bytes addressing is not supported");
852 return -EIO;
853 }
854
855 /* Initialize the read command */
856 s_command.OperationType = HAL_XSPI_OPTYPE_READ_CFG;
857 s_command.InstructionMode = (dev_cfg->data_rate == XSPI_STR_TRANSFER)
858 ? ((dev_cfg->data_mode == XSPI_SPI_MODE)
859 ? HAL_XSPI_INSTRUCTION_1_LINE
860 : HAL_XSPI_INSTRUCTION_8_LINES)
861 : HAL_XSPI_INSTRUCTION_8_LINES;
862 s_command.InstructionDTRMode = (dev_cfg->data_rate == XSPI_STR_TRANSFER)
863 ? HAL_XSPI_INSTRUCTION_DTR_DISABLE
864 : HAL_XSPI_INSTRUCTION_DTR_ENABLE;
865 s_command.InstructionWidth = (dev_cfg->data_rate == XSPI_STR_TRANSFER)
866 ? ((dev_cfg->data_mode == XSPI_SPI_MODE)
867 ? HAL_XSPI_INSTRUCTION_8_BITS
868 : HAL_XSPI_INSTRUCTION_16_BITS)
869 : HAL_XSPI_INSTRUCTION_16_BITS;
870 s_command.Instruction = (dev_cfg->data_rate == XSPI_STR_TRANSFER)
871 ? ((dev_cfg->data_mode == XSPI_SPI_MODE)
872 ? ((stm32_xspi_hal_address_size(dev) ==
873 HAL_XSPI_ADDRESS_24_BITS)
874 ? SPI_NOR_CMD_READ_FAST
875 : SPI_NOR_CMD_READ_FAST_4B)
876 : dev_data->read_opcode)
877 : SPI_NOR_OCMD_DTR_RD;
878 s_command.AddressMode = (dev_cfg->data_rate == XSPI_STR_TRANSFER)
879 ? ((dev_cfg->data_mode == XSPI_SPI_MODE)
880 ? HAL_XSPI_ADDRESS_1_LINE
881 : HAL_XSPI_ADDRESS_8_LINES)
882 : HAL_XSPI_ADDRESS_8_LINES;
883 s_command.AddressDTRMode = (dev_cfg->data_rate == XSPI_STR_TRANSFER)
884 ? HAL_XSPI_ADDRESS_DTR_DISABLE
885 : HAL_XSPI_ADDRESS_DTR_ENABLE;
886 s_command.AddressWidth = (dev_cfg->data_rate == XSPI_STR_TRANSFER)
887 ? stm32_xspi_hal_address_size(dev)
888 : HAL_XSPI_ADDRESS_32_BITS;
889 s_command.DataMode = (dev_cfg->data_rate == XSPI_STR_TRANSFER)
890 ? ((dev_cfg->data_mode == XSPI_SPI_MODE)
891 ? HAL_XSPI_DATA_1_LINE
892 : HAL_XSPI_DATA_8_LINES)
893 : HAL_XSPI_DATA_8_LINES;
894 s_command.DataDTRMode = (dev_cfg->data_rate == XSPI_STR_TRANSFER)
895 ? HAL_XSPI_DATA_DTR_DISABLE
896 : HAL_XSPI_DATA_DTR_ENABLE;
897 s_command.DummyCycles = (dev_cfg->data_rate == XSPI_STR_TRANSFER)
898 ? ((dev_cfg->data_mode == XSPI_SPI_MODE)
899 ? SPI_NOR_DUMMY_RD
900 : SPI_NOR_DUMMY_RD_OCTAL)
901 : SPI_NOR_DUMMY_RD_OCTAL_DTR;
902 s_command.DQSMode = (dev_cfg->data_rate == XSPI_STR_TRANSFER)
903 ? HAL_XSPI_DQS_DISABLE
904 : HAL_XSPI_DQS_ENABLE;
905 #ifdef XSPI_CCR_SIOO
906 s_command.SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD;
907 #endif /* XSPI_CCR_SIOO */
908
909 ret = HAL_XSPI_Command(&dev_data->hxspi, &s_command, HAL_XSPI_TIMEOUT_DEFAULT_VALUE);
910 if (ret != HAL_OK) {
911 LOG_ERR("%d: Failed to set memory map", ret);
912 return -EIO;
913 }
914
915 /* Initialize the program command */
916 s_command.OperationType = HAL_XSPI_OPTYPE_WRITE_CFG;
917 if (dev_cfg->data_rate == XSPI_STR_TRANSFER) {
918 s_command.Instruction = (dev_cfg->data_mode == XSPI_SPI_MODE)
919 ? ((stm32_xspi_hal_address_size(dev) ==
920 HAL_XSPI_ADDRESS_24_BITS)
921 ? SPI_NOR_CMD_PP
922 : SPI_NOR_CMD_PP_4B)
923 : SPI_NOR_OCMD_PAGE_PRG;
924 } else {
925 s_command.Instruction = SPI_NOR_OCMD_PAGE_PRG;
926 }
927 s_command.DQSMode = HAL_XSPI_DQS_DISABLE;
928
929 ret = HAL_XSPI_Command(&dev_data->hxspi, &s_command, HAL_XSPI_TIMEOUT_DEFAULT_VALUE);
930 if (ret != HAL_OK) {
931 LOG_ERR("%d: Failed to set memory mapped", ret);
932 return -EIO;
933 }
934
935 /* Enable the memory-mapping */
936 s_MemMappedCfg.TimeOutActivation = HAL_XSPI_TIMEOUT_COUNTER_DISABLE;
937
938 ret = HAL_XSPI_MemoryMapped(&dev_data->hxspi, &s_MemMappedCfg);
939 if (ret != HAL_OK) {
940 LOG_ERR("%d: Failed to enable memory mapped", ret);
941 return -EIO;
942 }
943
944 LOG_DBG("MemoryMap mode enabled");
945 return 0;
946 }
947
948 /* Function to return true if the octoflash is in MemoryMapped else false */
stm32_xspi_is_memorymap(const struct device * dev)949 static bool stm32_xspi_is_memorymap(const struct device *dev)
950 {
951 struct flash_stm32_xspi_data *dev_data = dev->data;
952
953 return ((READ_BIT(dev_data->hxspi.Instance->CR,
954 XSPI_CR_FMODE) == XSPI_CR_FMODE) ?
955 true : false);
956 }
957
stm32_xspi_abort(const struct device * dev)958 static int stm32_xspi_abort(const struct device *dev)
959 {
960 struct flash_stm32_xspi_data *dev_data = dev->data;
961
962 if (HAL_XSPI_Abort(&dev_data->hxspi) != HAL_OK) {
963 LOG_ERR("XSPI abort failed");
964 return -EIO;
965 }
966
967 return 0;
968 }
969 #endif /* CONFIG_STM32_MEMMAP */
970
971 /*
972 * Function to erase the flash : chip or sector with possible OCTO/SPI and STR/DTR
973 * to erase the complete chip (using dedicated command) :
974 * set size >= flash size
975 * set addr = 0
976 */
flash_stm32_xspi_erase(const struct device * dev,off_t addr,size_t size)977 static int flash_stm32_xspi_erase(const struct device *dev, off_t addr,
978 size_t size)
979 {
980 const struct flash_stm32_xspi_config *dev_cfg = dev->config;
981 struct flash_stm32_xspi_data *dev_data = dev->data;
982 int ret = 0;
983
984 /* Ignore zero size erase */
985 if (size == 0) {
986 return 0;
987 }
988
989 /* Maximise erase size : means the complete chip */
990 if (size > dev_cfg->flash_size) {
991 size = dev_cfg->flash_size;
992 }
993
994 if (!xspi_address_is_valid(dev, addr, size)) {
995 LOG_ERR("Error: address or size exceeds expected values: "
996 "addr 0x%lx, size %zu", (long)addr, size);
997 return -EINVAL;
998 }
999
1000 if (((size % SPI_NOR_SECTOR_SIZE) != 0) && (size < dev_cfg->flash_size)) {
1001 LOG_ERR("Error: wrong sector size 0x%x", size);
1002 return -ENOTSUP;
1003 }
1004
1005 xspi_lock_thread(dev);
1006
1007 #ifdef CONFIG_STM32_MEMMAP
1008 if (stm32_xspi_is_memorymap(dev)) {
1009 /* Abort ongoing transfer to force CS high/BUSY deasserted */
1010 ret = stm32_xspi_abort(dev);
1011 if (ret != 0) {
1012 LOG_ERR("Failed to abort memory-mapped access before erase");
1013 goto erase_end;
1014 }
1015 }
1016 #endif
1017
1018 XSPI_RegularCmdTypeDef cmd_erase = {
1019 .OperationType = HAL_XSPI_OPTYPE_COMMON_CFG,
1020 .AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE,
1021 .DataMode = HAL_XSPI_DATA_NONE,
1022 .DummyCycles = 0U,
1023 .DQSMode = HAL_XSPI_DQS_DISABLE,
1024 .SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD,
1025 };
1026
1027 if (stm32_xspi_mem_ready(dev,
1028 dev_cfg->data_mode, dev_cfg->data_rate) != 0) {
1029 LOG_ERR("Erase failed : flash busy");
1030 goto erase_end;
1031 }
1032
1033 cmd_erase.InstructionMode = (dev_cfg->data_mode == XSPI_OCTO_MODE)
1034 ? HAL_XSPI_INSTRUCTION_8_LINES
1035 : HAL_XSPI_INSTRUCTION_1_LINE;
1036 cmd_erase.InstructionDTRMode = (dev_cfg->data_rate == XSPI_DTR_TRANSFER)
1037 ? HAL_XSPI_INSTRUCTION_DTR_ENABLE
1038 : HAL_XSPI_INSTRUCTION_DTR_DISABLE;
1039 cmd_erase.InstructionWidth = (dev_cfg->data_mode == XSPI_OCTO_MODE)
1040 ? HAL_XSPI_INSTRUCTION_16_BITS
1041 : HAL_XSPI_INSTRUCTION_8_BITS;
1042
1043 while ((size > 0) && (ret == 0)) {
1044
1045 ret = stm32_xspi_write_enable(dev,
1046 dev_cfg->data_mode, dev_cfg->data_rate);
1047 if (ret != 0) {
1048 LOG_ERR("Erase failed : write enable");
1049 break;
1050 }
1051
1052 if (size == dev_cfg->flash_size) {
1053 /* Chip erase */
1054 LOG_DBG("Chip Erase");
1055
1056 cmd_erase.Address = 0;
1057 cmd_erase.Instruction = (dev_cfg->data_mode == XSPI_OCTO_MODE)
1058 ? SPI_NOR_OCMD_BULKE
1059 : SPI_NOR_CMD_BULKE;
1060 cmd_erase.AddressMode = HAL_XSPI_ADDRESS_NONE;
1061 /* Full chip erase (Bulk) command */
1062 xspi_send_cmd(dev, &cmd_erase);
1063
1064 size -= dev_cfg->flash_size;
1065 /* Chip (Bulk) erase started, wait until WEL becomes 0 */
1066 ret = stm32_xspi_mem_erased(dev);
1067 if (ret != 0) {
1068 LOG_ERR("Chip Erase failed");
1069 break;
1070 }
1071 } else {
1072 /* Sector or Block erase depending on the size */
1073 LOG_DBG("Sector/Block Erase");
1074
1075 cmd_erase.AddressMode =
1076 (dev_cfg->data_mode == XSPI_OCTO_MODE)
1077 ? HAL_XSPI_ADDRESS_8_LINES
1078 : HAL_XSPI_ADDRESS_1_LINE;
1079 cmd_erase.AddressDTRMode =
1080 (dev_cfg->data_rate == XSPI_DTR_TRANSFER)
1081 ? HAL_XSPI_ADDRESS_DTR_ENABLE
1082 : HAL_XSPI_ADDRESS_DTR_DISABLE;
1083 cmd_erase.AddressWidth = stm32_xspi_hal_address_size(dev);
1084 cmd_erase.Address = addr;
1085
1086 const struct jesd216_erase_type *erase_types =
1087 dev_data->erase_types;
1088 const struct jesd216_erase_type *bet = NULL;
1089
1090 for (uint8_t ei = 0;
1091 ei < JESD216_NUM_ERASE_TYPES; ++ei) {
1092 const struct jesd216_erase_type *etp =
1093 &erase_types[ei];
1094
1095 if ((etp->exp != 0)
1096 && SPI_NOR_IS_ALIGNED(addr, etp->exp)
1097 && (size >= BIT(etp->exp))
1098 && ((bet == NULL)
1099 || (etp->exp > bet->exp))) {
1100 bet = etp;
1101 cmd_erase.Instruction = bet->cmd;
1102 } else if (bet == NULL) {
1103 /* Use the default sector erase cmd */
1104 if (dev_cfg->data_mode == XSPI_OCTO_MODE) {
1105 cmd_erase.Instruction = SPI_NOR_OCMD_SE;
1106 } else {
1107 cmd_erase.Instruction =
1108 (stm32_xspi_hal_address_size(dev) ==
1109 HAL_XSPI_ADDRESS_32_BITS)
1110 ? SPI_NOR_CMD_SE_4B
1111 : SPI_NOR_CMD_SE;
1112 }
1113 }
1114 /* Avoid using wrong erase type,
1115 * if zero entries are found in erase_types
1116 */
1117 bet = NULL;
1118 }
1119 LOG_DBG("Sector/Block Erase addr 0x%x, asize 0x%x amode 0x%x instr 0x%x",
1120 cmd_erase.Address, cmd_erase.AddressWidth,
1121 cmd_erase.AddressMode, cmd_erase.Instruction);
1122
1123 xspi_send_cmd(dev, &cmd_erase);
1124
1125 if (bet != NULL) {
1126 addr += BIT(bet->exp);
1127 size -= BIT(bet->exp);
1128 } else {
1129 addr += SPI_NOR_SECTOR_SIZE;
1130 size -= SPI_NOR_SECTOR_SIZE;
1131 }
1132
1133 ret = stm32_xspi_mem_ready(dev, dev_cfg->data_mode,
1134 dev_cfg->data_rate);
1135 }
1136
1137 }
1138 /* Ends the erase operation */
1139
1140 erase_end:
1141 xspi_unlock_thread(dev);
1142
1143 return ret;
1144 }
1145
1146 /* Function to read the flash with possible OCTO/SPI and STR/DTR */
flash_stm32_xspi_read(const struct device * dev,off_t addr,void * data,size_t size)1147 static int flash_stm32_xspi_read(const struct device *dev, off_t addr,
1148 void *data, size_t size)
1149 {
1150 const struct flash_stm32_xspi_config *dev_cfg = dev->config;
1151 struct flash_stm32_xspi_data *dev_data = dev->data;
1152 int ret;
1153
1154 if (!xspi_address_is_valid(dev, addr, size)) {
1155 LOG_ERR("Error: address or size exceeds expected values: "
1156 "addr 0x%lx, size %zu", (long)addr, size);
1157 return -EINVAL;
1158 }
1159
1160 /* Ignore zero size read */
1161 if (size == 0) {
1162 return 0;
1163 }
1164
1165 #ifdef CONFIG_STM32_MEMMAP
1166 ARG_UNUSED(dev_cfg);
1167 ARG_UNUSED(dev_data);
1168
1169 xspi_lock_thread(dev);
1170
1171 /* Do reads through memory-mapping instead of indirect */
1172 if (!stm32_xspi_is_memorymap(dev)) {
1173 ret = stm32_xspi_set_memorymap(dev);
1174 if (ret != 0) {
1175 LOG_ERR("READ: failed to set memory mapped");
1176 goto read_end;
1177 }
1178 }
1179
1180 __ASSERT_NO_MSG(stm32_xspi_is_memorymap(dev));
1181
1182 uintptr_t mmap_addr = STM32_XSPI_BASE_ADDRESS + addr;
1183
1184 LOG_DBG("Memory-mapped read from 0x%08lx, len %zu", mmap_addr, size);
1185 memcpy(data, (void *)mmap_addr, size);
1186 ret = 0;
1187 goto read_end;
1188 #else
1189 XSPI_RegularCmdTypeDef cmd = xspi_prepare_cmd(dev_cfg->data_mode, dev_cfg->data_rate);
1190
1191 if (dev_cfg->data_mode != XSPI_OCTO_MODE) {
1192 switch (dev_data->read_mode) {
1193 case JESD216_MODE_112: {
1194 cmd.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE;
1195 cmd.AddressMode = HAL_XSPI_ADDRESS_1_LINE;
1196 cmd.DataMode = HAL_XSPI_DATA_2_LINES;
1197 break;
1198 }
1199 case JESD216_MODE_122: {
1200 cmd.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE;
1201 cmd.AddressMode = HAL_XSPI_ADDRESS_2_LINES;
1202 cmd.DataMode = HAL_XSPI_DATA_2_LINES;
1203 break;
1204 }
1205 case JESD216_MODE_114: {
1206 cmd.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE;
1207 cmd.AddressMode = HAL_XSPI_ADDRESS_1_LINE;
1208 cmd.DataMode = HAL_XSPI_DATA_4_LINES;
1209 break;
1210 }
1211 case JESD216_MODE_144: {
1212 cmd.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE;
1213 cmd.AddressMode = HAL_XSPI_ADDRESS_4_LINES;
1214 cmd.DataMode = HAL_XSPI_DATA_4_LINES;
1215 break;
1216 }
1217 default:
1218 /* use the mode from ospi_prepare_cmd */
1219 break;
1220 }
1221 }
1222
1223 /* Instruction and DummyCycles are set below */
1224 cmd.Address = addr; /* AddressSize is 32bits in OPSI mode */
1225 cmd.AddressWidth = stm32_xspi_hal_address_size(dev);
1226 /* DataSize is set by the read cmd */
1227
1228 /* Configure other parameters */
1229 if (dev_cfg->data_rate == XSPI_DTR_TRANSFER) {
1230 /* DTR transfer rate (==> Octal mode) */
1231 cmd.Instruction = SPI_NOR_OCMD_DTR_RD;
1232 cmd.DummyCycles = SPI_NOR_DUMMY_RD_OCTAL_DTR;
1233 } else {
1234 /* STR transfer rate */
1235 if (dev_cfg->data_mode == XSPI_OCTO_MODE) {
1236 /* OPI and STR */
1237 cmd.Instruction = SPI_NOR_OCMD_RD;
1238 cmd.DummyCycles = SPI_NOR_DUMMY_RD_OCTAL;
1239 } else {
1240 /* use SFDP:BFP read instruction */
1241 cmd.Instruction = dev_data->read_opcode;
1242 cmd.DummyCycles = dev_data->read_dummy;
1243 /* in SPI and STR : expecting SPI_NOR_CMD_READ_FAST_4B */
1244 }
1245 }
1246
1247 LOG_DBG("XSPI: read %zu data at 0x%lx",
1248 size,
1249 (long)(STM32_XSPI_BASE_ADDRESS + addr));
1250 xspi_lock_thread(dev);
1251
1252 ret = xspi_read_access(dev, &cmd, data, size);
1253 goto read_end;
1254 #endif
1255
1256 read_end:
1257 xspi_unlock_thread(dev);
1258
1259 return ret;
1260 }
1261
1262 /* Function to write the flash (page program) : with possible OCTO/SPI and STR/DTR */
flash_stm32_xspi_write(const struct device * dev,off_t addr,const void * data,size_t size)1263 static int flash_stm32_xspi_write(const struct device *dev, off_t addr,
1264 const void *data, size_t size)
1265 {
1266 const struct flash_stm32_xspi_config *dev_cfg = dev->config;
1267 struct flash_stm32_xspi_data *dev_data = dev->data;
1268 size_t to_write;
1269 int ret = 0;
1270
1271 if (!xspi_address_is_valid(dev, addr, size)) {
1272 LOG_ERR("Error: address or size exceeds expected values: "
1273 "addr 0x%lx, size %zu", (long)addr, size);
1274 return -EINVAL;
1275 }
1276
1277 /* Ignore zero size write */
1278 if (size == 0) {
1279 return 0;
1280 }
1281
1282 xspi_lock_thread(dev);
1283
1284 #ifdef CONFIG_STM32_MEMMAP
1285 ARG_UNUSED(dev_data);
1286
1287 if (stm32_xspi_is_memorymap(dev)) {
1288 /* Abort ongoing transfer to force CS high/BUSY deasserted */
1289 ret = stm32_xspi_abort(dev);
1290 if (ret != 0) {
1291 LOG_ERR("Failed to abort memory-mapped access before write");
1292 goto write_end;
1293 }
1294 }
1295 #endif
1296 /* page program for STR or DTR mode */
1297 XSPI_RegularCmdTypeDef cmd_pp = xspi_prepare_cmd(dev_cfg->data_mode, dev_cfg->data_rate);
1298
1299 /* using 32bits address also in SPI/STR mode */
1300 cmd_pp.Instruction = dev_data->write_opcode;
1301
1302 if (dev_cfg->data_mode != XSPI_OCTO_MODE) {
1303 switch (cmd_pp.Instruction) {
1304 case SPI_NOR_CMD_PP_4B:
1305 __fallthrough;
1306 case SPI_NOR_CMD_PP: {
1307 cmd_pp.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE;
1308 cmd_pp.AddressMode = HAL_XSPI_ADDRESS_1_LINE;
1309 cmd_pp.DataMode = HAL_XSPI_DATA_1_LINE;
1310 break;
1311 }
1312 case SPI_NOR_CMD_PP_1_1_4_4B:
1313 __fallthrough;
1314 case SPI_NOR_CMD_PP_1_1_4: {
1315 cmd_pp.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE;
1316 cmd_pp.AddressMode = HAL_XSPI_ADDRESS_1_LINE;
1317 cmd_pp.DataMode = HAL_XSPI_DATA_4_LINES;
1318 break;
1319 }
1320 case SPI_NOR_CMD_PP_1_4_4_4B:
1321 __fallthrough;
1322 case SPI_NOR_CMD_PP_1_4_4: {
1323 cmd_pp.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE;
1324 cmd_pp.AddressMode = HAL_XSPI_ADDRESS_4_LINES;
1325 cmd_pp.DataMode = HAL_XSPI_DATA_4_LINES;
1326 break;
1327 }
1328 default:
1329 /* use the mode from ospi_prepare_cmd */
1330 break;
1331 }
1332 }
1333
1334 cmd_pp.Address = addr;
1335 cmd_pp.AddressWidth = stm32_xspi_hal_address_size(dev);
1336 cmd_pp.DummyCycles = 0U;
1337
1338 LOG_DBG("XSPI: write %zu data at 0x%lx",
1339 size,
1340 (long)(STM32_XSPI_BASE_ADDRESS + addr));
1341
1342 ret = stm32_xspi_mem_ready(dev,
1343 dev_cfg->data_mode, dev_cfg->data_rate);
1344 if (ret != 0) {
1345 LOG_ERR("XSPI: write not ready");
1346 goto write_end;
1347 }
1348
1349 while ((size > 0) && (ret == 0)) {
1350 to_write = size;
1351 ret = stm32_xspi_write_enable(dev,
1352 dev_cfg->data_mode, dev_cfg->data_rate);
1353 if (ret != 0) {
1354 LOG_ERR("XSPI: write not enabled");
1355 break;
1356 }
1357 /* Don't write more than a page. */
1358 if (to_write >= SPI_NOR_PAGE_SIZE) {
1359 to_write = SPI_NOR_PAGE_SIZE;
1360 }
1361
1362 /* Don't write across a page boundary */
1363 if (((addr + to_write - 1U) / SPI_NOR_PAGE_SIZE)
1364 != (addr / SPI_NOR_PAGE_SIZE)) {
1365 to_write = SPI_NOR_PAGE_SIZE -
1366 (addr % SPI_NOR_PAGE_SIZE);
1367 }
1368 cmd_pp.Address = addr;
1369
1370 ret = xspi_write_access(dev, &cmd_pp, data, to_write);
1371 if (ret != 0) {
1372 LOG_ERR("XSPI: write not access");
1373 break;
1374 }
1375
1376 size -= to_write;
1377 data = (const uint8_t *)data + to_write;
1378 addr += to_write;
1379
1380 /* Configure automatic polling mode to wait for end of program */
1381 ret = stm32_xspi_mem_ready(dev,
1382 dev_cfg->data_mode, dev_cfg->data_rate);
1383 if (ret != 0) {
1384 LOG_ERR("XSPI: write PP not ready");
1385 break;
1386 }
1387 }
1388 /* Ends the write operation */
1389
1390 write_end:
1391 xspi_unlock_thread(dev);
1392
1393 return ret;
1394 }
1395
1396 static const struct flash_parameters flash_stm32_xspi_parameters = {
1397 .write_block_size = 1,
1398 .erase_value = 0xff
1399 };
1400
1401 static const struct flash_parameters *
flash_stm32_xspi_get_parameters(const struct device * dev)1402 flash_stm32_xspi_get_parameters(const struct device *dev)
1403 {
1404 ARG_UNUSED(dev);
1405
1406 return &flash_stm32_xspi_parameters;
1407 }
1408
flash_stm32_xspi_isr(const struct device * dev)1409 static void flash_stm32_xspi_isr(const struct device *dev)
1410 {
1411 struct flash_stm32_xspi_data *dev_data = dev->data;
1412
1413 HAL_XSPI_IRQHandler(&dev_data->hxspi);
1414 }
1415
1416 #if !defined(CONFIG_SOC_SERIES_STM32H7X)
1417 /* weak function required for HAL compilation */
HAL_DMA_Abort_IT(DMA_HandleTypeDef * hdma)1418 __weak HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
1419 {
1420 return HAL_OK;
1421 }
1422
1423 /* weak function required for HAL compilation */
HAL_DMA_Abort(DMA_HandleTypeDef * hdma)1424 __weak HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
1425 {
1426 return HAL_OK;
1427 }
1428 #endif /* !CONFIG_SOC_SERIES_STM32H7X */
1429
1430 /* This function is executed in the interrupt context */
1431 #if STM32_XSPI_USE_DMA
xspi_dma_callback(const struct device * dev,void * arg,uint32_t channel,int status)1432 static void xspi_dma_callback(const struct device *dev, void *arg,
1433 uint32_t channel, int status)
1434 {
1435 DMA_HandleTypeDef *hdma = arg;
1436
1437 ARG_UNUSED(dev);
1438
1439 if (status < 0) {
1440 LOG_ERR("DMA callback error with channel %d.", channel);
1441 }
1442
1443 HAL_DMA_IRQHandler(hdma);
1444 }
1445 #endif
1446
1447
1448 /*
1449 * Transfer Error callback.
1450 */
HAL_XSPI_ErrorCallback(XSPI_HandleTypeDef * hxspi)1451 void HAL_XSPI_ErrorCallback(XSPI_HandleTypeDef *hxspi)
1452 {
1453 struct flash_stm32_xspi_data *dev_data =
1454 CONTAINER_OF(hxspi, struct flash_stm32_xspi_data, hxspi);
1455
1456 LOG_DBG("Error cb");
1457
1458 dev_data->cmd_status = -EIO;
1459
1460 k_sem_give(&dev_data->sync);
1461 }
1462
1463 /*
1464 * Command completed callback.
1465 */
HAL_XSPI_CmdCpltCallback(XSPI_HandleTypeDef * hxspi)1466 void HAL_XSPI_CmdCpltCallback(XSPI_HandleTypeDef *hxspi)
1467 {
1468 struct flash_stm32_xspi_data *dev_data =
1469 CONTAINER_OF(hxspi, struct flash_stm32_xspi_data, hxspi);
1470
1471 LOG_DBG("Cmd Cplt cb");
1472
1473 k_sem_give(&dev_data->sync);
1474 }
1475
1476 /*
1477 * Rx Transfer completed callback.
1478 */
HAL_XSPI_RxCpltCallback(XSPI_HandleTypeDef * hxspi)1479 void HAL_XSPI_RxCpltCallback(XSPI_HandleTypeDef *hxspi)
1480 {
1481 struct flash_stm32_xspi_data *dev_data =
1482 CONTAINER_OF(hxspi, struct flash_stm32_xspi_data, hxspi);
1483
1484 LOG_DBG("Rx Cplt cb");
1485
1486 k_sem_give(&dev_data->sync);
1487 }
1488
1489 /*
1490 * Tx Transfer completed callback.
1491 */
HAL_XSPI_TxCpltCallback(XSPI_HandleTypeDef * hxspi)1492 void HAL_XSPI_TxCpltCallback(XSPI_HandleTypeDef *hxspi)
1493 {
1494 struct flash_stm32_xspi_data *dev_data =
1495 CONTAINER_OF(hxspi, struct flash_stm32_xspi_data, hxspi);
1496
1497 LOG_DBG("Tx Cplt cb");
1498
1499 k_sem_give(&dev_data->sync);
1500 }
1501
1502 /*
1503 * Status Match callback.
1504 */
HAL_XSPI_StatusMatchCallback(XSPI_HandleTypeDef * hxspi)1505 void HAL_XSPI_StatusMatchCallback(XSPI_HandleTypeDef *hxspi)
1506 {
1507 struct flash_stm32_xspi_data *dev_data =
1508 CONTAINER_OF(hxspi, struct flash_stm32_xspi_data, hxspi);
1509
1510 LOG_DBG("Status Match cb");
1511
1512 k_sem_give(&dev_data->sync);
1513 }
1514
1515 /*
1516 * Timeout callback.
1517 */
HAL_XSPI_TimeOutCallback(XSPI_HandleTypeDef * hxspi)1518 void HAL_XSPI_TimeOutCallback(XSPI_HandleTypeDef *hxspi)
1519 {
1520 struct flash_stm32_xspi_data *dev_data =
1521 CONTAINER_OF(hxspi, struct flash_stm32_xspi_data, hxspi);
1522
1523 LOG_DBG("Timeout cb");
1524
1525 dev_data->cmd_status = -EIO;
1526
1527 k_sem_give(&dev_data->sync);
1528 }
1529
1530 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
flash_stm32_xspi_pages_layout(const struct device * dev,const struct flash_pages_layout ** layout,size_t * layout_size)1531 static void flash_stm32_xspi_pages_layout(const struct device *dev,
1532 const struct flash_pages_layout **layout,
1533 size_t *layout_size)
1534 {
1535 struct flash_stm32_xspi_data *dev_data = dev->data;
1536
1537 *layout = &dev_data->layout;
1538 *layout_size = 1;
1539 }
1540 #endif
1541
1542 static DEVICE_API(flash, flash_stm32_xspi_driver_api) = {
1543 .read = flash_stm32_xspi_read,
1544 .write = flash_stm32_xspi_write,
1545 .erase = flash_stm32_xspi_erase,
1546 .get_parameters = flash_stm32_xspi_get_parameters,
1547 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
1548 .page_layout = flash_stm32_xspi_pages_layout,
1549 #endif
1550 #if defined(CONFIG_FLASH_JESD216_API)
1551 .sfdp_read = xspi_read_sfdp,
1552 .read_jedec_id = xspi_read_jedec_id,
1553 #endif /* CONFIG_FLASH_JESD216_API */
1554 };
1555
1556 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
setup_pages_layout(const struct device * dev)1557 static int setup_pages_layout(const struct device *dev)
1558 {
1559 const struct flash_stm32_xspi_config *dev_cfg = dev->config;
1560 struct flash_stm32_xspi_data *data = dev->data;
1561 const size_t flash_size = dev_cfg->flash_size;
1562 uint32_t layout_page_size = data->page_size;
1563 uint8_t value = 0;
1564 int rv = 0;
1565
1566 /* Find the smallest erase size. */
1567 for (size_t i = 0; i < ARRAY_SIZE(data->erase_types); ++i) {
1568 const struct jesd216_erase_type *etp = &data->erase_types[i];
1569
1570 if ((etp->cmd != 0)
1571 && ((value == 0) || (etp->exp < value))) {
1572 value = etp->exp;
1573 }
1574 }
1575
1576 uint32_t erase_size = BIT(value);
1577
1578 if (erase_size == 0) {
1579 erase_size = SPI_NOR_SECTOR_SIZE;
1580 }
1581
1582 /* We need layout page size to be compatible with erase size */
1583 if ((layout_page_size % erase_size) != 0) {
1584 LOG_DBG("layout page %u not compatible with erase size %u",
1585 layout_page_size, erase_size);
1586 LOG_DBG("erase size will be used as layout page size");
1587 layout_page_size = erase_size;
1588 }
1589
1590 /* Warn but accept layout page sizes that leave inaccessible
1591 * space.
1592 */
1593 if ((flash_size % layout_page_size) != 0) {
1594 LOG_DBG("layout page %u wastes space with device size %zu",
1595 layout_page_size, flash_size);
1596 }
1597
1598 data->layout.pages_size = layout_page_size;
1599 data->layout.pages_count = flash_size / layout_page_size;
1600 LOG_DBG("layout %u x %u By pages", data->layout.pages_count,
1601 data->layout.pages_size);
1602
1603 return rv;
1604 }
1605 #endif /* CONFIG_FLASH_PAGE_LAYOUT */
1606
stm32_xspi_read_status_register(const struct device * dev,uint8_t reg_num,uint8_t * reg)1607 static int stm32_xspi_read_status_register(const struct device *dev, uint8_t reg_num, uint8_t *reg)
1608 {
1609 XSPI_RegularCmdTypeDef s_command = {
1610 .InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE,
1611 .DataMode = HAL_XSPI_DATA_1_LINE,
1612 };
1613
1614 switch (reg_num) {
1615 case 1U:
1616 s_command.Instruction = SPI_NOR_CMD_RDSR;
1617 break;
1618 case 2U:
1619 s_command.Instruction = SPI_NOR_CMD_RDSR2;
1620 break;
1621 case 3U:
1622 s_command.Instruction = SPI_NOR_CMD_RDSR3;
1623 break;
1624 default:
1625 return -EINVAL;
1626 }
1627
1628 return xspi_read_access(dev, &s_command, reg, sizeof(*reg));
1629 }
1630
stm32_xspi_write_status_register(const struct device * dev,uint8_t reg_num,uint8_t reg)1631 static int stm32_xspi_write_status_register(const struct device *dev, uint8_t reg_num, uint8_t reg)
1632 {
1633 struct flash_stm32_xspi_data *data = dev->data;
1634 XSPI_RegularCmdTypeDef s_command = {
1635 .Instruction = SPI_NOR_CMD_WRSR,
1636 .InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE,
1637 .DataMode = HAL_XSPI_DATA_1_LINE
1638 };
1639 size_t size;
1640 uint8_t regs[4] = { 0 };
1641 uint8_t *regs_p;
1642 int ret;
1643
1644 if (reg_num == 1U) {
1645 size = 1U;
1646 regs[0] = reg;
1647 regs_p = ®s[0];
1648 /* 1 byte write clears SR2, write SR2 as well */
1649 if (data->qer_type == JESD216_DW15_QER_S2B1v1) {
1650 ret = stm32_xspi_read_status_register(dev, 2, ®s[1]);
1651 if (ret < 0) {
1652 return ret;
1653 }
1654 size = 2U;
1655 }
1656 } else if (reg_num == 2U) {
1657 s_command.Instruction = SPI_NOR_CMD_WRSR2;
1658 size = 1U;
1659 regs[1] = reg;
1660 regs_p = ®s[1];
1661 /* if SR2 write needs SR1 */
1662 if ((data->qer_type == JESD216_DW15_QER_VAL_S2B1v1) ||
1663 (data->qer_type == JESD216_DW15_QER_VAL_S2B1v4) ||
1664 (data->qer_type == JESD216_DW15_QER_VAL_S2B1v5)) {
1665 ret = stm32_xspi_read_status_register(dev, 1, ®s[0]);
1666 if (ret < 0) {
1667 return ret;
1668 }
1669 s_command.Instruction = SPI_NOR_CMD_WRSR;
1670 size = 2U;
1671 regs_p = ®s[0];
1672 }
1673 } else if (reg_num == 3U) {
1674 s_command.Instruction = SPI_NOR_CMD_WRSR3;
1675 size = 1U;
1676 regs[2] = reg;
1677 regs_p = ®s[2];
1678 } else {
1679 return -EINVAL;
1680 }
1681
1682 return xspi_write_access(dev, &s_command, regs_p, size);
1683 }
1684
stm32_xspi_enable_qe(const struct device * dev)1685 static int stm32_xspi_enable_qe(const struct device *dev)
1686 {
1687 struct flash_stm32_xspi_data *data = dev->data;
1688 uint8_t qe_reg_num;
1689 uint8_t qe_bit;
1690 uint8_t reg;
1691 int ret;
1692
1693 switch (data->qer_type) {
1694 case JESD216_DW15_QER_NONE:
1695 /* no QE bit, device detects reads based on opcode */
1696 return 0;
1697 case JESD216_DW15_QER_S1B6:
1698 qe_reg_num = 1U;
1699 qe_bit = BIT(6U);
1700 break;
1701 case JESD216_DW15_QER_S2B7:
1702 qe_reg_num = 2U;
1703 qe_bit = BIT(7U);
1704 break;
1705 case JESD216_DW15_QER_S2B1v1:
1706 __fallthrough;
1707 case JESD216_DW15_QER_S2B1v4:
1708 __fallthrough;
1709 case JESD216_DW15_QER_S2B1v5:
1710 __fallthrough;
1711 case JESD216_DW15_QER_S2B1v6:
1712 qe_reg_num = 2U;
1713 qe_bit = BIT(1U);
1714 break;
1715 default:
1716 return -ENOTSUP;
1717 }
1718
1719 ret = stm32_xspi_read_status_register(dev, qe_reg_num, ®);
1720 if (ret < 0) {
1721 return ret;
1722 }
1723
1724 /* exit early if QE bit is already set */
1725 if ((reg & qe_bit) != 0U) {
1726 return 0;
1727 }
1728
1729 ret = stm32_xspi_write_enable(dev, XSPI_SPI_MODE, XSPI_STR_TRANSFER);
1730 if (ret < 0) {
1731 return ret;
1732 }
1733
1734 reg |= qe_bit;
1735
1736 ret = stm32_xspi_write_status_register(dev, qe_reg_num, reg);
1737 if (ret < 0) {
1738 return ret;
1739 }
1740
1741 ret = stm32_xspi_mem_ready(dev, XSPI_SPI_MODE, XSPI_STR_TRANSFER);
1742 if (ret < 0) {
1743 return ret;
1744 }
1745
1746 /* validate that QE bit is set */
1747 ret = stm32_xspi_read_status_register(dev, qe_reg_num, ®);
1748 if (ret < 0) {
1749 return ret;
1750 }
1751
1752 if ((reg & qe_bit) == 0U) {
1753 LOG_ERR("Status Register %u [0x%02x] not set", qe_reg_num, reg);
1754 ret = -EIO;
1755 }
1756
1757 return ret;
1758 }
1759
spi_nor_process_bfp_addrbytes(const struct device * dev,const uint8_t jesd216_bfp_addrbytes)1760 static void spi_nor_process_bfp_addrbytes(const struct device *dev,
1761 const uint8_t jesd216_bfp_addrbytes)
1762 {
1763 struct flash_stm32_xspi_data *data = dev->data;
1764
1765 if ((jesd216_bfp_addrbytes == JESD216_SFDP_BFP_DW1_ADDRBYTES_VAL_4B) ||
1766 (jesd216_bfp_addrbytes == JESD216_SFDP_BFP_DW1_ADDRBYTES_VAL_3B4B)) {
1767 data->address_width = 4U;
1768 } else {
1769 data->address_width = 3U;
1770 }
1771 }
1772
spi_nor_convert_read_to_4b(const uint8_t opcode)1773 static inline uint8_t spi_nor_convert_read_to_4b(const uint8_t opcode)
1774 {
1775 switch (opcode) {
1776 case SPI_NOR_CMD_READ:
1777 return SPI_NOR_CMD_READ_4B;
1778 case SPI_NOR_CMD_DREAD:
1779 return SPI_NOR_CMD_DREAD_4B;
1780 case SPI_NOR_CMD_2READ:
1781 return SPI_NOR_CMD_2READ_4B;
1782 case SPI_NOR_CMD_QREAD:
1783 return SPI_NOR_CMD_QREAD_4B;
1784 case SPI_NOR_CMD_4READ:
1785 return SPI_NOR_CMD_4READ_4B;
1786 default:
1787 /* use provided */
1788 return opcode;
1789 }
1790 }
1791
spi_nor_convert_write_to_4b(const uint8_t opcode)1792 static inline uint8_t spi_nor_convert_write_to_4b(const uint8_t opcode)
1793 {
1794 switch (opcode) {
1795 case SPI_NOR_CMD_PP:
1796 return SPI_NOR_CMD_PP_4B;
1797 case SPI_NOR_CMD_PP_1_1_4:
1798 return SPI_NOR_CMD_PP_1_1_4_4B;
1799 case SPI_NOR_CMD_PP_1_4_4:
1800 return SPI_NOR_CMD_PP_1_4_4_4B;
1801 default:
1802 /* use provided */
1803 return opcode;
1804 }
1805 }
1806
spi_nor_process_bfp(const struct device * dev,const struct jesd216_param_header * php,const struct jesd216_bfp * bfp)1807 static int spi_nor_process_bfp(const struct device *dev,
1808 const struct jesd216_param_header *php,
1809 const struct jesd216_bfp *bfp)
1810 {
1811 const struct flash_stm32_xspi_config *dev_cfg = dev->config;
1812 struct flash_stm32_xspi_data *data = dev->data;
1813 /* must be kept in data mode order, ignore 1-1-1 (always supported) */
1814 const enum jesd216_mode_type supported_read_modes[] = { JESD216_MODE_112, JESD216_MODE_122,
1815 JESD216_MODE_114,
1816 JESD216_MODE_144 };
1817 size_t supported_read_modes_max_idx;
1818 struct jesd216_erase_type *etp = data->erase_types;
1819 size_t idx;
1820 const size_t flash_size = jesd216_bfp_density(bfp) / 8U;
1821 struct jesd216_instr read_instr = { 0 };
1822 struct jesd216_bfp_dw15 dw15;
1823
1824 if (flash_size != dev_cfg->flash_size) {
1825 LOG_DBG("Unexpected flash size: %u", flash_size);
1826 }
1827
1828 LOG_DBG("%s: %u MiBy flash", dev->name, (uint32_t)(flash_size >> 20));
1829
1830 /* Copy over the erase types, preserving their order. (The
1831 * Sector Map Parameter table references them by index.)
1832 */
1833 memset(data->erase_types, 0, sizeof(data->erase_types));
1834 for (idx = 1U; idx <= ARRAY_SIZE(data->erase_types); ++idx) {
1835 if (jesd216_bfp_erase(bfp, idx, etp) == 0) {
1836 LOG_DBG("Erase %u with %02x",
1837 (uint32_t)BIT(etp->exp), etp->cmd);
1838 }
1839 ++etp;
1840 }
1841
1842 spi_nor_process_bfp_addrbytes(dev, jesd216_bfp_addrbytes(bfp));
1843 LOG_DBG("Address width: %u Bytes", data->address_width);
1844
1845 /* use PP opcode based on configured data mode if nothing is set in DTS */
1846 if (data->write_opcode == SPI_NOR_WRITEOC_NONE) {
1847 switch (dev_cfg->data_mode) {
1848 case XSPI_OCTO_MODE:
1849 data->write_opcode = SPI_NOR_OCMD_PAGE_PRG;
1850 break;
1851 case XSPI_QUAD_MODE:
1852 data->write_opcode = SPI_NOR_CMD_PP_1_4_4;
1853 break;
1854 case XSPI_DUAL_MODE:
1855 data->write_opcode = SPI_NOR_CMD_PP_1_1_2;
1856 break;
1857 default:
1858 data->write_opcode = SPI_NOR_CMD_PP;
1859 break;
1860 }
1861 }
1862
1863 if (dev_cfg->data_mode != XSPI_OCTO_MODE) {
1864 /* determine supported read modes, begin from the slowest */
1865 data->read_mode = JESD216_MODE_111;
1866 data->read_opcode = SPI_NOR_CMD_READ;
1867 data->read_dummy = 0U;
1868
1869 if (dev_cfg->data_mode != XSPI_SPI_MODE) {
1870 if (dev_cfg->data_mode == XSPI_DUAL_MODE) {
1871 /* the index of JESD216_MODE_114 in supported_read_modes */
1872 supported_read_modes_max_idx = 2U;
1873 } else {
1874 supported_read_modes_max_idx = ARRAY_SIZE(supported_read_modes);
1875 }
1876
1877 for (idx = 0U; idx < supported_read_modes_max_idx; ++idx) {
1878 if (jesd216_bfp_read_support(php, bfp, supported_read_modes[idx],
1879 &read_instr) < 0) {
1880 /* not supported */
1881 continue;
1882 }
1883
1884 LOG_DBG("Supports read mode: %d, instr: 0x%X",
1885 supported_read_modes[idx], read_instr.instr);
1886 data->read_mode = supported_read_modes[idx];
1887 data->read_opcode = read_instr.instr;
1888 data->read_dummy =
1889 (read_instr.wait_states + read_instr.mode_clocks);
1890 }
1891 }
1892
1893 /* convert 3-Byte opcodes to 4-Byte (if required) */
1894 if (IS_ENABLED(DT_INST_PROP(0, four_byte_opcodes))) {
1895 if (data->address_width != 4U) {
1896 LOG_DBG("4-Byte opcodes require 4-Byte address width");
1897 return -ENOTSUP;
1898 }
1899 data->read_opcode = spi_nor_convert_read_to_4b(data->read_opcode);
1900 data->write_opcode = spi_nor_convert_write_to_4b(data->write_opcode);
1901 }
1902
1903 /* enable quad mode (if required) */
1904 if (dev_cfg->data_mode == XSPI_QUAD_MODE) {
1905 if (jesd216_bfp_decode_dw15(php, bfp, &dw15) < 0) {
1906 /* will use QER from DTS or default (refer to device data) */
1907 LOG_WRN("Unable to decode QE requirement [DW15]");
1908 } else {
1909 /* bypass DTS QER value */
1910 data->qer_type = dw15.qer;
1911 }
1912
1913 LOG_DBG("QE requirement mode: %x", data->qer_type);
1914
1915 if (stm32_xspi_enable_qe(dev) < 0) {
1916 LOG_ERR("Failed to enable QUAD mode");
1917 return -EIO;
1918 }
1919
1920 LOG_DBG("QUAD mode enabled");
1921 }
1922 }
1923
1924 data->page_size = jesd216_bfp_page_size(php, bfp);
1925
1926 LOG_DBG("Page size %u bytes", data->page_size);
1927 LOG_DBG("Flash size %zu bytes", flash_size);
1928 LOG_DBG("Using read mode: %d, instr: 0x%X, dummy cycles: %u",
1929 data->read_mode, data->read_opcode, data->read_dummy);
1930 LOG_DBG("Using write instr: 0x%X", data->write_opcode);
1931
1932 return 0;
1933 }
1934
1935 #if STM32_XSPI_USE_DMA
flash_stm32_xspi_dma_init(DMA_HandleTypeDef * hdma,struct stream * dma_stream)1936 static int flash_stm32_xspi_dma_init(DMA_HandleTypeDef *hdma, struct stream *dma_stream)
1937 {
1938 int ret;
1939 /*
1940 * DMA configuration
1941 * Due to use of XSPI HAL API in current driver,
1942 * both HAL and Zephyr DMA drivers should be configured.
1943 * The required configuration for Zephyr DMA driver should only provide
1944 * the minimum information to inform the DMA slot will be in used and
1945 * how to route callbacks.
1946 */
1947
1948 if (!device_is_ready(dma_stream->dev)) {
1949 LOG_ERR("DMA %s device not ready", dma_stream->dev->name);
1950 return -ENODEV;
1951 }
1952 /* Proceed to the minimum Zephyr DMA driver init of the channel */
1953 dma_stream->cfg.user_data = hdma;
1954 /* HACK: This field is used to inform driver that it is overridden */
1955 dma_stream->cfg.linked_channel = STM32_DMA_HAL_OVERRIDE;
1956 /* Because of the STREAM OFFSET, the DMA channel given here is from 1 - 8 */
1957 ret = dma_config(dma_stream->dev,
1958 (dma_stream->channel + STM32_DMA_STREAM_OFFSET), &dma_stream->cfg);
1959 if (ret != 0) {
1960 LOG_ERR("Failed to configure DMA channel %d",
1961 dma_stream->channel + STM32_DMA_STREAM_OFFSET);
1962 return ret;
1963 }
1964
1965 /* Proceed to the HAL DMA driver init */
1966 if (dma_stream->cfg.source_data_size != dma_stream->cfg.dest_data_size) {
1967 LOG_ERR("DMA Source and destination data sizes not aligned");
1968 return -EINVAL;
1969 }
1970
1971 hdma->Init.SrcDataWidth = DMA_SRC_DATAWIDTH_WORD; /* Fixed value */
1972 hdma->Init.DestDataWidth = DMA_DEST_DATAWIDTH_WORD; /* Fixed value */
1973 hdma->Init.SrcInc = (dma_stream->src_addr_increment)
1974 ? DMA_SINC_INCREMENTED
1975 : DMA_SINC_FIXED;
1976 hdma->Init.DestInc = (dma_stream->dst_addr_increment)
1977 ? DMA_DINC_INCREMENTED
1978 : DMA_DINC_FIXED;
1979 hdma->Init.SrcBurstLength = 4;
1980 hdma->Init.DestBurstLength = 4;
1981 hdma->Init.Priority = table_priority[dma_stream->cfg.channel_priority];
1982 hdma->Init.Direction = table_direction[dma_stream->cfg.channel_direction];
1983 hdma->Init.TransferAllocatedPort = DMA_SRC_ALLOCATED_PORT0 | DMA_SRC_ALLOCATED_PORT1;
1984 hdma->Init.TransferEventMode = DMA_TCEM_BLOCK_TRANSFER;
1985 hdma->Init.Mode = DMA_NORMAL;
1986 hdma->Init.BlkHWRequest = DMA_BREQ_SINGLE_BURST;
1987 hdma->Init.Request = dma_stream->cfg.dma_slot;
1988
1989 /*
1990 * HAL expects a valid DMA channel (not DMAMUX).
1991 * The channel is from 0 to 7 because of the STM32_DMA_STREAM_OFFSET
1992 * in the dma_stm32 driver
1993 */
1994 hdma->Instance = LL_DMA_GET_CHANNEL_INSTANCE(dma_stream->reg,
1995 dma_stream->channel);
1996
1997 /* Initialize DMA HAL */
1998 if (HAL_DMA_Init(hdma) != HAL_OK) {
1999 LOG_ERR("XSPI DMA Init failed");
2000 return -EIO;
2001 }
2002
2003 if (HAL_DMA_ConfigChannelAttributes(hdma, DMA_CHANNEL_NPRIV) != HAL_OK) {
2004 LOG_ERR("XSPI DMA Init failed");
2005 return -EIO;
2006 }
2007
2008 LOG_DBG("XSPI with DMA transfer");
2009 return 0;
2010 }
2011 #endif /* STM32_XSPI_USE_DMA */
2012
2013
flash_stm32_xspi_init(const struct device * dev)2014 static int flash_stm32_xspi_init(const struct device *dev)
2015 {
2016 const struct flash_stm32_xspi_config *dev_cfg = dev->config;
2017 struct flash_stm32_xspi_data *dev_data = dev->data;
2018 uint32_t ahb_clock_freq;
2019 uint32_t prescaler = STM32_XSPI_CLOCK_PRESCALER_MIN;
2020 int ret;
2021
2022 /* The SPI/DTR is not a valid config of data_mode/data_rate according to the DTS */
2023 if ((dev_cfg->data_mode != XSPI_OCTO_MODE)
2024 && (dev_cfg->data_rate == XSPI_DTR_TRANSFER)) {
2025 /* already the right config, continue */
2026 LOG_ERR("XSPI mode SPI|DUAL|QUAD/DTR is not valid");
2027 return -ENOTSUP;
2028 }
2029
2030 /* Signals configuration */
2031 ret = pinctrl_apply_state(dev_cfg->pcfg, PINCTRL_STATE_DEFAULT);
2032 if (ret < 0) {
2033 LOG_ERR("XSPI pinctrl setup failed (%d)", ret);
2034 return ret;
2035 }
2036
2037 if (!device_is_ready(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE))) {
2038 LOG_ERR("clock control device not ready");
2039 return -ENODEV;
2040 }
2041
2042 #ifdef CONFIG_STM32_MEMMAP
2043 /* If MemoryMapped then configure skip init */
2044 if (stm32_xspi_is_memorymap(dev)) {
2045 LOG_DBG("NOR init'd in MemMapped mode\n");
2046 /* Force HAL instance in correct state */
2047 dev_data->hxspi.State = HAL_XSPI_STATE_BUSY_MEM_MAPPED;
2048 return 0;
2049 }
2050 #endif /* CONFIG_STM32_MEMMAP */
2051
2052 if (dev_cfg->pclk_len > 3) {
2053 /* Max 3 domain clock are expected */
2054 LOG_ERR("Could not select %d XSPI domain clock", dev_cfg->pclk_len);
2055 return -EIO;
2056 }
2057
2058 /* Clock configuration */
2059 if (clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
2060 (clock_control_subsys_t) &dev_cfg->pclken[0]) != 0) {
2061 LOG_ERR("Could not enable XSPI clock");
2062 return -EIO;
2063 }
2064 if (clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
2065 (clock_control_subsys_t) &dev_cfg->pclken[0],
2066 &ahb_clock_freq) < 0) {
2067 LOG_ERR("Failed call clock_control_get_rate(pclken)");
2068 return -EIO;
2069 }
2070 /* Alternate clock config for peripheral if any */
2071 if (IS_ENABLED(STM32_XSPI_DOMAIN_CLOCK_SUPPORT) && (dev_cfg->pclk_len > 1)) {
2072 if (clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
2073 (clock_control_subsys_t) &dev_cfg->pclken[1],
2074 NULL) != 0) {
2075 LOG_ERR("Could not select XSPI domain clock");
2076 return -EIO;
2077 }
2078 /*
2079 * Get the clock rate from this one (update ahb_clock_freq)
2080 * TODO: retrieve index in the clocks property where clocks has "xspi-ker"
2081 * Assuming index is 1
2082 */
2083 if (clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
2084 (clock_control_subsys_t) &dev_cfg->pclken[1],
2085 &ahb_clock_freq) < 0) {
2086 LOG_ERR("Failed call clock_control_get_rate(pclken)");
2087 return -EIO;
2088 }
2089 }
2090 /* Clock domain corresponding to the IO-Mgr (XSPIM) */
2091 if (IS_ENABLED(STM32_XSPI_DOMAIN_CLOCK_SUPPORT) && (dev_cfg->pclk_len > 2)) {
2092 if (clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
2093 (clock_control_subsys_t) &dev_cfg->pclken[2]) != 0) {
2094 LOG_ERR("Could not enable XSPI Manager clock");
2095 return -EIO;
2096 }
2097 /* Do NOT Get the clock rate from this one */
2098 }
2099
2100 for (; prescaler <= STM32_XSPI_CLOCK_PRESCALER_MAX; prescaler++) {
2101 uint32_t clk = STM32_XSPI_CLOCK_COMPUTE(ahb_clock_freq, prescaler);
2102
2103 if (clk <= dev_cfg->max_frequency) {
2104 break;
2105 }
2106 }
2107 __ASSERT_NO_MSG(prescaler >= STM32_XSPI_CLOCK_PRESCALER_MIN &&
2108 prescaler <= STM32_XSPI_CLOCK_PRESCALER_MAX);
2109
2110 /* Initialize XSPI HAL structure completely */
2111 dev_data->hxspi.Init.ClockPrescaler = prescaler;
2112 /* The stm32 hal_xspi driver does not reduce DEVSIZE before writing the DCR1 */
2113 dev_data->hxspi.Init.MemorySize = find_lsb_set(dev_cfg->flash_size) - 2;
2114 #if defined(XSPI_DCR2_WRAPSIZE)
2115 dev_data->hxspi.Init.WrapSize = HAL_XSPI_WRAP_NOT_SUPPORTED;
2116 #endif /* XSPI_DCR2_WRAPSIZE */
2117 /* STR mode else Macronix for DTR mode */
2118 if (dev_cfg->data_rate == XSPI_DTR_TRANSFER) {
2119 dev_data->hxspi.Init.MemoryType = HAL_XSPI_MEMTYPE_MACRONIX;
2120 dev_data->hxspi.Init.DelayHoldQuarterCycle = HAL_XSPI_DHQC_ENABLE;
2121 } else {
2122
2123 }
2124 #if STM32_XSPI_DLYB_BYPASSED
2125 dev_data->hxspi.Init.DelayBlockBypass = HAL_XSPI_DELAY_BLOCK_BYPASS;
2126 #else
2127 dev_data->hxspi.Init.DelayBlockBypass = HAL_XSPI_DELAY_BLOCK_ON;
2128 #endif /* STM32_XSPI_DLYB_BYPASSED */
2129
2130
2131 if (HAL_XSPI_Init(&dev_data->hxspi) != HAL_OK) {
2132 LOG_ERR("XSPI Init failed");
2133 return -EIO;
2134 }
2135
2136 LOG_DBG("XSPI Init'd");
2137
2138 #if defined(HAL_XSPIM_IOPORT_1) || defined(HAL_XSPIM_IOPORT_2)
2139 /* XSPI I/O manager init Function */
2140 XSPIM_CfgTypeDef xspi_mgr_cfg;
2141
2142 if (dev_data->hxspi.Instance == XSPI1) {
2143 xspi_mgr_cfg.IOPort = HAL_XSPIM_IOPORT_1;
2144 } else if (dev_data->hxspi.Instance == XSPI2) {
2145 xspi_mgr_cfg.IOPort = HAL_XSPIM_IOPORT_2;
2146 }
2147 xspi_mgr_cfg.nCSOverride = HAL_XSPI_CSSEL_OVR_DISABLED;
2148 xspi_mgr_cfg.Req2AckTime = 1;
2149
2150 if (HAL_XSPIM_Config(&dev_data->hxspi, &xspi_mgr_cfg,
2151 HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
2152 LOG_ERR("XSPI M config failed");
2153 return -EIO;
2154 }
2155
2156 #endif /* XSPIM */
2157
2158 #if defined(DLYB_XSPI1) || defined(DLYB_XSPI2) || defined(DLYB_OCTOSPI1) || defined(DLYB_OCTOSPI2)
2159 /* XSPI delay block init Function */
2160 HAL_XSPI_DLYB_CfgTypeDef xspi_delay_block_cfg = {0};
2161
2162 (void)HAL_XSPI_DLYB_GetClockPeriod(&dev_data->hxspi, &xspi_delay_block_cfg);
2163 /* with DTR, set the PhaseSel/4 (empiric value from stm32Cube) */
2164 xspi_delay_block_cfg.PhaseSel /= 4;
2165
2166 if (HAL_XSPI_DLYB_SetConfig(&dev_data->hxspi, &xspi_delay_block_cfg) != HAL_OK) {
2167 LOG_ERR("XSPI DelayBlock failed");
2168 return -EIO;
2169 }
2170
2171 LOG_DBG("Delay Block Init");
2172 #endif /* DLYB_ */
2173
2174 #if STM32_XSPI_USE_DMA
2175 /* Configure and enable the DMA channels after XSPI config */
2176 static DMA_HandleTypeDef hdma_tx;
2177 static DMA_HandleTypeDef hdma_rx;
2178
2179 if (flash_stm32_xspi_dma_init(&hdma_tx, &dev_data->dma_tx) != 0) {
2180 LOG_ERR("XSPI DMA Tx init failed");
2181 return -EIO;
2182 }
2183
2184 /* The dma_tx handle is hold by the dma_stream.cfg.user_data */
2185 __HAL_LINKDMA(&dev_data->hxspi, hdmatx, hdma_tx);
2186
2187 if (flash_stm32_xspi_dma_init(&hdma_rx, &dev_data->dma_rx) != 0) {
2188 LOG_ERR("XSPI DMA Rx init failed");
2189 return -EIO;
2190 }
2191
2192 /* The dma_rx handle is hold by the dma_stream.cfg.user_data */
2193 __HAL_LINKDMA(&dev_data->hxspi, hdmarx, hdma_rx);
2194
2195 #endif /* CONFIG_USE_STM32_HAL_DMA */
2196 /* Initialize semaphores */
2197 k_sem_init(&dev_data->sem, 1, 1);
2198 k_sem_init(&dev_data->sync, 0, 1);
2199
2200 /* Run IRQ init */
2201 dev_cfg->irq_config(dev);
2202
2203 /* Reset NOR flash memory : still with the SPI/STR config for the NOR */
2204 if (stm32_xspi_mem_reset(dev) != 0) {
2205 LOG_ERR("XSPI reset failed");
2206 return -EIO;
2207 }
2208
2209 LOG_DBG("Reset Mem (SPI/STR)");
2210
2211 /* Check if memory is ready in the SPI/STR mode */
2212 if (stm32_xspi_mem_ready(dev,
2213 XSPI_SPI_MODE, XSPI_STR_TRANSFER) != 0) {
2214 LOG_ERR("XSPI memory not ready");
2215 return -EIO;
2216 }
2217
2218 LOG_DBG("Mem Ready (SPI/STR)");
2219
2220 #if defined(CONFIG_FLASH_JESD216_API)
2221 /* Process with the RDID (jedec read ID) instruction at init and fill jedec_id Table */
2222 ret = stm32_xspi_read_jedec_id(dev);
2223 if (ret != 0) {
2224 LOG_ERR("Read ID failed: %d", ret);
2225 return ret;
2226 }
2227 #endif /* CONFIG_FLASH_JESD216_API */
2228
2229 if (stm32_xspi_config_mem(dev) != 0) {
2230 LOG_ERR("OSPI mode not config'd (%u rate %u)",
2231 dev_cfg->data_mode, dev_cfg->data_rate);
2232 return -EIO;
2233 }
2234
2235 /* Send the instruction to read the SFDP */
2236 const uint8_t decl_nph = 2;
2237 union {
2238 /* We only process BFP so use one parameter block */
2239 uint8_t raw[JESD216_SFDP_SIZE(decl_nph)];
2240 struct jesd216_sfdp_header sfdp;
2241 } u;
2242 const struct jesd216_sfdp_header *hp = &u.sfdp;
2243
2244 ret = xspi_read_sfdp(dev, 0, u.raw, sizeof(u.raw));
2245 if (ret != 0) {
2246 LOG_ERR("SFDP read failed: %d", ret);
2247 return ret;
2248 }
2249
2250 uint32_t magic = jesd216_sfdp_magic(hp);
2251
2252 if (magic != JESD216_SFDP_MAGIC) {
2253 LOG_ERR("SFDP magic %08x invalid", magic);
2254 return -EINVAL;
2255 }
2256
2257 LOG_DBG("%s: SFDP v %u.%u AP %x with %u PH", dev->name,
2258 hp->rev_major, hp->rev_minor, hp->access, 1 + hp->nph);
2259
2260 const struct jesd216_param_header *php = hp->phdr;
2261 const struct jesd216_param_header *phpe = php +
2262 MIN(decl_nph, 1 + hp->nph);
2263
2264 while (php != phpe) {
2265 uint16_t id = jesd216_param_id(php);
2266
2267 LOG_DBG("PH%u: %04x rev %u.%u: %u DW @ %x",
2268 (php - hp->phdr), id, php->rev_major, php->rev_minor,
2269 php->len_dw, jesd216_param_addr(php));
2270
2271 if (id == JESD216_SFDP_PARAM_ID_BFP) {
2272 union {
2273 uint32_t dw[20];
2274 struct jesd216_bfp bfp;
2275 } u2;
2276 const struct jesd216_bfp *bfp = &u2.bfp;
2277
2278 ret = xspi_read_sfdp(dev, jesd216_param_addr(php),
2279 (uint8_t *)u2.dw,
2280 MIN(sizeof(uint32_t) * php->len_dw, sizeof(u2.dw)));
2281 if (ret == 0) {
2282 ret = spi_nor_process_bfp(dev, php, bfp);
2283 }
2284
2285 if (ret != 0) {
2286 LOG_ERR("SFDP BFP failed: %d", ret);
2287 break;
2288 }
2289 }
2290 if (id == JESD216_SFDP_PARAM_ID_4B_ADDR_INSTR) {
2291
2292 if (dev_data->address_width == 4U) {
2293 /*
2294 * Check table 4 byte address instruction table to get supported
2295 * erase opcodes when running in 4 byte address mode
2296 */
2297 union {
2298 uint32_t dw[2];
2299 struct {
2300 uint32_t dummy;
2301 uint8_t type[4];
2302 } types;
2303 } u2;
2304 ret = xspi_read_sfdp(dev, jesd216_param_addr(php),
2305 (uint8_t *)u2.dw,
2306 MIN(sizeof(uint32_t) * php->len_dw, sizeof(u2.dw)));
2307 if (ret != 0) {
2308 break;
2309 }
2310 for (uint8_t ei = 0; ei < JESD216_NUM_ERASE_TYPES; ++ei) {
2311 struct jesd216_erase_type *etp = &dev_data->erase_types[ei];
2312 const uint8_t cmd = u2.types.type[ei];
2313 /* 0xff means not supported */
2314 if (cmd == 0xff) {
2315 etp->exp = 0;
2316 etp->cmd = 0;
2317 } else {
2318 etp->cmd = cmd;
2319 };
2320 }
2321 }
2322 }
2323 ++php;
2324 }
2325
2326 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
2327 ret = setup_pages_layout(dev);
2328 if (ret != 0) {
2329 LOG_ERR("layout setup failed: %d", ret);
2330 return -ENODEV;
2331 }
2332 #endif /* CONFIG_FLASH_PAGE_LAYOUT */
2333
2334 #ifdef CONFIG_STM32_MEMMAP
2335 ret = stm32_xspi_set_memorymap(dev);
2336 if (ret != 0) {
2337 LOG_ERR("Failed to enable memory-mapped mode: %d", ret);
2338 return ret;
2339 }
2340 LOG_INF("Memory-mapped NOR-flash at 0x%lx (0x%x bytes)",
2341 (long)(STM32_XSPI_BASE_ADDRESS),
2342 dev_cfg->flash_size);
2343 #else
2344 LOG_INF("NOR external-flash at 0x%lx (0x%x bytes)",
2345 (long)(STM32_XSPI_BASE_ADDRESS),
2346 dev_cfg->flash_size);
2347 #endif /* CONFIG_STM32_MEMMAP*/
2348 return 0;
2349 }
2350
2351
2352 #if STM32_XSPI_USE_DMA
2353 #define DMA_CHANNEL_CONFIG(node, dir) \
2354 DT_DMAS_CELL_BY_NAME(node, dir, channel_config)
2355
2356 #define XSPI_DMA_CHANNEL_INIT(node, dir, dir_cap, src_dev, dest_dev) \
2357 .dev = DEVICE_DT_GET(DT_DMAS_CTLR(node)), \
2358 .channel = DT_DMAS_CELL_BY_NAME(node, dir, channel), \
2359 .reg = (DMA_TypeDef *)DT_REG_ADDR( \
2360 DT_PHANDLE_BY_NAME(node, dmas, dir)), \
2361 .cfg = { \
2362 .dma_slot = DT_DMAS_CELL_BY_NAME(node, dir, slot), \
2363 .channel_direction = STM32_DMA_CONFIG_DIRECTION( \
2364 DMA_CHANNEL_CONFIG(node, dir)), \
2365 .channel_priority = STM32_DMA_CONFIG_PRIORITY( \
2366 DMA_CHANNEL_CONFIG(node, dir)), \
2367 .dma_callback = xspi_dma_callback, \
2368 }, \
2369 .src_addr_increment = STM32_DMA_CONFIG_##src_dev##_ADDR_INC( \
2370 DMA_CHANNEL_CONFIG(node, dir)), \
2371 .dst_addr_increment = STM32_DMA_CONFIG_##dest_dev##_ADDR_INC( \
2372 DMA_CHANNEL_CONFIG(node, dir)),
2373
2374 #define XSPI_DMA_CHANNEL(node, dir, DIR, src, dest) \
2375 .dma_##dir = { \
2376 COND_CODE_1(DT_DMAS_HAS_NAME(node, dir), \
2377 (XSPI_DMA_CHANNEL_INIT(node, dir, DIR, src, dest)), \
2378 (NULL)) \
2379 },
2380 #else
2381 #define XSPI_DMA_CHANNEL(node, dir, DIR, src, dest)
2382 #endif /* CONFIG_USE_STM32_HAL_DMA */
2383
2384 #define XSPI_FLASH_MODULE(drv_id, flash_id) \
2385 (DT_DRV_INST(drv_id), xspi_nor_flash_##flash_id)
2386
2387 #define DT_WRITEOC_PROP_OR(inst, default_value) \
2388 COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, writeoc), \
2389 (_CONCAT(SPI_NOR_CMD_, DT_STRING_TOKEN(DT_DRV_INST(inst), writeoc))), \
2390 ((default_value)))
2391
2392 #define DT_QER_PROP_OR(inst, default_value) \
2393 COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, quad_enable_requirements), \
2394 (_CONCAT(JESD216_DW15_QER_VAL_, \
2395 DT_STRING_TOKEN(DT_DRV_INST(inst), quad_enable_requirements))), \
2396 ((default_value)))
2397
2398 static void flash_stm32_xspi_irq_config_func(const struct device *dev);
2399
2400 static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(STM32_XSPI_NODE);
2401
2402 PINCTRL_DT_DEFINE(STM32_XSPI_NODE);
2403
2404 static const struct flash_stm32_xspi_config flash_stm32_xspi_cfg = {
2405 .pclken = pclken,
2406 .pclk_len = DT_NUM_CLOCKS(STM32_XSPI_NODE),
2407 .irq_config = flash_stm32_xspi_irq_config_func,
2408 .flash_size = DT_INST_REG_ADDR_BY_IDX(0, 1),
2409 .max_frequency = DT_INST_PROP(0, ospi_max_frequency),
2410 .data_mode = DT_INST_PROP(0, spi_bus_width), /* SPI or OPI */
2411 .data_rate = DT_INST_PROP(0, data_rate), /* DTR or STR */
2412 .pcfg = PINCTRL_DT_DEV_CONFIG_GET(STM32_XSPI_NODE),
2413 #if STM32_XSPI_RESET_GPIO
2414 .reset = GPIO_DT_SPEC_INST_GET(0, reset_gpios),
2415 #endif /* STM32_XSPI_RESET_GPIO */
2416 #if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_ospi_nor), sfdp_bfp)
2417 .sfdp_bfp = DT_INST_PROP(0, sfdp_bfp),
2418 #endif /* sfdp_bfp */
2419 };
2420
2421 static struct flash_stm32_xspi_data flash_stm32_xspi_dev_data = {
2422 .hxspi = {
2423 .Instance = (XSPI_TypeDef *)DT_REG_ADDR(STM32_XSPI_NODE),
2424 .Init = {
2425 .FifoThresholdByte = STM32_XSPI_FIFO_THRESHOLD,
2426 .SampleShifting = (DT_PROP(STM32_XSPI_NODE, ssht_enable)
2427 ? HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE
2428 : HAL_XSPI_SAMPLE_SHIFT_NONE),
2429 .ChipSelectHighTimeCycle = 1,
2430 .ClockMode = HAL_XSPI_CLOCK_MODE_0,
2431 .ChipSelectBoundary = 0,
2432 .MemoryMode = HAL_XSPI_SINGLE_MEM,
2433 #if defined(HAL_XSPIM_IOPORT_1) || defined(HAL_XSPIM_IOPORT_2)
2434 .MemorySelect = ((DT_INST_PROP(0, ncs_line) == 1)
2435 ? HAL_XSPI_CSSEL_NCS1
2436 : HAL_XSPI_CSSEL_NCS2),
2437 #endif
2438 .FreeRunningClock = HAL_XSPI_FREERUNCLK_DISABLE,
2439 #if defined(OCTOSPI_DCR4_REFRESH)
2440 .Refresh = 0,
2441 #endif /* OCTOSPI_DCR4_REFRESH */
2442 },
2443 },
2444 .qer_type = DT_QER_PROP_OR(0, JESD216_DW15_QER_VAL_S1B6),
2445 .write_opcode = DT_WRITEOC_PROP_OR(0, SPI_NOR_WRITEOC_NONE),
2446 .page_size = SPI_NOR_PAGE_SIZE, /* by default, to be updated by sfdp */
2447 #if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_ospi_nor), jedec_id)
2448 .jedec_id = DT_INST_PROP(0, jedec_id),
2449 #endif /* jedec_id */
2450 XSPI_DMA_CHANNEL(STM32_XSPI_NODE, tx, TX, MEMORY, PERIPHERAL)
2451 XSPI_DMA_CHANNEL(STM32_XSPI_NODE, rx, RX, PERIPHERAL, MEMORY)
2452 };
2453
flash_stm32_xspi_irq_config_func(const struct device * dev)2454 static void flash_stm32_xspi_irq_config_func(const struct device *dev)
2455 {
2456 IRQ_CONNECT(DT_IRQN(STM32_XSPI_NODE), DT_IRQ(STM32_XSPI_NODE, priority),
2457 flash_stm32_xspi_isr, DEVICE_DT_INST_GET(0), 0);
2458 irq_enable(DT_IRQN(STM32_XSPI_NODE));
2459 }
2460
2461 DEVICE_DT_INST_DEFINE(0, &flash_stm32_xspi_init, NULL,
2462 &flash_stm32_xspi_dev_data, &flash_stm32_xspi_cfg,
2463 POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
2464 &flash_stm32_xspi_driver_api);
2465
