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/Zephyr-latest/dts/bindings/video/
Despressif,esp32-cam.yaml4 # SPDX-License-Identifier: Apache-2.0
9 compatible: "espressif,esp32-lcd-cam"
11 include: [base.yaml, pinctrl-device.yaml]
19 data-width:
24 invert-byte-order:
26 description: invert byte order in 16bit mode
28 invert-bit-order:
30 description: invert bit order
32 invert-pclk:
34 description: invert pixel clock signal
[all …]
/Zephyr-latest/dts/bindings/input/
Dpixart,pmw3610.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: spi-device.yaml
11 motion-gpios:
12 type: phandle-array
17 reset-gpios:
18 type: phandle-array
22 zephyr,axis-x:
29 zephyr,axis-y:
36 res-cpi:
43 invert-x:
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Dcirque,pinnacle-common.yaml2 # SPDX-License-Identifier: Apache-2.0
7 data-ready-gpios:
8 type: phandle-array
20 - "1x"
21 - "2x"
22 - "3x"
23 - "4x"
25 data-mode:
29 Data output mode in which position is reported. In the relative mode
31 absolute mode absolute coordinates are reported.
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Dpixart,pat912x.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: i2c-device.yaml
11 motion-gpios:
12 type: phandle-array
17 zephyr,axis-x:
23 zephyr,axis-y:
29 res-x-cpi:
35 res-y-cpi:
41 invert-x:
44 Invert X axis values.
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Dpixart,paw32xx.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: spi-device.yaml
11 motion-gpios:
12 type: phandle-array
17 zephyr,axis-x:
24 zephyr,axis-y:
31 res-cpi:
37 invert-x:
40 Invert X axis values.
42 invert-y:
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/Zephyr-latest/boards/shields/lcd_par_s035/
Dlcd_par_s035_8080.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
16 compatible = "zephyr,lvgl-pointer-input";
18 swap-xy;
19 invert-y;
25 gt911_lcd_par_s035: gt911-lcd_par_s035@5d {
28 irq-gpios = <&nxp_lcd_8080_connector 9 GPIO_ACTIVE_HIGH>;
29 reset-gpios = <&nxp_lcd_8080_connector 11 GPIO_ACTIVE_LOW>;
35 #address-cells = <1>;
36 #size-cells = <0>;
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/Zephyr-latest/tests/drivers/build_all/input/
Dapp.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/input/input-event-codes.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
17 #io-channel-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
26 zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
32 gpio-controller;
34 #gpio-cells = <0x2>;
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/Zephyr-latest/dts/bindings/sensor/
Dnxp,lpcmp.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: NXP low-power analog comparator (LPCMP)
8 include: [sensor-device.yaml, pinctrl-device.yaml]
17 enable-output-pin:
22 use-unfiltered-output:
27 enable-output-invert:
30 Decide whether to invert the comparator output.
32 hysteresis-level:
35 - 0
36 - 1
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Despressif,esp32-pcnt.yaml2 # SPDX-License-Identifier: Apache-2.0
6 Espressif's Pulse Counter Mode (PCNT) controller Node
14 Each pulse counter unit has a 16-bit signed counter register.
29 Example: Use PCNT to read a rotary-enconder
38 bias-pull-up;
43 Note: Check espressif,esp32-pinctrl.yaml for complete documentation regarding pinctrl.
48 pinctrl-0 = <&pcnt_default>;
49 pinctrl-names = "default";
51 #address-cells = <1>;
52 #size-cells = <0>;
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/Zephyr-latest/dts/bindings/pinctrl/
Dnxp,rt-iocon-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
17 slew-rate = "normal";
18 drive-strength = "normal";
28 IOCON_SLEWRATE = <slew-rate selection>,
29 IOCON_FULLDRIVE = <drive-strength selection>,
35 drive-open-drain: IOCON_ODENA=1
36 bias-pull-up: IOCON_PUPDENA=1, IOCON_PUPSEL=1
37 bias-pull-down: IOCON_PUPDENA=1, IOCON_PUPSEL=0
38 input-enable: IOCON_IBENA=1
40 compatible: "nxp,rt-iocon-pinctrl"
[all …]
Dnxp,lpc-iocon-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
16 slew-rate = "standard";
24 IOCON_SLEW=<slew-rate selection>,
38 drive-open-drain: IOCON_OD=1
39 bias-pull-up: IOCON_MODE=2
40 bias-pull-down: IOCON_MODE=1
41 drive-push-pull: IOCON_MODE=3
44 IOCON_HYS- set by input-schmitt-enable
45 IOCON_S_MODE- set by nxp,digital-filter
46 IOCON_CLKDIV- set by nxp,filter-clock-div
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Dnxp,s32k3-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
20 #include <nxp/s32/S32K344-257BGA-pinctrl.h>
26 output-enable;
30 input-enable;
40 'bias-pull-up' or 'slew-rate' that will be applied to all the pins defined in
41 'pinmux' array. To enable the input buffer use 'input-enable' and to enable the
42 output buffer use 'output-enable'.
44 To link the pin configurations with UART0 device, use pinctrl-N property in the
45 device node, where 'N' is the zero-based state index (0 is the default state).
49 pinctrl-0 = <&uart0_default>;
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Dnxp,lpc11u6x-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
4 compatible: "nxp,lpc11u6x-pinctrl"
7 - name: base.yaml
8 - name: nxp,lpc-iocon-pinctrl.yaml
9 child-binding:
10 child-binding:
11 property-allowlist:
12 - pinmux
13 - nxp,invert
14 - nxp,analog-mode
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Dnordic,nrf-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
7 node to route UART0 RX to pin P0.1 and enable the pull-up resistor on the
20 /* You can put this in places like a board-pinctrl.dtsi file in
35 /* both P0.3 and P0.4 are configured with pull-up */
36 bias-pull-up;
43 state. You would specify the low-power configuration for the same device
52 include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h header file.
55 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
58 - bias-disable: Disable pull-up/down (default behavior, not required).
59 - bias-pull-up: Enable pull-up resistor.
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/Zephyr-latest/dts/bindings/display/
Dsitronix,st7796s.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: [mipi-dbi-spi-device.yaml, display-controller.yaml]
12 type: uint8-array
15 Frame rate control (partial mode / full colors). The default value should
19 type: uint8-array
22 Frame rate control (idle mode / 8 colors). This property sets the
23 division ratio for internal clocks in idle mode
26 type: uint8-array
29 Frame rate control (partial mode / full colors). This property sets the
30 division ratio for internal clocks in partial mode
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/Zephyr-latest/soc/nxp/lpc/lpc11u6x/
Dsoc.h5 * SPDX-License-Identifier: Apache-2.0
12 * This header file is used to specify and describe board-level aspects for the
30 * [3:4] mode.
32 * [6] invert input.
34 * [10] open-drain mode.
35 * [11:12] digital filter sample mode.
60 * [3:4] mode.
62 * [6] invert input.
63 * [7] analog mode.
66 * [10] open-drain mode.
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/Zephyr-latest/dts/bindings/serial/
Dst,stm32-uart-base.yaml2 # SPDX-License-Identifier: Apache-2.0
5 description: STM32 UART-BASE
8 - name: uart-controller.yaml
9 property-blocklist:
10 - clock-frequency
11 - name: pinctrl-device.yaml
12 - name: reset-device.yaml
13 - name: uart-controller-pin-inversion.yaml
28 single-wire:
31 Enable the single wire half-duplex communication.
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/Zephyr-latest/samples/drivers/led/pwm/boards/
Dmec172xevb_assy6906.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/pwm/pwm.h>
10 * BBLED controller 0 uses GPIO156/LED1 connected to JP71-11
11 * BBLED controller 1 uses GPIO157/LED2 connected to JP71-13
12 * BBLED controller 2 uses GPIO153/LED3 connected to JP71-5
13 * BBLED controller 3 uses GPIO035/PWM8 connected to JP67-19
17 * and implements duty cycle for blink mode as an 8-bit value where 0 is off and
18 * 255 full on. BBLED PWM is 8-bit.
19 * BBLED-PWM driver get cycles API reports 32KHz/256 or 48M/256.
26 compatible = "pwm-leds";
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Dmec15xxevb_assy6853.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/pwm/pwm.h>
10 * BBLED controller 0 uses GPIO156/LED0 connected to JP31-13
11 * BBLED controller 1 uses GPIO157/LED1 connected to JP31-15
12 * BBLED controller 2 uses GPIO153/LED2 connected to JP31-17
15 * and implements duty cycle for blink mode as an 8-bit value where 0 is off and
16 * 255 full on. BBLED PWM is 8-bit.
17 * BBLED-PWM driver get cycles API reports 32KHz/256 or 48M/256.
24 compatible = "pwm-leds";
41 microchip,output-func-invert;
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/Zephyr-latest/include/zephyr/drivers/sensor/
Dmcux_lpcmp.h5 * SPDX-License-Identifier: Apache-2.0
10 * @brief Data structure for the NXP MCUX low-power analog comparator (LPCMP)
56 * LPCMP internal DAC high power mode disabled.
73 /** LPCMP window signal invert. */
75 /** LPCMP window signal invert. */
/Zephyr-latest/drivers/pwm/
Dpwm_sam0_tc.c7 * SPDX-License-Identifier: Apache-2.0
14 * The 8-bit counter operates in Normal PWM (NPWM) mode, it supports pulse width and period
16 * however, it is not suitable for high-precision or low-frequency applications.
18 * The 16-bit counter operates in Match PWM (MPWM) mode to generate the PWM signal.
19 * this mode sacrifices the timer's CC0 channel in order to achieve pulse width modulation.
56 while (regs->COUNT8.SYNCBUSY.reg != 0) { in wait_synchronization()
59 while (regs->COUNT16.SYNCBUSY.reg != 0) { in wait_synchronization()
67 const struct pwm_sam0_config *const cfg = dev->config; in pwm_sam0_get_cycles_per_sec()
69 if (channel >= cfg->channels) { in pwm_sam0_get_cycles_per_sec()
70 return -EINVAL; in pwm_sam0_get_cycles_per_sec()
[all …]
Dpwm_mchp_xec_bbled.c4 * SPDX-License-Identifier: Apache-2.0
33 /* Hardware blink mode equation is Fpwm = Fin / (256 * (LD + 1))
45 /* BBLED PWM mode uses the duty cycle to set the PWM frequency:
51 * Puse_OFF_width = (1/Fpwm) * (256 - duty_cycle) seconds
52 * where duty_cycle is an 8-bit value 0 to 255.
53 * Prescale is derived from DELAY register LOW_DELAY 12-bit field
54 * Duty cycle is derived from LIMITS register MINIMUM 8-bit field
61 * BBLED PWM mode duty cycle specified by 8-bit MIN field of the LIMITS register
140 * DELAY.LO = pre-scaler = [0, 4095]
147 const struct pwm_bbled_xec_config * const cfg = dev->config; in xec_pwmbb_progam_pwm()
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/Zephyr-latest/drivers/dai/intel/ssp/
Ddai-params-intel-ipc3.h4 * SPDX-License-Identifier: Apache-2.0
12 #define DAI_INTEL_IPC3_SSP_FMT_I2S 1 /**< I2S mode */
13 #define DAI_INTEL_IPC3_SSP_FMT_RIGHT_J 2 /**< Right Justified mode */
14 #define DAI_INTEL_IPC3_SSP_FMT_LEFT_J 3 /**< Left Justified mode */
24 #define DAI_INTEL_IPC3_SSP_FMT_IB_NF (3 << 8) /**< invert BCLK + nor FRM */
25 #define DAI_INTEL_IPC3_SSP_FMT_IB_IF (4 << 8) /**< invert BCLK + FRM */
100 /* SSP Configuration Request - SOF_DAI_SSP_CONFIG */
/Zephyr-latest/dts/bindings/comparator/
Dnxp,kinetis-acmp.yaml3 # SPDX-License-Identifier: Apache-2.0
11 compatible = "nxp,kinetis-acmp";
32 pinctrl-0 = <&acmp0_default>;
33 pinctrl-names = "default";
35 positive-mux-input = "IN0";
36 negative-mux-input = "IN1";
39 compatible: "nxp,kinetis-acmp"
42 - base.yaml
43 - pinctrl-device.yaml
52 nxp,enable-output-pin:
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/Zephyr-latest/boards/nxp/rd_rw612_bga/dts/
Dgoworld_16880_lcm.overlay1 #include <zephyr/dt-bindings/spi/spi.h>
10 compatible = "zephyr,lvgl-pointer-input";
12 swap-xy;
13 invert-y;
19 nxp,swap-bytes;
21 nxp,timer0-ratio = <15>;
25 * - R125, R123, R12, R124, R15, R243, R239, R236, R233, R286, R246
27 * - R9, R11, R20, R19, R242, R241, R237, R235, R245
31 * -------------------------------
49 mipi-max-frequency = <23000000>;
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