7  * SPDX-License-Identifier: Apache-2.0
14  * The 8-bit counter operates in Normal PWM (NPWM) mode, it supports pulse width and period
16  * however, it is not suitable for high-precision or low-frequency applications.
18  * The 16-bit counter operates in Match PWM (MPWM) mode to generate the PWM signal.
19  * this mode sacrifices the timer's CC0 channel in order to achieve pulse width modulation.
56 		while (regs->COUNT8.SYNCBUSY.reg != 0) {  in wait_synchronization()
59 		while (regs->COUNT16.SYNCBUSY.reg != 0) {  in wait_synchronization()
67 	const struct pwm_sam0_config *const cfg = dev->config;  in pwm_sam0_get_cycles_per_sec()
69 	if (channel >= cfg->channels) {  in pwm_sam0_get_cycles_per_sec()
70 		return -EINVAL;  in pwm_sam0_get_cycles_per_sec()
73 	*cycles = cfg->freq;  in pwm_sam0_get_cycles_per_sec()
81 	const struct pwm_sam0_config *const cfg = dev->config;  in pwm_sam0_set_cycles()
82 	Tc *regs = cfg->regs;  in pwm_sam0_set_cycles()
83 	uint8_t counter_size = cfg->counter_size;  in pwm_sam0_set_cycles()
86 	bool invert = ((flags & PWM_POLARITY_INVERTED) != 0);  in pwm_sam0_set_cycles()  local
89 	if (channel >= cfg->channels) {  in pwm_sam0_set_cycles()
90 		return -EINVAL;  in pwm_sam0_set_cycles()
93 		return -EINVAL;  in pwm_sam0_set_cycles()
101 		inverted = ((regs->COUNT8.DRVCTRL.vec.INVEN & invert_mask) != 0);  in pwm_sam0_set_cycles()
102 		regs->COUNT8.CCBUF[channel].reg = TC_COUNT8_CCBUF_CCBUF(pulse_cycles);  in pwm_sam0_set_cycles()
103 		regs->COUNT8.PERBUF.reg = TC_COUNT8_PERBUF_PERBUF(period_cycles);  in pwm_sam0_set_cycles()
106 		if (invert != inverted) {  in pwm_sam0_set_cycles()
107 			regs->COUNT8.CTRLA.bit.ENABLE = 0;  in pwm_sam0_set_cycles()
110 			regs->COUNT8.DRVCTRL.vec.INVEN ^= invert_mask;  in pwm_sam0_set_cycles()
111 			regs->COUNT8.CTRLA.bit.ENABLE = 1;  in pwm_sam0_set_cycles()
115 		inverted = ((regs->COUNT16.DRVCTRL.vec.INVEN & invert_mask) != 0);  in pwm_sam0_set_cycles()
116 		regs->COUNT16.CCBUF[0].reg = TC_COUNT16_CCBUF_CCBUF(period_cycles);  in pwm_sam0_set_cycles()
117 		regs->COUNT16.CCBUF[1].reg = TC_COUNT16_CCBUF_CCBUF(pulse_cycles);  in pwm_sam0_set_cycles()
120 		if (invert != inverted) {  in pwm_sam0_set_cycles()
121 			regs->COUNT16.CTRLA.bit.ENABLE = 0;  in pwm_sam0_set_cycles()
124 			regs->COUNT16.DRVCTRL.vec.INVEN ^= invert_mask;  in pwm_sam0_set_cycles()
125 			regs->COUNT16.CTRLA.bit.ENABLE = 1;  in pwm_sam0_set_cycles()
135 	const struct pwm_sam0_config *const cfg = dev->config;  in pwm_sam0_init()
137 	Tc *regs = cfg->regs;  in pwm_sam0_init()
138 	uint8_t counter_size = cfg->counter_size;  in pwm_sam0_init()
142 	GCLK->PCHCTRL[cfg->gclk_id].reg =  in pwm_sam0_init()
144 	*cfg->mclk |= cfg->mclk_mask;  in pwm_sam0_init()
146 	GCLK->CLKCTRL.reg = cfg->gclk_clkctrl_id | GCLK_CLKCTRL_GEN_GCLK0 |  in pwm_sam0_init()
148 	PM->APBCMASK.reg |= cfg->pm_apbcmask;  in pwm_sam0_init()
151 	retval = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);  in pwm_sam0_init()
157 		regs->COUNT8.CTRLA.bit.SWRST = 1;  in pwm_sam0_init()
160 		regs->COUNT8.CTRLA.reg = cfg->prescaler | TC_CTRLA_MODE_COUNT8 |  in pwm_sam0_init()
162 		regs->COUNT8.WAVE.reg = TC_WAVE_WAVEGEN_NPWM;  in pwm_sam0_init()
163 		regs->COUNT8.PER.reg = TC_COUNT8_PER_PER(1);  in pwm_sam0_init()
165 		regs->COUNT8.CTRLA.bit.ENABLE = 1;  in pwm_sam0_init()
168 		regs->COUNT16.CTRLA.bit.SWRST = 1;  in pwm_sam0_init()
171 		regs->COUNT16.CTRLA.reg = cfg->prescaler | TC_CTRLA_MODE_COUNT16 |  in pwm_sam0_init()
173 		regs->COUNT16.WAVE.reg = TC_WAVE_WAVEGEN_MPWM;  in pwm_sam0_init()
174 		regs->COUNT16.CC[0].reg = TC_COUNT16_CC_CC(1);  in pwm_sam0_init()
176 		regs->COUNT16.CTRLA.bit.ENABLE = 1;  in pwm_sam0_init()
177 		wait_synchronization(regs, cfg->counter_size);  in pwm_sam0_init()