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/Zephyr-latest/include/zephyr/dsp/
Dutils.h4 * SPDX-License-Identifier: Apache-2.0
35 * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
40 * @brief Convert a Q7 fixed-point value to a floating-point (float32_t) value with a left shift.
42 * @param src The input Q7 fixed-point value.
43 * @param m The number of bits to left shift the input value (0 to 7).
44 * @return The converted floating-point (float32_t) value.
46 #define Z_SHIFT_Q7_TO_F32(src, m) ((float32_t)(((src << m)) / (float32_t)(1U << 7))) argument
49 * @brief Convert a Q15 fixed-point value to a floating-point (float32_t) value with a left shift.
51 * @param src The input Q15 fixed-point value.
52 * @param m The number of bits to left shift the input value (0 to 15).
[all …]
Dbasicmath_f16.h1 /* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
2 * SPDX-License-Identifier: Apache-2.0
26 * @brief Floating-point vector multiplication.
27 * @param[in] src_a points to the first input vector
28 * @param[in] src_b points to the second input vector
37 * @brief Floating-point vector addition.
38 * @param[in] src_a points to the first input vector
39 * @param[in] src_b points to the second input vector
48 * @brief Floating-point vector subtraction.
49 * @param[in] src_a points to the first input vector
[all …]
Dbasicmath.h1 /* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
2 * SPDX-License-Identifier: Apache-2.0
29 * Element-by-element multiplication of two vectors.
33 * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
44 * @param[in] src_a points to the first input vector
45 * @param[in] src_b points to the second input vector
59 * @param[in] src_a points to the first input vector
60 * @param[in] src_b points to the second input vector
74 * @param[in] src_a points to the first input vector
75 * @param[in] src_b points to the second input vector
[all …]
/Zephyr-latest/include/zephyr/sys/
Dcrc.h9 * SPDX-License-Identifier: Apache-2.0
34 /* Initial value expected to be used at the beginning of the OpenPGP CRC-24 computation. */
37 * The CRC-24 value is stored on a 32-bit value, only the 3 least significant bytes
38 * are meaningful. Use the following mask to only keep the CRC-24 value.
75 * @brief Generic function for computing a CRC-16 without input or output
78 * Compute CRC-16 by passing in the address of the input, the input length
88 * @param src Input bytes for the computation
89 * @param len Length of the input in bytes
93 uint16_t crc16(uint16_t poly, uint16_t seed, const uint8_t *src, size_t len);
96 * @brief Generic function for computing a CRC-16 with input and output
[all …]
Dbase64.h5 * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
6 * SPDX-License-Identifier: Apache-2.0
12 * http://www.apache.org/licenses/LICENSE-2.0
21 * - Removed mbedtls_ prefixes
22 * - Reworked coding style
49 * @param src source buffer
52 * @return 0 if successful, or -ENOMEM if the buffer is too small.
62 int base64_encode(uint8_t *dst, size_t dlen, size_t *olen, const uint8_t *src,
66 * @brief Decode a base64-formatted buffer
71 * @param src source buffer
[all …]
/Zephyr-latest/dts/arm/infineon/cat3/xmc/
Dxmc4500_F100x1024-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/pinctrl/xmc4xxx-pinctrl.h>
10 /omit-if-no-ref/ uart_tx_p0_1_u1c1: uart_tx_p0_1_u1c1 {
13 /omit-if-no-ref/ uart_tx_p0_5_u1c0: uart_tx_p0_5_u1c0 {
16 /omit-if-no-ref/ uart_tx_p1_5_u0c0: uart_tx_p1_5_u0c0 {
19 /omit-if-no-ref/ uart_tx_p1_7_u0c0: uart_tx_p1_7_u0c0 {
22 /omit-if-no-ref/ uart_tx_p2_5_u0c1: uart_tx_p2_5_u0c1 {
25 /omit-if-no-ref/ uart_tx_p2_14_u1c0: uart_tx_p2_14_u1c0 {
28 /omit-if-no-ref/ uart_tx_p3_5_u2c1: uart_tx_p3_5_u2c1 {
31 /omit-if-no-ref/ uart_tx_p3_5_u0c1: uart_tx_p3_5_u0c1 {
[all …]
Dxmc4700_F144x2048-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/pinctrl/xmc4xxx-pinctrl.h>
10 /omit-if-no-ref/ uart_tx_p0_1_u1c1: uart_tx_p0_1_u1c1 {
13 /omit-if-no-ref/ uart_tx_p0_5_u1c0: uart_tx_p0_5_u1c0 {
16 /omit-if-no-ref/ uart_tx_p1_5_u0c0: uart_tx_p1_5_u0c0 {
19 /omit-if-no-ref/ uart_tx_p1_7_u0c0: uart_tx_p1_7_u0c0 {
22 /omit-if-no-ref/ uart_tx_p1_9_u1c1: uart_tx_p1_9_u1c1 {
25 /omit-if-no-ref/ uart_tx_p1_15_u1c0: uart_tx_p1_15_u1c0 {
28 /omit-if-no-ref/ uart_tx_p2_5_u0c1: uart_tx_p2_5_u0c1 {
31 /omit-if-no-ref/ uart_tx_p2_14_u1c0: uart_tx_p2_14_u1c0 {
[all …]
/Zephyr-latest/samples/modules/tflite-micro/tflm_ethosu/src/
Dinference_process.cpp2 * Copyright 2019-2022 Arm Limited and/or its affiliates <open-source-office@arm.com>
4 * SPDX-License-Identifier: Apache-2.0
24 bool copyOutput(const TfLiteTensor &src, InferenceProcess::DataPtr &dst) in copyOutput() argument
30 if (src.bytes > dst.size) { in copyOutput()
31 printk("Tensor size mismatch (bytes): actual=%d, expected%d.\n", src.bytes, in copyOutput()
36 copy(src.data.uint8, src.data.uint8 + src.bytes, static_cast<uint8_t *>(dst.data)); in copyOutput()
37 dst.size = src.bytes; in copyOutput()
71 : name(_name), networkModel(_networkModel), input(_input), output(_output), in InferenceJob()
80 for (auto &it : input) { in invalidate()
97 for (auto &it : input) { in clean()
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/Zephyr-latest/dts/bindings/i2c/
Dinfineon,xmc4xxx-i2c.yaml4 # SPDX-License-Identifier: Apache-2.0
16 compatible = "infineon,xmc4xxx-i2c";
19 pinctrl-0 = <&i2c_scl_p0_13_u1c1 &i2c_sda_p3_15_u1c1>;
20 pinctrl-names = "default";
21 scl-src = "DX1B";
22 sda-src = "DX0A";
25 #address-cells = <1>;
26 #size-cells = <0>;
28 clock-frequency = <I2C_BITRATE_STANDARD>;
35 The pinctrl nodes need to be configured as open-drain and
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/Zephyr-latest/dts/bindings/pinctrl/
Dinfineon,xmc4xxx-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
12 compatible = "infineon,xmc4xxx-uart";
13 pinctrl-0 = <&uart_tx_p0_1_u1c1 &uart_rx_p0_0_u1c1>;
14 pinctrl-names = "default";
15 input-src = "DX0D";
19 pinctrl-0 is the phandle that stores the pin settings for two pins: &uart_tx_p0_1_u1c1
20 and &uart_rx_p0_0_u1c1. These nodes are pre-defined and their naming convention is designed
24 The pre-defined nodes only set the alternate function of the output pin. The
27 to the inherited property-allowlist list from pincfg-node.yaml).
31 #include <zephyr/dt-bindings/pinctrl/xmc4xxx-pinctrl.h>
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/Zephyr-latest/dts/bindings/can/
Dinfineon,xmc4xxx-can-node.yaml2 # SPDX-License-Identifier: Apache-2.0
8 compatible: "infineon,xmc4xxx-can-node"
10 include: ["can-controller.yaml", "pinctrl-device.yaml"]
23 input-src:
24 description: Connects the CAN input line to a specific IO.
28 - "RXDA"
29 - "RXDB"
30 - "RXDC"
31 - "RXDD"
32 - "RXDE"
[all …]
/Zephyr-latest/modules/lvgl/
DCMakeLists.txt5 # SPDX-License-Identifier: Apache-2.0
15 zephyr_include_directories(${LVGL_DIR}/src/)
23 ${LVGL_DIR}/src/core/lv_group.c
24 ${LVGL_DIR}/src/core/lv_obj.c
25 ${LVGL_DIR}/src/core/lv_obj_class.c
26 ${LVGL_DIR}/src/core/lv_obj_draw.c
27 ${LVGL_DIR}/src/core/lv_obj_event.c
28 ${LVGL_DIR}/src/core/lv_obj_id_builtin.c
29 ${LVGL_DIR}/src/core/lv_obj_pos.c
30 ${LVGL_DIR}/src/core/lv_obj_property.c
[all …]
/Zephyr-latest/tests/drivers/uart/uart_async_api/boards/
Dxmc47_relax_kit.overlay1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <zephyr/dt-bindings/dma/infineon-xmc4xxx-dma.h>
6 compatible = "infineon,xmc4xxx-uart";
9 /delete-property/ scl-src;
10 /delete-property/ sda-src;
12 current-speed = <921600>;
14 interrupt-names = "tx", "rx";
16 dma-names = "tx", "rx";
17 pinctrl-0 = <&uart_tx_p3_15_u1c1 &uart_rx_p3_14_u1c1>;
18 pinctrl-names = "default";
[all …]
/Zephyr-latest/boards/infineon/xmc47_relax_kit/
Dxmc47_relax_kit.dts2 * SPDX-License-Identifier: Apache-2.0
8 /dts-v1/;
11 #include <infineon/cat3/xmc/xmc4700_F144x2048-intc.dtsi>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include "xmc47_relax_kit-pinctrl.dtsi"
22 die-temp0 = &die_temp;
23 pwm-led0 = &pwm_led1;
29 compatible = "gpio-leds";
40 compatible = "pwm-leds";
55 zephyr,shell-uart = &usic0ch0;
[all …]
/Zephyr-latest/doc/build/dts/
Dintro-input-output.rst1 .. _devicetree-in-out-files:
3 Input and output files
6 This section describes the input and output files shown in the figure in
7 :ref:`devicetree-scope-purpose` in more detail.
10 :figclass: align-center
12 Devicetree input (green) and output (yellow) files
14 .. _dt-input-files:
16 Input files
19 There are four types of devicetree input files:
21 - sources (``.dts``)
[all …]
/Zephyr-latest/tests/drivers/gpio/gpio_basic_api/
DREADME.txt1 GPIO 2-Pin Test
6 identified through a test-specific devicetree binding in the `dts/`
10 For some boards `src/main.c` may also need to be extended to configure
18 Check GPIO_0 output 2 connected to input 3
19 FATAL output pin not wired to input pin? (out high => in low)
/Zephyr-latest/tests/drivers/input/kbd_matrix/
DCMakeLists.txt1 # SPDX-License-Identifier: Apache-2.0
8 target_include_directories(app PRIVATE ${ZEPHYR_BASE}/drivers/input)
10 FILE(GLOB app_sources src/*.c)
/Zephyr-latest/tests/drivers/input/gpio_kbd_matrix/
DCMakeLists.txt1 # SPDX-License-Identifier: Apache-2.0
8 target_include_directories(app PRIVATE ${ZEPHYR_BASE}/drivers/input)
10 FILE(GLOB app_sources src/*.c)
/Zephyr-latest/subsys/bluetooth/mesh/
Dbrg_cfg.h4 * SPDX-License-Identifier: Apache-2.0
10 /** These are internal APIs. They do not sanitize input params. */
21 * 0 - no entry,
22 * 1 - bridge messages with src as addr1 and dst as addr2
23 * 2 - bridge messages with src as addr1 and dst as addr2 and vice-versa
51 * @brief Iterate over the bridging table to find a matching entry for the given SRC, DST, and
59 * @param src The source address to match.
65 void bt_mesh_brg_cfg_tbl_foreach_subnet(uint16_t src, uint16_t dst, uint16_t net_idx,
/Zephyr-latest/include/zephyr/drivers/interrupt_controller/
Dintc_mchp_xec_ecia.h4 * SPDX-License-Identifier: Apache-2.0
11 * Reference Manuals for MEC152x and MEC172x ARM(r) 32-bit MCUs
26 * @param girq_id is the GIRQ number (8 - 26)
27 * @param src is the interrupt source in the GIRQ (0 - 31)
29 int mchp_xec_ecia_enable(int girq_id, int src);
42 * @param girq_id is the GIRQ number (8 - 26)
43 * @param src is the interrupt source in the GIRQ (0 - 31)
45 int mchp_xec_ecia_disable(int girq_id, int src);
57 typedef void (*mchp_xec_ecia_callback_t) (int girq_id, int src, void *user);
62 * @param girq_id is the GIRQ number (8 - 26)
[all …]
/Zephyr-latest/dts/bindings/counter/
Drenesas,smartbond-timer.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "renesas,smartbond-timer"
14 clock-src:
24 Clock prescaler at the input of the timer
/Zephyr-latest/drivers/clock_control/
Dclock_control_mchp_xec.c4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
30 * 32KHz period counter minimum for pass/fail: 16-bit
31 * 32KHz period counter maximum for pass/fail: 16-bit
32 * 32KHz duty cycle variation max for pass/fail: 16-bit
33 * 32KHz valid count minimum: 8-bit
99 uint32_t RSVD4[(0x00c0 - 0x0094) / 4];
156 #define XEC_CC_VBATR_CS_XTAL_SE BIT(9) /* crystal XTAL2 used as 32KHz input */
192 uint8_t core_clk_div; /* Cortex-M4 clock divider (CPU and NVIC) */
208 pcr->SYS_SLP_CTRL = 0U; in pcr_slp_init()
[all …]
/Zephyr-latest/soc/intel/intel_adsp/common/include/
Dcavs-idc.h4 * SPDX-License-Identifier: Apache-2.0
40 * So you can send a synchronous message from core "src" (where src is
41 * the PRID of the CPU, equal to arch_curr_cpu()->id in Zephyr) to
44 * IDC[src].core[dst].itc = BIT(31) | message;
45 * while (IDC[src].core[dst].itc & BIT(31)) {}
50 * uint32_t my_msg = IDC[dst].core[src].tfc & 0x7fffffff;
51 * IDC[dst].core[src].tfc = BIT(31); // clear high bit to signal completion
53 * And for clarity, at all times and for all cores and all pairs of src/dst:
55 * IDC[src].core[dst].itc == IDC[dst].core[src].tfc
61 * level 2 bit for IDC in the per-core INTCTRL DSP register AND the
[all …]
/Zephyr-latest/dts/bindings/rtc/
Dnxp,irtc.yaml2 # SPDX-License-Identifier: Apache-2.0
9 - name: rtc.yaml
10 - name: rtc-device.yaml
16 clock-src:
20 - 0
21 - 1
23 The input clock select for IRTC.
24 0 <- 16.384 kHz
25 1 <- 32.768 kHz
27 output-clk-en:
[all …]
/Zephyr-latest/dts/bindings/clock/
Dnxp,imx-ccm-fnpll.yaml2 # SPDX-License-Identifier: Apache-2.0
6 formula: Fout = Fin * (loop-div + (numerator/denominator)
8 compatible: "nxp,imx-ccm-fnpll"
10 include: [clock-controller.yaml, base.yaml]
13 "#clock-cells":
16 loop-div:
35 src:
38 description: Sets source for PLL input. SOC specific.

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