Lines Matching +full:input +full:- +full:src

4  * SPDX-License-Identifier: Apache-2.0
40  * So you can send a synchronous message from core "src" (where src is
41  * the PRID of the CPU, equal to arch_curr_cpu()->id in Zephyr) to
44  *     IDC[src].core[dst].itc = BIT(31) | message;
45  *     while (IDC[src].core[dst].itc & BIT(31)) {}
50  *     uint32_t my_msg = IDC[dst].core[src].tfc & 0x7fffffff;
51  *     IDC[dst].core[src].tfc = BIT(31); // clear high bit to signal completion
53  * And for clarity, at all times and for all cores and all pairs of src/dst:
55  *     IDC[src].core[dst].itc == IDC[dst].core[src].tfc
61  * level 2 bit for IDC in the per-core INTCTRL DSP register AND the
63  * form core "src" to core "dst" with:
65  *     IDC[src].busy_int |= BIT(dst)  // Or disable with "&= ~BIT(dst)" of course
89  * level 2-5 interrupts).  The "mask" field shows the current masking
119 #define CAVS_L2_SHA        BIT(16)	/* SHA-256 */
130 #define CAVS_L3_DSPGHIS(n) BIT(n)	/* DSP Gateway Host Input Stream */
134 #define CAVS_L4_DSPGLIS(n) BIT(n)	/* DSP Gateway Link Input Stream */