Lines Matching +full:input +full:- +full:src
4 # SPDX-License-Identifier: Apache-2.0
16 compatible = "infineon,xmc4xxx-i2c";
19 pinctrl-0 = <&i2c_scl_p0_13_u1c1 &i2c_sda_p3_15_u1c1>;
20 pinctrl-names = "default";
21 scl-src = "DX1B";
22 sda-src = "DX0A";
25 #address-cells = <1>;
26 #size-cells = <0>;
28 clock-frequency = <I2C_BITRATE_STANDARD>;
35 The pinctrl nodes need to be configured as open-drain and
39 drive-strength = "strong-sharp-edge";
40 drive-open-drain;
45 drive-strength = "strong-soft-edge";
46 drive-open-drain;
50 compatible: "infineon,xmc4xxx-i2c"
52 include: [i2c-controller.yaml, pinctrl-device.yaml]
59 scl-src:
61 Connects the I2C clock line (USIC DX1 input) to a specific GPIO pin.
62 The USIC DX1 input is a multiplexer which connects to different GPIO pins.
67 - "DX1A"
68 - "DX1B"
69 - "DX1C"
70 - "DX1D"
71 - "DX1E"
72 - "DX1F"
73 - "DX1G"
75 sda-src:
77 Connects the I2C data line (USIC DX0 input) to a specific GPIO pin.
78 The USIC DX0 input is a multiplexer which connects to different GPIO pins.
83 - "DX0A"
84 - "DX0B"
85 - "DX0C"
86 - "DX0D"
87 - "DX0E"
88 - "DX0F"
89 - "DX0G"
100 pinctrl-0:
109 pinctrl-0 = <&i2c_scl_p5_2_u2c0 &i2c_sda_p5_0_u2c0>;
111 The pins should set to open-drain and hwctrl should be disabled.
114 drive-strength = "strong-sharp-edge";
115 drive-open-drain;
119 In the above example, the pin is both an input and output (as is
122 page 18-110, Figure 18-50 for more details).
135 pinctrl-0 = <&i2c_sda_dout0_p3_8_u2c0 &i2c_sda_dx0_p6_5_u2c0
145 to open-drain while the input pins (dx0 and dx1) should not include this setting.
148 drive-strength = "strong-sharp-edge";
149 drive-open-drain;
154 drive-strength = "strong-sharp-edge";
155 drive-open-drain;
159 &i2c_sda_dx0_p6_5_u2c0 { /* will require USIC setting sda-src = DX0D */
163 &i2c_scl_p5_2_u2c0 { /* will require USIC scl-src = DX1A */
169 pinctrl-names: