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/Zephyr-latest/dts/bindings/pwm/
Dnxp,imx-pwm.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,imx-pwm"
8 include: [pwm-controller.yaml, pinctrl-device.yaml, base.yaml]
19 run-in-wait:
24 run-in-debug:
39 - "immediate"
40 - "half-cycle"
41 - "full-cycle"
42 - "half-and-full-cycle"
44 Select how to load the buffered-registers with new values:
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/Zephyr-latest/dts/bindings/memory-controllers/
Drenesas,ra-sdram.yaml2 # SPDX-License-Identifier: Apache-2.0
7 pinctrl-0 = <&sdram_default>;
8 pinctrl-names = "default";
10 auto-refresh-interval = <10>;
11 auto-refresh-count = <8>;
12 precharge-cycle-count = <3>;
13 multiplex-addr-shift = "10-bit";
14 edian-mode = "little-endian";
15 continuous-access;
16 bus-width = "16-bit";
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/Zephyr-latest/dts/bindings/qspi/
Dnxp,s32-qspi.yaml2 # SPDX-License-Identifier: Apache-2.0
10 compatible: "nxp,s32-qspi"
12 include: [base.yaml, pinctrl-device.yaml]
20 "#address-cells":
23 "#size-cells":
26 data-rate:
29 - SDR
30 - DDR
33 - Single Data Rate (SDR): sampling of incoming data occurs on single edges.
34 - Double Data Rate (DDR): sampling of incoming data occurs on both edges.
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/Zephyr-latest/drivers/led_strip/
Dtlc59731.c4 * SPDX-License-Identifier: Apache-2.0
13 * TLC59731 is a 3-Channel, 8-Bit, PWM LED Driver
14 * With Single-Wire Interface (EasySet)
20 * cycle time.
24 * A zero is represented by no additional pulses within a cycle.
26 * (half a cycle) after the first one. We need at least some delay to get to
29 * the cycle. This time can be slightly shorter because the second pulse
30 * already closes the cycle.
99 rgb_write_bit(led_dev, data & BIT((idx--))); in rgb_write_data()
108 const struct tlc59731_cfg *tlc_conf = dev->config; in tlc59731_led_set_color()
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/Zephyr-latest/tests/drivers/pwm/pwm_api/src/
Dtest_pwm.c4 * SPDX-License-Identifier: Apache-2.0
10 * or cycle.
13 * - Test Steps
14 * -# Bind PWM_0 port 0.
15 * -# Set PWM period and pulse using pwm_set_cycles() or pwm_set().
16 * -# Use multimeter or other instruments to measure the output
18 * - Expected Results
19 * -# The output of PWM_OUT_0 will differ according to the value
21 * Always on -> Period : Pulse (1 : 1) -> 3.3V
22 * Half on -> Period : Pulse (2 : 1) -> 1.65V
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/Zephyr-latest/soc/sifive/sifive_freedom/fu700/
Dclock.c4 * SPDX-License-Identifier: Apache-2.0
20 /* HACK to get the '1 full controller clock cycle'. */ in wait_controller_cycle()
26 * - core: to 1GHz PLL (CORE_PLL) from 26MHz oscillator (HFCLK)
27 * - peri: to 250MHz PLL (HFPCLKPLL) from HFCLK
28 * - ddr: to 923MHz PLL (DDRPLL) from HFCLK (half of the data rate)
/Zephyr-latest/drivers/pwm/
Dpwm_rcar.c4 * SPDX-License-Identifier: Apache-2.0
48 #define RCAR_PWM_CNT_CYC_MASK 0x03ff0000 /* PWM Cycle */
50 #define RCAR_PWM_CNT_PH_MASK 0x000003ff /* PWM High-Level Period */
67 return sys_read32(config->reg_addr + offs); in pwm_rcar_read()
72 sys_write32(value, config->reg_addr + offs); in pwm_rcar_write()
109 return -ENOTSUP; in pwm_rcar_update_clk()
116 return -ENOTSUP; in pwm_rcar_update_clk()
121 power--; in pwm_rcar_update_clk()
138 const struct pwm_rcar_cfg *config = dev->config; in pwm_rcar_set_cycles()
143 return -ENOTSUP; in pwm_rcar_set_cycles()
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/Zephyr-latest/doc/project/
Drelease_process.rst6 The Zephyr project releases on a time-based cycle, rather than a feature-driven
10 A time-based release process enables the Zephyr project to provide users with a
12 roughly 4-month release cycle allows the project to coordinate development of
19 - Release tagging procedure:
21 - linear mode on main branch,
22 - release branches for maintenance after release tagging.
23 - Each release period will consist of a development phase followed by a
29 - Development phase: all changes are considered and merged, subject to
31 - Stabilisation phase: the release manager creates a vN-rc1 tag and the tree
33 - CI sees the tag, builds and runs tests; Test teams analyse the report from the
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/Zephyr-latest/drivers/ethernet/
Deth_adin2111_priv.h4 * SPDX-License-Identifier: Apache-2.0
17 /* SPI frequency maximum, based on clock cycle time */
175 /* SPI Header for writing control transaction in half duplex mode */
177 /* SPI Header for writing control transaction with MAC TX register (!) in half duplex mode */
179 /* SPI Header for reading control transaction in half duplex mode */
193 /* Max setting to a max RCA of 255 68-bytes ckunks */
/Zephyr-latest/doc/releases/
Dindex.rst20 Release Life Cycle and Maintenance
27 long term support releases approximately every 2 years. Periodic and non-LTS
39 Support and maintenance for an LTS release stops at least half a year
48 - Currently supported Long Term Support (LTS) release.
50 - The most recent two releases.
58 +-----------------+----------------+---------------+
61 | `Zephyr 2.7.6`_ | 2024-03-01 | 2025-01-26 |
62 +-----------------+----------------+---------------+
63 | `Zephyr 3.7.0`_ | 2024-07-26 | 2027-01-26 |
64 +-----------------+----------------+---------------+
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/Zephyr-latest/dts/bindings/ospi/
Dst,stm32-ospi.yaml2 # SPDX-License-Identifier: Apache-2.0
9 pinctrl-0 = <&octospi_clk_pe9 &octospi_ncs_pe10 &octospi_dqs_pe11
16 dma-names = "tx_rx";
21 compatible: "st,stm32-ospi"
23 include: [base.yaml, pinctrl-device.yaml]
34 pinctrl-0:
37 pinctrl-names:
40 clock-names:
50 - &dma1: dma controller phandle
51 - 5: channel number (0 to Max-Channel minus 1). From 0 to 15 on stm32u5x.
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/Zephyr-latest/doc/services/storage/zms/
Dzms.rst5 Zephyr Memory Storage is a new key-value storage system that is designed to work with all types
6 of non-volatile storage technologies. It supports classical on-chip NOR flash as well as new
12 ZMS divides the memory space into sectors (minimum 2), and each sector is filled with key-value
15 The key-value pair is divided into two parts:
17 - The key part is written in an ATE (Allocation Table Entry) called "ID-ATE" which is stored
19 - The value part is defined as "DATA" and is stored raw starting from the top of the sector
21 Additionally, for each sector we store at the last positions Header-ATEs which are ATEs that
37 .. list-table::
39 :header-rows: 1
41 * - Sector 0 (closed)
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/Zephyr-latest/drivers/spi/
Dspi_xec_qmspi_ldma.c4 * SPDX-License-Identifier: Apache-2.0
20 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
21 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
35 * data bytes will be left shifted by 1. Work-around for SPI Mode 3 is
85 uint8_t width; /* 0(half) 1(single), 2(dual), 4(quad) */
123 return -ETIMEDOUT; in xec_qmspi_spin_yield()
133 * Some QMSPI timing register may be modified by the Boot-ROM OTP
144 taps[0] = regs->TM_TAPS; in qmspi_reset()
145 taps[1] = regs->TM_TAPS_ADJ; in qmspi_reset()
146 taps[2] = regs->TM_TAPS_CTRL; in qmspi_reset()
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Dspi_bitbang.c2 * Copyright (c) 2021 Marc Reilly - Creative Product Design
4 * SPDX-License-Identifier: Apache-2.0
35 if (config->operation & SPI_OP_MODE_SLAVE) { in spi_bitbang_configure()
37 return -ENOTSUP; in spi_bitbang_configure()
40 if (config->operation & (SPI_LINES_DUAL | SPI_LINES_QUAD | SPI_LINES_OCTAL)) { in spi_bitbang_configure()
42 return -ENOTSUP; in spi_bitbang_configure()
45 const int bits = SPI_WORD_SIZE_GET(config->operation); in spi_bitbang_configure()
49 return -ENOTSUP; in spi_bitbang_configure()
52 data->bits = bits; in spi_bitbang_configure()
53 data->dfs = ((data->bits - 1) / 8) + 1; in spi_bitbang_configure()
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Dspi_rpi_pico_pio.c4 * SPDX-License-Identifier: Apache-2.0
56 /* ------------ */
58 /* ------------ */
71 /* ------------ */
73 /* ------------ */
88 /* ------------------- */
90 /* ------------------- */
105 /* ------------------------- */
107 /* ------------------------- */
119 0x0042, /* 3: jmp x--, 2 side 0 */
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/Zephyr-latest/samples/kernel/metairq_dispatch/
DREADME.rst10 priority level to implement "bottom half" style processing
17 Each message has a random (and non-trivial) amount of processing that
21 Messages are accompanied by a timestamp that allows per-message
24 * The cycle time between message creation in the ISR and receipt by
43 priority will experience some load-dependent delays, as the CPU
72 .. zephyr-app-commands::
73 :zephyr-app: samples/kernel/metairq_dispatch
88 (intended) for non-cooperative threads like T2 and T3 which is attributed to delays
92 .. code-block:: console
94 I: Starting Thread0 at priority -2
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/Zephyr-latest/drivers/timer/
Dcc13xx_cc26xx_rtc_timer.c4 * SPDX-License-Identifier: Apache-2.0
10 * TI SimpleLink CC13X2/CC26X2 RTC-based system timer
13 * RTC counts continually in 64-bit mode and timeouts are
33 /* Number of counts per rtc timer cycle */
79 /* assume next never be more than half the maximum 32 bit count value */ in setThreshold()
80 if ((next - now) > (uint32_t)0x80000000) { in setThreshold()
83 } else if ((now + COMPARE_MARGIN - next) < (uint32_t)0x80000000) { in setThreshold()
111 ticks = (currCount - rtc_last) / RTC_COUNTS_PER_TICK; in rtc_isr()
120 /* calculate new 64-bit RTC count for next interrupt */ in rtc_isr()
197 ticks = CLAMP(ticks - 1, 0, (int32_t) MAX_TICKS); in sys_clock_set_timeout()
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Dcortex_m_systick.c4 * SPDX-License-Identifier: Apache-2.0
20 #define MAX_TICKS ((k_ticks_t)(COUNTER_MAX / CYC_PER_TICK) - 1)
25 * reliably" -- it becomes the minimum value of the LOAD register, and
61 * Additions/subtractions/comparisons of 64-bits values on 32-bits systems
63 * cycle_count and announced_cycles is stored in a 32-bit variable before
84 * case because the Cortex-m SysTick is not clocked in the low power
89 /* Cycle counter before entering the idle state. */
102 * re-program the SysTick.LOAD register, in sys_clock_set_timeout().
109 * - reprogramming of SysTick.LOAD must be clearing the SysTick.COUNTER
111 * - ISR must be clearing the 'overflow_cyc' counter.
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Darcv2_timer0.c2 * Copyright (c) 2014-2015 Wind River Systems, Inc.
5 * SPDX-License-Identifier: Apache-2.0
51 #define MAX_TICKS ((COUNTER_MAX / CYC_PER_TICK) - 1)
168 * - reprogramming of LIMIT must be clearing the COUNT
169 * - ISR must be clearing the 'overflow_cycles' counter.
170 * - no more than one counter-wrap has occurred between
171 * - the timer reset or the last time the function was called
172 * - and until the current call of the function is completed.
173 * - the function is invoked with interrupts disabled.
227 dticks = (curr_time - last_time) / CYC_PER_TICK; in timer_int_handler()
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Dnrf_rtc_timer.c2 * Copyright (c) 2016-2021 Nordic Semiconductor ASA
5 * SPDX-License-Identifier: Apache-2.0
29 #define CHAN_COUNT_MAX (RTC1_CC_NUM - (RTC_PRETICK ? 1 : 0))
38 #define COUNTER_MAX (COUNTER_SPAN - 1U)
42 #define MAX_TICKS ((COUNTER_HALF_SPAN - CYC_PER_TICK) / CYC_PER_TICK)
70 return (a - b) & COUNTER_MAX; in counter_sub()
214 -EINVAL : (curr_time + t.ticks); in z_nrf_rtc_timer_get_ticks()
218 result = abs_ticks - curr_tick; in z_nrf_rtc_timer_get_ticks()
221 return -EINVAL; in z_nrf_rtc_timer_get_ticks()
242 * fail with -EINVAL result if @p req_cc is too close to the
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/Zephyr-latest/drivers/counter/
Dcounter_renesas_ra_agt.c4 * SPDX-License-Identifier: Apache-2.0
53 uint32_t cycle_end_ipl; /* Cycle end interrupt priority */
54 IRQn_Type cycle_end_irq; /* Cycle end interrupt */
55 /* Alarm-related data */
74 reg->AGTCR = AGT_AGTCR_START_TIMER; in counter_ra_agt_start()
76 while (!(reg->AGTCR & BIT(R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos)) && likely(--timeout)) in counter_ra_agt_start()
79 return timeout > 0 ? 0 : -EIO; in counter_ra_agt_start()
87 reg->AGTCR = AGT_AGTCR_STOP_TIMER; in counter_ra_agt_stop()
89 while ((reg->AGTCR & BIT(R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos)) && likely(--timeout)) in counter_ra_agt_stop()
92 return timeout > 0 ? 0 : -EIO; in counter_ra_agt_stop()
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/Zephyr-latest/samples/kernel/metairq_dispatch/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
62 m.metairq_latency = k_cycle_get_32() - m.timestamp; in metairq_fn()
103 int64_t d = (int32_t) (array[i] - *mean); in calc_stats()
114 * metairq latency for the very first event of 7-8us. Maybe in record_latencies()
117 if (IS_ENABLED(CONFIG_QEMU_TARGET) && m->seq == 0) { in record_latencies()
125 if (m->seq >= MAX_EVENTS) { in record_latencies()
129 int t = m->target; in record_latencies()
136 stats.mirq_latencies[atomic_inc(&stats.num_mirq)] = m->metairq_latency; in record_latencies()
144 if (m->seq == MAX_EVENTS - 1) { in record_latencies()
154 LOG_INF(" ---------- Latency (cyc) ----------"); in record_latencies()
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/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_espi_iom.h4 * SPDX-License-Identifier: Apache-2.0
38 #define MCHP_ESPI_GBL_CAP1_ALERT_POS 3u /* Read-Only */
63 * EC sets this bit if it can support open-drain ESPI_ALERT#
69 * Read-Only ALERT Open Drain select.
70 * If EC has indicated it can support open-drain ESPI_ALERT# then
71 * the Host can enable open-drain ESPI_ALERT# by sending a configuration
72 * message. This read-only bit reflects the configuration selection.
89 /* Out-of-Band(OOB) Capabilities */
199 * MCHP_ESPI_IO_PC - eSPI IO Peripheral Channel registers @ 0x400F3500
202 /* Peripheral Channel Last Cycle length, type, and tag. */
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/Zephyr-latest/soc/nuvoton/npcx/common/reg/
Dreg_def.h4 * SPDX-License-Identifier: Apache-2.0
20 * must meet the alignment requirement of cortex-m4.
44 __ASSERT(reg == val, "16-bit reg access failed!"); \
50 __ASSERT(reg == val, "32-bit reg access failed!"); \
90 /* 0x102: High-Frequency Reference Divisor I */
92 /* 0x104: High-Frequency Reference Divisor F */
127 /* 0x008 - 0D: Power-Down Control 1 - 6 */
130 /* 0x020 - 21: Power-Down Control 1 - 2 */
133 /* 0x024: Power-Down Control 7 */
137 /* PMC internal inline functions for multi-registers */
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/Zephyr-latest/kernel/
DKconfig3 # Copyright (c) 2014-2015 Wind River Systems, Inc.
4 # SPDX-License-Identifier: Apache-2.0
9 module-str = kernel
13 bool "Multi-threading" if ARCH_HAS_SINGLE_THREAD_SUPPORT
35 K_PRIO_COOP(0) to K_PRIO_COOP(CONFIG_NUM_COOP_PRIORITIES - 1)
39 -CONFIG_NUM_COOP_PRIORITIES to -1
58 to priorities 0 to CONFIG_NUM_PREEMPT_PRIORITIES - 1.
71 default -2 if !PREEMPT_ENABLED
85 default -127
92 int "Number of very-high priority 'preemptor' threads"
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