| /Zephyr-latest/dts/bindings/gpio/ |
| D | ti,boosterpack-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 TI BoosterPack GPIO header
7 GPIO pins exposed as BoosterPack headers on TI LaunchPads.
9 BoosterPack plug-in modules are available in 20 and 40 pin variants. The
10 20 pin variant has two 10 x 1 pin headers and the 40 pin variant has two
11 10 x 2 pin headers. Both variants are compatible and stackable.
13 The pins of the 20 pin variant and the outer row of the 40 pin variant are
14 numbered 1 through 20. The inner rows of the 40 pin variant are numbered 21
17 1 3.3V 21 5V 40 GPIO 20 GND
18 2 Analog 22 GND 39 GPIO 19 GPIO / SPI CS
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| D | ti,tca6424a.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: TI TCA6424A I2C-based GPIO expander
8 include: [gpio-controller.yaml, i2c-device.yaml]
11 int-gpios:
12 type: phandle-array
14 GPIO connected to the controller INT pin. This pin is active-low
15 and open-drain.
17 reset-gpios:
18 type: phandle-array
20 GPIO connected to the controller RESET pin. This pin is active-low.
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| D | microchip,mcp23xxx.yaml | 6 # SPDX-License-Identifier: Apache-2.0
9 include: [gpio-controller.yaml]
12 "#gpio-cells":
15 int-gpios:
16 type: phandle-array
18 GPIO connected to the controller INT pin. This pin is active-low.
20 reset-gpios:
21 type: phandle-array
23 GPIO connected to the controller RESET pin. This pin is active-low.
25 gpio-cells:
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| D | ambiq,gpio.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 Ambiq GPIO provides the GPIO pin mapping for GPIO child nodes.
7 The Ambiq Apollo4x soc designs a single GPIO port with 128 pins.
8 It uses 128 continuous 32-bit registers to configure the GPIO pins.
9 This binding provides a pin mapping to solve the limitation of the maximum
10 32 pins handling in GPIO driver API.
12 The Ambiq Apollo4x soc should define one "ambiq,gpio" parent node in soc
13 devicetree and some child nodes which are compatible with "ambiq,gpio-bank"
16 Here is an example of how a "ambiq,gpio" node can be used with the combined
17 gpio child nodes:
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| D | nxp,pca_series.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: Base binding for PCA series I2C-based GPIO expander
6 include: [gpio-controller.yaml, i2c-device.yaml]
21 # (b) PCAL6534 has 34 GPIO pins in 4x 8-bit port and 1x
22 # 2-bit port. This driver only support 4x 8-bit port.
25 reset-gpios:
26 type: phandle-array
28 Reset GPIO pin (active-low)
29 Left blank if the device does not have reset pin
30 or the pin is not connected in your application.
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| D | atmel,sam0-gpio.yaml | 1 description: SAM0 GPIO PORT node
3 compatible: "atmel,sam0-gpio"
5 include: [gpio-controller.yaml, base.yaml]
11 "#gpio-cells":
14 "#atmel,pin-cells":
20 gpio-cells:
21 - pin
22 - flags
24 atmel,pin-cells:
25 - pin
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| /Zephyr-latest/include/zephyr/drivers/gpio/ |
| D | gpio_emul.h | 4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Backend API for emulated GPIO
16 #include <zephyr/drivers/gpio.h>
23 * @brief Emulated GPIO backend API
24 * @defgroup gpio_emul Emulated GPIO
28 * Behaviour of emulated GPIO is application-defined. As-such, each
31 * - define a Device Tree overlay file to indicate the number of GPIO
33 * - register a callback with the GPIO controller using
35 * - asynchronously call @ref gpio_emul_input_set and / or
36 * @ref gpio_emul_input_set_masked in order to emulate GPIO events
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| /Zephyr-latest/drivers/gpio/ |
| D | gpio_b91.c | 4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/drivers/gpio.h>
12 #include <zephyr/drivers/gpio/gpio_utils.h>
19 /* Get GPIO instance */
21 ((const struct gpio_b91_config *)dev->config)->gpio_base)
23 /* Get GPIO IRQ number defined in dts */
24 #define GET_IRQ_NUM(dev) (((const struct gpio_b91_config *)dev->config)->irq_num)
26 /* Get GPIO IRQ priority defined in dts */
27 #define GET_IRQ_PRIORITY(dev) (((const struct gpio_b91_config *)dev->config)->irq_priority)
29 /* Get GPIO port number: port A - 0, port B - 1, ..., port F - 5 */
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| D | gpio_sifive.c | 2 * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
4 * SPDX-License-Identifier: Apache-2.0
10 * @file GPIO driver for the SiFive Freedom Processor
17 #include <zephyr/drivers/gpio.h>
22 #include <zephyr/drivers/gpio/gpio_utils.h>
26 /* sifive GPIO register-set structure */
51 /* multi-level encoded interrupt corresponding to pin 0 */
63 /* Helper Macros for GPIO */
65 ((const struct gpio_sifive_config * const)(dev)->config)
67 ((volatile struct gpio_sifive_t *)(DEV_GPIO_CFG(dev))->gpio_base_addr)
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| D | gpio_stm32.c | 2 * Copyright (c) 2016 Open-RnD Sp. z o.o.
4 * SPDX-License-Identifier: Apache-2.0
18 #include <zephyr/drivers/gpio.h>
25 #include <zephyr/dt-bindings/gpio/stm32-gpio.h>
29 #include <zephyr/drivers/gpio/gpio_utils.h>
36 * @brief Common GPIO driver for STM32 MCUs.
42 static void gpio_stm32_isr(gpio_port_pins_t pin, void *arg) in gpio_stm32_isr() argument
46 gpio_fire_callbacks(&data->cb, data->dev, pin); in gpio_stm32_isr()
50 * @brief Common gpio flags to custom flags
65 return -ENOTSUP; in gpio_stm32_flags_to_conf()
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| D | gpio_xlnx_ps_bank.c | 2 * Xilinx Processor System MIO / EMIO GPIO controller driver
3 * GPIO bank module
6 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/drivers/gpio.h>
14 #include <zephyr/drivers/gpio/gpio_utils.h>
24 #define DEV_CFG(_dev) ((const struct gpio_xlnx_ps_bank_dev_cfg *)(_dev)->config)
25 #define DEV_DATA(_dev) ((struct gpio_xlnx_ps_bank_dev_data *const)(_dev)->data)
28 * @brief GPIO bank pin configuration function
30 * Configures an individual pin within a MIO / EMIO GPIO pin bank.
31 * The following flags specified by the GPIO subsystem are NOT
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| D | gpio_shell.c | 6 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/drivers/gpio.h>
20 #define NGPIOS_UNKNOWN -1
23 /* Pin syntax maximum length */
38 gpio_pin_t pin; member
41 * Find idx-th pin reference from the set of non reserved
42 * pin numbers and provided line names.
50 gpio_pin_t pin; in port_pin_get() local
53 entry->handler = NULL; in port_pin_get()
55 /* Find allowed numeric pin reference */ in port_pin_get()
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| D | gpio_mchp_mss.c | 4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/drivers/gpio.h>
16 #include <zephyr/drivers/gpio/gpio_utils.h>
61 /* Helper Macros for GPIO */
63 ((const struct mss_gpio_config * const)(dev)->config)
65 ((volatile struct mss_gpio_t *)(DEV_GPIO_CFG(dev))->gpio_base_addr)
67 ((struct mss_gpio_data *)(dev)->data)
71 gpio_pin_t pin, in mss_gpio_config() argument
74 volatile struct mss_gpio_t *gpio = DEV_GPIO(dev); in mss_gpio_config() local
79 return -ENOTSUP; in mss_gpio_config()
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| /Zephyr-latest/dts/bindings/sdhc/ |
| D | espressif,esp32-sdhc-slot.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "espressif,esp32-sdhc-slot"
8 include: [sdhc.yaml, pinctrl-device.yaml]
14 pinctrl-0:
17 pinctrl-names:
20 bus-width:
23 - 1
24 - 4
28 clk-pin:
31 Clock pin for ESP32 and SoC models with fixed pins for SDIO.
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| /Zephyr-latest/soc/atmel/sam/common/ |
| D | soc_sam4l_gpio.c | 3 * SPDX-License-Identifier: Apache-2.0
7 * @brief Atmel SAM MCU family General-Purpose Input/Output Controller (GPIO)
14 static void configure_common_attr(volatile Gpio *gpio, in configure_common_attr() argument
19 /* Disable interrupts on the pin(s) */ in configure_common_attr()
20 gpio->IERC = mask; in configure_common_attr()
22 /* Configure pull-up(s) */ in configure_common_attr()
24 gpio->PUERS = mask; in configure_common_attr()
26 gpio->PUERC = mask; in configure_common_attr()
29 /* Configure pull-down(s) */ in configure_common_attr()
31 gpio->PDERS = mask; in configure_common_attr()
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| /Zephyr-latest/soc/nuvoton/npcx/common/ |
| D | soc_gpio.h | 4 * SPDX-License-Identifier: Apache-2.0
16 /* Pin number for each GPIO device */
20 * @brief Get GPIO device instance by port index
22 * @param port GPIO device index
25 * @retval NULL Invalid parameter of GPIO port index
30 * @brief Enable the connection between io pads and GPIO instance
32 * @param dev Pointer to device structure for the gpio driver instance.
33 * @param pin Pin number.
35 void npcx_gpio_enable_io_pads(const struct device *dev, int pin);
38 * @brief Disable the connection between io pads and GPIO instance
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| /Zephyr-latest/samples/basic/custom_dts_binding/ |
| D | README.rst | 1 .. zephyr:code-sample:: gpio-custom-dts-binding
2 :name: GPIO with custom Devicetree binding
3 :relevant-api: gpio_interface devicetree-generic-id devicetree-generic-exist
5 Use custom Devicetree binding to control a GPIO.
10 In Zephyr, all hardware-specific configuration is described in the devicetree.
12 Consequently, also GPIO pins are configured in the devicetree and assigned to a specific purpose
16 output) of a GPIO pin is configured in the application firmware.
18 For typical use cases like LEDs or buttons, the existing :dtcompatible:`gpio-leds` or
19 :dtcompatible:`gpio-keys` compatibles can be used.
21 This sample demonstrates how to use a GPIO pin for other purposes with a custom devicetree binding.
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| /Zephyr-latest/boards/nordic/nrf9160dk/ |
| D | board.c | 2 * Copyright (c) 2018-2021 Nordic Semiconductor ASA.
4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/drivers/gpio.h>
27 /* If the GPIO pin selected to be the reset line is actually the pin that
29 * provide any additional GPIO configuration for it.
39 const struct device *gpio; member
40 gpio_pin_t pin; member
53 .gpio = GET_DEV(_name, control_gpios, _idx), \
54 .pin = GET_PIN(_name, control_gpios, _idx), \
65 DT_PHA_HAS_CELL_AT_IDX(DT_NODELABEL(_name), control_gpios, 1, pin)
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| /Zephyr-latest/dts/bindings/mipi-dbi/ |
| D | nxp,mipi-dbi-flexio-lcdif.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,mipi-dbi-flexio-lcdif"
8 include: [mipi-dbi-controller.yaml, base.yaml, pinctrl-device.yaml]
11 shifters-count:
17 timers-count:
23 enwr-pin:
27 Pin select for WR(8080 mode), EN(6800 mode).
29 rd-pin:
32 Pin select for RD(8080 mode), not used in 6800 mode.
34 data-pin-start:
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| /Zephyr-latest/drivers/pinctrl/ |
| D | pinctrl_ite_it8xxx2.c | 4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/drivers/gpio.h>
22 /* gpio port control register (byte mapping to pin) */
46 * KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio control register
47 * (bit mapping to pin)
53 * KSO push-pull/open-drain bit of KSO[15:0] control register
67 struct pinctrl_it8xxx2_gpio gpio; member
74 const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config; in pinctrl_it8xxx2_set()
75 const struct pinctrl_it8xxx2_gpio *gpio = &(pinctrl_config->gpio); in pinctrl_it8xxx2_set() local
76 uint32_t pincfg = pins->pincfg; in pinctrl_it8xxx2_set()
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| /Zephyr-latest/dts/bindings/pinctrl/ |
| D | silabs,dbus-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 The Silabs pin controller is a singleton node responsible for controlling
6 pin function selection and pin properties. For example, you can use this
7 node to route USART0 RX to pin PA1 and enable the pull-up resistor on the
8 pin. This pin controller is used for devices that use DBUS (Digital Bus)
15 compatible = "silabs,gecko-usart";
16 pinctrl-0 = <&usart0_default>;
17 pinctrl-names = "default";
20 pinctrl-0 is a phandle that stores the pin settings for the peripheral, in
22 'pinctrl' node, typically in a board-pinctrl.dtsi file in the board
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| D | st,stm32-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Pin controller Node
6 Based on pincfg-node.yaml binding.
8 Note: `bias-disable` and `drive-push-pull` are default pin configurations.
9 They will be applied in case no `bias-foo` or `driver-bar` properties
12 compatible: "st,stm32-pinctrl"
20 remap-pa11:
22 description: Remaps the PA11 pin to operate as PA9 pin.
25 remap-pa12:
27 description: Remaps the PA12 pin to operate as PA10 pin.
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| D | adi,max32-pinctrl.yaml | 1 # Copyright (c) 2023-2024 Analog Devices, Inc.
2 # SPDX-License-Identifier: Apache-2.0
5 MAX32 Pin controller Node
6 Based on pincfg-node.yaml binding.
8 Note: `bias-disable` are default pin configurations.
10 compatible: "adi,max32-pinctrl"
19 child-binding:
24 - name: pincfg-node.yaml
25 property-allowlist:
26 - bias-disable
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| /Zephyr-latest/include/zephyr/drivers/ |
| D | gpio.h | 2 * Copyright (c) 2019-2020 Nordic Semiconductor ASA
5 * Copyright (c) 2015-2016 Intel Corporation.
7 * SPDX-License-Identifier: Apache-2.0
12 * @brief Public APIs for GPIO drivers
27 #include <zephyr/dt-bindings/gpio/gpio.h>
34 * @brief GPIO Driver APIs
35 * @defgroup gpio_interface GPIO Driver APIs
43 * @name GPIO input/output configuration flags
47 /** Enables pin as input. */
50 /** Enables pin as output, no change to the output state. */
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| /Zephyr-latest/soc/st/stm32/common/ |
| D | stm32_wkup_pins.c | 4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/drivers/gpio.h>
19 #include <zephyr/dt-bindings/power/stm32_pwr.h>
42 * @brief flags for wake-up pin polarity configuration
46 /* detection of wake-up event on the high level : rising edge */
48 /* detection of wake-up event on the low level : falling edge */
54 * @brief flags for configuration of pull-ups & pull-downs of GPIO ports
55 * that are associated with wake-up pins
66 * @brief Structure for storing the devicetree configuration of a wake-up pin.
71 /* GPIO pin(s) associated with wake-up pin */
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