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/Zephyr-latest/drivers/gpio/
Dgpio_xlnx_ps_bank.c2 * Xilinx Processor System MIO / EMIO GPIO controller driver
3 * GPIO bank module
6 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/drivers/gpio.h>
14 #include <zephyr/drivers/gpio/gpio_utils.h>
24 #define DEV_CFG(_dev) ((const struct gpio_xlnx_ps_bank_dev_cfg *)(_dev)->config)
25 #define DEV_DATA(_dev) ((struct gpio_xlnx_ps_bank_dev_data *const)(_dev)->data)
28 * @brief GPIO bank pin configuration function
30 * Configures an individual pin within a MIO / EMIO GPIO pin bank.
31 * The following flags specified by the GPIO subsystem are NOT
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Dgpio_xlnx_ps.c2 * Xilinx Processor System MIO / EMIO GPIO controller driver
6 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/drivers/gpio.h>
12 #include <zephyr/drivers/gpio/gpio_utils.h>
23 #define DEV_CFG(_dev) ((const struct gpio_xlnx_ps_dev_cfg *)(_dev)->config)
24 #define DEV_DATA(_dev) ((struct gpio_xlnx_ps_dev_data *const)(_dev)->data)
30 static DEVICE_API(gpio, gpio_xlnx_ps_default_apis);
33 * @brief Initialize a Xilinx PS GPIO controller parent device
35 * Initialize a Xilinx PS GPIO controller parent device, whose task it is
37 * status and data acquisition of each MIO / EMIO GPIO pin associated with
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Dgpio_xlnx_ps_bank.h2 * Xilinx Processor System MIO / EMIO GPIO controller driver
4 * Driver private data declarations, GPIO bank module
7 * SPDX-License-Identifier: Apache-2.0
15 * Register address offsets: comp. Zynq-7000 TRM, ug585, chap. B.19
17 #define GPIO_XLNX_PS_BANK_MASK_DATA_LSW_REG (dev_data->base\
18 + ((uint32_t)dev_conf->bank_index * 0x8))
19 #define GPIO_XLNX_PS_BANK_MASK_DATA_MSW_REG ((dev_data->base + 0x04)\
20 + ((uint32_t)dev_conf->bank_index * 0x8))
21 #define GPIO_XLNX_PS_BANK_DATA_REG ((dev_data->base + 0x40)\
22 + ((uint32_t)dev_conf->bank_index * 0x4))
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Dgpio_adp5585.c4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/drivers/gpio.h>
9 #include <zephyr/drivers/gpio/gpio_utils.h>
69 const struct adp5585_gpio_config *cfg = dev->config; in gpio_adp5585_config()
70 struct adp5585_gpio_data *data = dev->data; in gpio_adp5585_config()
72 (struct mfd_adp5585_config *)(cfg->mfd_dev->config); in gpio_adp5585_config()
73 struct mfd_adp5585_data *parent_data = (struct mfd_adp5585_data *)(cfg->mfd_dev->data); in gpio_adp5585_config()
78 /* ADP5585 has non-contiguous gpio pin layouts, account for this */ in gpio_adp5585_config()
79 if ((pin & cfg->common.port_pin_mask) == 0) { in gpio_adp5585_config()
81 return -ENOTSUP; in gpio_adp5585_config()
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/Zephyr-latest/dts/bindings/gpio/
Dxlnx,ps-gpio.yaml3 # SPDX-License-Identifier: Apache-2.0
7 Xilinx Zynq-7000/ZynqMP MIO/EMIO GPIO controller node.
9 This GPIO controller is contained in both the Xilinx Zynq-7000 and
11 which can be mapped in the system design tools (MIO pins), or SoC-
16 of available GPIO pins differs between the two SoC families:
18 Zynq-7000 (comp. Zynq-7000 TRM, chap. 14.1.2, p. 381):
19 * Bank 0: MIO pins [31:00]
20 * Bank 1: MIO pins [53:32] (total: 54 MIO pins)
21 * Bank 2: EMIO pins [31:00]
22 * Bank 3: EMIO pins [63:32] (total: 64 EMIO pins)
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Dambiq,gpio.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Ambiq GPIO provides the GPIO pin mapping for GPIO child nodes.
7 The Ambiq Apollo4x soc designs a single GPIO port with 128 pins.
8 It uses 128 continuous 32-bit registers to configure the GPIO pins.
10 32 pins handling in GPIO driver API.
12 The Ambiq Apollo4x soc should define one "ambiq,gpio" parent node in soc
13 devicetree and some child nodes which are compatible with "ambiq,gpio-bank"
16 Here is an example of how a "ambiq,gpio" node can be used with the combined
17 gpio child nodes:
19 gpio: gpio@40010000 {
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Dxlnx,ps-gpio-bank.yaml3 # SPDX-License-Identifier: Apache-2.0
7 Xilinx Zynq-7000/ZynqMP MIO/EMIO GPIO controller bank node.
10 a bank of the MIO/EMIO GPIO controller integrated in the Processor
13 compatible: "xlnx,ps-gpio-bank"
15 include: [gpio-controller.yaml, base.yaml]
21 "#gpio-cells":
27 gpio-cells:
28 - pin
29 - flags
Dambiq,gpio-bank.yaml3 # SPDX-License-Identifier: Apache-2.0
5 description: Ambiq GPIO bank node
7 compatible: "ambiq,gpio-bank"
9 include: [gpio-controller.yaml, base.yaml]
15 This property indicates the register address offset of each GPIO child node
16 under the "ambiq,gpio" parent node. The register address of pin described in
17 gpio-cells can be obtained by: base address + child address offset + (pin << 2).
19 "#gpio-cells":
22 gpio-cells:
23 - pin
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Dmicrochip,xec-gpio.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Microchip CEC/MEC GPIO node
6 compatible: "microchip,xec-gpio"
8 include: [gpio-controller.yaml, base.yaml]
14 port-id:
17 description: Zero based GPIO port number
19 girq-id:
22 description: Aggregated GIRQ number for this bank of 32 GPIO pins.
24 "#gpio-cells":
27 gpio-cells:
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Dmicrochip,xec-gpio-v2.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Microchip CEC/MEC GPIO V2 node
6 compatible: "microchip,xec-gpio-v2"
8 include: [gpio-controller.yaml, base.yaml]
14 port-id:
17 description: Zero based GPIO port number
19 girq-id:
22 description: Aggregated GIRQ number for this bank of 32 GPIO pins.
24 "#gpio-cells":
27 gpio-cells:
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/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/renesas/
Dpinctrl-rcar-common.h2 * Copyright (c) 2021-2023 IoT.bzh
4 * SPDX-License-Identifier: Apache-2.0
13 * Each IPSR bank can hold 8 cellules of 4 bits coded function.
15 * @param bank the IPSR register bank.
22 * IPSR bank [ 10 : 14 ]
25 #define IPSR(bank, shift, func) (((bank) << 10U) | ((shift) << 4U) | (func)) argument
27 /* Arbitrary number to encode non capable gpio pin */
31 * @brief Utility macro to encode a GPIO capable pin
33 * @param bank the GPIO bank
34 * @param pin the pin within the GPIO bank (0..31)
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/Zephyr-latest/dts/arm/xilinx/
Dzynqmp.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-r.dtsi>
9 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
10 #include <zephyr/dt-bindings/ethernet/xlnx_gem.h>
16 compatible = "xlnx,pinctrl-zynqmp";
19 compatible = "soc-nv-flash";
24 compatible = "mmio-sram";
29 compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
31 zephyr,memory-region = "OCM";
40 interrupt-names = "irq_0";
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Dzynq7000.dtsi3 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-a.dtsi>
8 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
9 #include <zephyr/dt-bindings/ethernet/xlnx_gem.h>
13 interrupt-parent = <&gic>;
16 compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
18 zephyr,memory-region = "OCM_LOW";
22 compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
24 zephyr,memory-region = "OCM_HIGH";
28 compatible = "arm,armv8-timer";
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/Zephyr-latest/drivers/ethernet/
Deth_enc28j60_priv.h1 /* ENC28J60 Stand-alone Ethernet Controller with SPI
5 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/drivers/gpio.h>
15 /* Any Bank Registers */
26 * Nibble 2 : Bank number
27 * Nibble 1-0: Register address
30 /* Bank 0 Registers */
56 /* Bank 1 Registers */
82 /* Bank 2 Registers */
102 /* Bank 3 Registers */
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Deth_enc424j600_priv.h1 /* ENC424J600 Stand-alone Ethernet Controller with SPI
6 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/drivers/gpio.h>
16 /* Bank 0 Registers */
51 /* Bank 1 Registers */
75 /* Bank 2 Registers */
94 /* Bank 3 Registers */
266 /* Full-Duplex mode Inter-Packet Gap default value */
/Zephyr-latest/drivers/pinctrl/
Dpinctrl_ene_kb1200.c4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/dt-bindings/pinctrl/ene-kb1200-pinctrl.h>
15 #include <reg/gpio.h>
18 * PINMUX_FUNC_A : GPIO Function
24 * GPIO Alternate Output Function Selection
42 * b[7:5] = pin bank
43 * b[4:0] = pin position in bank
60 static int kb1200_config_pin(uint32_t gpio, uint32_t conf, uint32_t func) in kb1200_config_pin() argument
62 uint32_t port = ENE_KB1200_PINMUX_PORT(gpio); in kb1200_config_pin()
63 uint32_t pin = (uint32_t)ENE_KB1200_PINMUX_PIN(gpio); in kb1200_config_pin()
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/Zephyr-latest/include/zephyr/dt-bindings/gpio/
Dmicrochip-xec-gpio.h4 * SPDX-License-Identifier: Apache-2.0
10 * @brief Microchip XEC GPIO bank and bit position convenience defines
12 * Microchip XEC documentation uses octal GPIO pin
27 /* bank A */
60 /* bank B */
93 /* bank C */
126 /* bank D */
159 /* bank E */
192 /* bank F */
/Zephyr-latest/dts/arm/ambiq/
Dambiq_apollo4p.dtsi1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv7-m.dtsi>
6 #include <zephyr/dt-bindings/adc/adc.h>
7 #include <zephyr/dt-bindings/i2c/i2c.h>
8 #include <zephyr/dt-bindings/gpio/gpio.h>
12 uartclk: apb-pclk {
13 compatible = "fixed-clock";
14 clock-frequency = <DT_FREQ_M(24)>;
15 #clock-cells = <0>;
20 #address-cells = <1>;
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Dambiq_apollo4p_blue.dtsi1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv7-m.dtsi>
6 #include <zephyr/dt-bindings/i2c/i2c.h>
7 #include <zephyr/dt-bindings/gpio/gpio.h>
11 uartclk: apb-pclk {
12 compatible = "fixed-clock";
13 clock-frequency = <DT_FREQ_M(24)>;
14 #clock-cells = <0>;
18 clock-frequency = <DT_FREQ_M(32)>;
19 #clock-cells = <1>;
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Dambiq_apollo3p_blue.dtsi1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv7-m.dtsi>
6 #include <zephyr/dt-bindings/adc/adc.h>
7 #include <zephyr/dt-bindings/i2c/i2c.h>
8 #include <zephyr/dt-bindings/gpio/gpio.h>
12 uartclk: apb-pclk {
13 compatible = "fixed-clock";
14 clock-frequency = <DT_FREQ_M(24)>;
15 #clock-cells = <0>;
20 #address-cells = <1>;
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/Zephyr-latest/include/zephyr/drivers/pinctrl/
Dpinctrl_rcar_common.h4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rcar-common.h>
17 uint8_t bank:5; /* bank number 0 - 18 */ member
18 uint8_t shift:5; /* bit shift 0 - 28 */
22 /** Pull-up, pull-down, or bias disable is requested */
26 /** Select pull-up resistor if set pull-down otherwise */
37 /** Type for R-Car pin. */
49 /* Offsets are defined in dt-bindings pinctrl-rcar-common.h */
115 uint32_t puen; /** Pull-enable or pull-up control register */
116 uint32_t pud; /** Pull-up/down or pull-down control register */
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/Zephyr-latest/drivers/pinctrl/renesas/rcar/
Dpfc_rcar.c2 * Copyright (c) 2021-2023 IoT.bzh
4 * SPDX-License-Identifier: Apache-2.0
20 /* Gen3 only has one base address, Gen4 has one per GPIO controller */
68 /* Set the pin either in gpio or peripheral */
74 uint8_t bank = pin / 32; in pfc_rcar_set_gpsr() local
77 uint8_t bank = 0; in pfc_rcar_set_gpsr()
81 bank * sizeof(uint32_t)); in pfc_rcar_set_gpsr()
88 pfc_rcar_write(pfc_base, PFC_RCAR_GPSR + bank * sizeof(uint32_t), val); in pfc_rcar_set_gpsr()
95 uint16_t reg_offs = PFC_RCAR_IPSR + rcar_func->bank * sizeof(uint32_t); in pfc_rcar_set_ipsr()
98 val &= ~(0xFU << rcar_func->shift); in pfc_rcar_set_ipsr()
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/Zephyr-latest/dts/arm/nxp/
Dnxp_rt1015.dtsi5 * SPDX-License-Identifier: Apache-2.0
11 flexram,num-ram-banks = <5>;
15 flexram,bank-spec = <FLEXRAM_OCRAM>,
23 clock-frequency = <500000000>;
39 ipg-podf {
40 clock-div = <4>;
49 /delete-node/ &lpspi3;
50 /delete-node/ &lpspi4;
55 /delete-node/ adc@400C8000;
56 /* GPIOS 4 and 6-9 are not preset on RT1015 */
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Dnxp_rt1020.dtsi5 * SPDX-License-Identifier: Apache-2.0
11 flexram,num-ram-banks = <8>;
13 flexram,bank-spec = <FLEXRAM_OCRAM>,
24 clock-frequency = <500000000>;
40 ipg-podf {
41 clock-div = <4>;
51 /* GPIOS 4 and 6-9 are not preset on RT1020 */
52 /delete-node/ gpio@401c4000;
53 /delete-node/ gpio@42000000;
54 /delete-node/ gpio@42004000;
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Dnxp_rt1024.dtsi5 * SPDX-License-Identifier: Apache-2.0
11 flexram,num-ram-banks = <8>;
13 flexram,bank-spec = <FLEXRAM_OCRAM>,
24 clock-frequency = <500000000>;
45 ipg-podf {
46 clock-div = <4>;
55 compatible = "nxp,imx-flexspi-nor";
58 spi-max-frequency = <133000000>;
60 jedec-id = [9d 70 17];
61 erase-block-size = <DT_SIZE_K(4)>;
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