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Searched +full:gd32 +full:- +full:afio (Results 1 – 12 of 12) sorted by relevance

/Zephyr-latest/drivers/pinctrl/
DKconfig.gd322 # SPDX-License-Identifier: Apache-2.0
5 bool "GD32 AF pin controller driver"
9 GD32 AF pin controller driver. This driver is used by series using the
13 bool "GD32 AFIO pin controller driver"
17 GD32 AFIO pin controller driver. This driver is used by series using the
18 AFIO pin multiplexing model.
Dpinctrl_gd32_afio.c4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/drivers/clock_control/gd32.h>
14 /** AFIO DT node */
15 #define AFIO_NODE DT_NODELABEL(afio)
19 /** GPIO mode: input with pull-up/down (CTL bits) */
21 /** GPIO mode: output push-pull (CTL bits) */
23 /** GPIO mode: output open-drain (CTL bits) */
36 /** GD32 port addresses */
47 /** GD32 port clock identifiers */
59 * @brief Initialize AFIO
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/Zephyr-latest/dts/bindings/pinctrl/
Dgd,gd32-afio.yaml2 # SPDX-License-Identifier: Apache-2.0
5 The AFIO peripheral is used to configure pin remapping, EXTI sources and,
8 compatible: "gd,gd32-afio"
19 enable-cps:
24 the power supply. This option is only available on certain GD32 series.
Dgd,gd32-pinctrl-afio.yaml2 # SPDX-License-Identifier: Apache-2.0
5 The GD32 pin controller (AFIO model) is a singleton node responsible for
7 use this node to route USART0 RX to pin PA10 and enable the pull-up resistor
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined combinations for the SoC variant used by the board */
25 #include <dt-bindings/pinctrl/gd32f403z(k-i-g-e-c-b)xx-pinctrl.h>
39 /* both PA10 and PA12 have pull-up enabled */
40 bias-pull-up;
56 is used for low power states because it disconnects the pin pull-up/down
64 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
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/Zephyr-latest/modules/hal_gigadevice/
DKconfig1 # Copyright (c) 2021 ATL-Electronics
2 # SPDX-License-Identifier: Apache-2.0
15 This option should be selected if the series use an AFIO pinmux model.
74 bool "Use GD32 Debug features"
78 Enable GD32 Debug features.
85 Enable GD32 Analog-to-Digital Converter (ADC) HAL module driver
90 Enable GD32 Backup Registers (BKP) HAL module driver
95 Enable GD32 Controller Area Network (CAN) HAL module driver
100 Enable GD32 Consumer Electronics Control (CEC) HAL module driver
105 Enable GD32 Comparator (CMP) HAL module driver
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/Zephyr-latest/soc/gd/gd32/common/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
19 #include <dt-bindings/pinctrl/gd32-af.h>
21 #include <dt-bindings/pinctrl/gd32-afio.h>
30 /** @brief Type for GD32 pin.
33 * - 0-12: GD32_PINMUX_AF bit field.
34 * - 13-25: Reserved.
35 * - 26-31: Pin configuration bit field (@ref GD32_PINCFG).
37 * Bits (AFIO model):
38 * - 0-19: GD32_PINMUX_AFIO bit field.
39 * - 20-25: Reserved.
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/Zephyr-latest/dts/arm/gd/gd32e50x/
Dgd32e50x.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/pwm/pwm.h>
12 #include <zephyr/dt-bindings/clock/gd32e50x-clocks.h>
13 #include <zephyr/dt-bindings/reset/gd32e50x.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "arm,cortex-m33";
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/Zephyr-latest/dts/riscv/gd/
Dgd32vf103.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/timer/nuclei-systimer.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include <zephyr/dt-bindings/clock/gd32vf103-clocks.h>
14 #include <zephyr/dt-bindings/reset/gd32vf103.h>
17 #address-cells = <1>;
18 #size-cells = <1>;
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/Zephyr-latest/dts/arm/gd/gd32e10x/
Dgd32e10x.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/pwm/pwm.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/clock/gd32e10x-clocks.h>
13 #include <zephyr/dt-bindings/reset/gd32e10x.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
21 clock-frequency = <DT_FREQ_M(120)>;
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/Zephyr-latest/dts/arm/gd/gd32f403/
Dgd32f403.dtsi5 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/adc/adc.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include <zephyr/dt-bindings/clock/gd32f403-clocks.h>
14 #include <zephyr/dt-bindings/reset/gd32f403.h>
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-m4f";
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/Zephyr-latest/drivers/gpio/
Dgpio_gd32.c4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/drivers/clock_control/gd32.h>
23 /** AFIO DT node */
24 #define AFIO_NODE DT_NODELABEL(afio)
30 /** GPIO mode: input with pull-up/down (CTL bits) */
32 /** GPIO mode: output push-pull @ 2MHz (CTL bits) */
34 /** GPIO mode: output open-drain @ 2MHz (CTL bits) */
67 struct gpio_gd32_data *data = dev->data; in gpio_gd32_isr()
69 gpio_fire_callbacks(&data->callbacks, dev, BIT(line)); in gpio_gd32_isr()
79 * @retval -EINVAL if pin is not valid.
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/Zephyr-latest/doc/releases/
Drelease-notes-3.2.rst13 * Added support for :ref:`bin-blobs` (also see :ref:`west-blobs`).
15 * Converted all supported boards from ``pinmux`` to :ref:`pinctrl-guide`.
31 * CVE-2022-2993: Under embargo until 2022-11-03
33 * CVE-2022-2741: Under embargo until 2022-10-14
56 This definition can be used by third-party code to compile code conditional
58 Therefore, any third-party code integrated using the Zephyr build system will
91 changed from ``-ENETDOWN`` to ``-ENETUNREACH``. A return value of ``-ENETDOWN`` now indicates
129 * Removed support for configuring the CAN-FD maximum DLC value via Kconfig
156 valid for specific bindings to specify like :dtcompatible:`gpio-leds` and
157 :dtcompatible:`fixed-partitions`.
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