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/Zephyr-latest/dts/bindings/ethernet/
Dethernet-phy.yaml1 # Copyright (c) 2021 IP-Logix Inc.
2 # SPDX-License-Identifier: Apache-2.0
8 compatible: "ethernet-phy"
16 no-reset:
19 fixed-link:
23 - "10BASE-T Half-Duplex"
24 - "10BASE-T Full-Duplex"
25 - "100BASE-T Half-Duplex"
26 - "100BASE-T Full-Duplex"
27 - "1000BASE-T Half-Duplex"
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Dnxp,kinetis-ethernet.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,kinetis-ethernet"
8 include: ["ethernet-controller.yaml", "pinctrl-device.yaml"]
15 phy-addr:
19 reset-gpios:
20 type: phandle-array
22 int-gpios:
23 type: phandle-array
27 child-binding:
35 - 100
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Dmicrochip,enc28j60.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: ENC28J60 standalone 10BASE-T Ethernet controller with SPI interface
8 include: [spi-device.yaml, ethernet-controller.yaml]
11 int-gpios:
12 type: phandle-array
20 full-duplex:
23 Optional feature flag - Enables full duplex reception and transmission.
25 hw-rx-filter:
Dxlnx,gem.yaml3 # SPDX-License-Identifier: Apache-2.0
10 include: ethernet-controller.yaml
19 clock-frequency:
27 which it will be adjusted at run-time. Therefore, the value of this
29 respective GEM's TX clock - by default, this is the IO PLL.
31 mdc-divider:
42 init-mdio-phy:
45 Activates the management of a PHY associated with the controller in-
46 stance. If this parameter is activated at the board level, the de-
47 fault values of the associated parameters mdio-phy-address, phy-poll-
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/Zephyr-latest/include/zephyr/net/
Dmii.h5 * SPDX-License-Identifier: Apache-2.0
33 /** Auto-Negotiation Advertisement Register */
35 /** Auto-Negotiation Link Partner Ability Reg */
37 /** Auto-Negotiation Expansion Register */
39 /** Auto-Negotiation Next Page Transmit Register */
41 /** Auto-Negotiation Link Partner Received Next Page Reg */
43 /** 1000BASE-T Control Register */
45 /** 1000BASE-T Status Register */
61 /** Auto-Negotiation enable */
67 /** restart auto-negotiation */
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Dphy.h8 * Copyright (c) 2021 IP-Logix Inc.
11 * SPDX-License-Identifier: Apache-2.0
33 /** 10Base-T Half-Duplex */
35 /** 10Base-T Full-Duplex */
37 /** 100Base-T Half-Duplex */
39 /** 100Base-T Full-Duplex */
41 /** 1000Base-T Half-Duplex */
43 /** 1000Base-T Full-Duplex */
45 /** 2.5GBase-T Full-Duplex */
47 /** 5GBase-T Full-Duplex */
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/Zephyr-latest/dts/bindings/mipi-dbi/
Dmipi-dbi-spi-device.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: [mipi-dbi-device.yaml]
9 duplex:
13 SPI Duplex mode, full or half. By default it's always full duplex thus 0
15 Selecting half duplex allows to use SPI MOSI as a bidirectional line,
18 list (see dt-bindings/spi/spi.h)
21 mipi-cpol:
26 mipi-cpha:
31 mipi-hold-cs:
/Zephyr-latest/drivers/ethernet/phy/
Dphy_dm8806_priv.h4 * SPDX-License-Identifier: Apache-2.0
9 /* 10 Mbit/s transfer with half duplex mask. */
11 /* 10 Mbit/s transfer with full duplex mask. */
13 /* 100 Mbit/s transfer with half duplex mask. */
15 /* 100 Mbit/s transfer with full duplex mask. */
17 /* Duplex mode ability offset. */
28 /* 10 Mbit/s transfer speed with half duplex. */
30 /* 10 Mbit/s transfer speed with full duplex. */
32 /* 100 Mbit/s transfer speed with half duplex. */
34 /* 100 Mbit/s transfer speed with full duplex. */
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/Zephyr-latest/dts/bindings/spi/
Dmicrochip,xec-qmspi-ldma.yaml3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "microchip,xec-qmspi-ldma"
9 include: [spi-controller.yaml, pinctrl-device.yaml]
30 pinctrl-0:
33 pinctrl-names:
39 QMSPI data lines 1, 2, or 4. 1 data line is full-duplex
40 MOSI and MISO or half-duplex on MOSI only. Lines set to 2
42 Defaults to 1 for full duplex driver's support for full-duplex spi.
44 - 1
45 - 2
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Dspi-device.yaml1 # Copyright (c) 2018, I-SENSE group of ICCS
2 # SPDX-License-Identifier: Apache-2.0
8 on-bus: spi
13 spi-max-frequency:
17 duplex:
21 Duplex mode, full or half. By default it's always full duplex thus 0
24 list (see dt-bindings/spi/spi.h)
28 - 0
29 - 2048
30 frame-format:
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/Zephyr-latest/dts/bindings/wifi/
Dinfineon,airoc-wifi-spi.yaml2 AIROC Wi-Fi Connectivity over SPI.
4 compatible: "infineon,airoc-wifi"
6 include: [spi-device.yaml, "infineon,airoc-wifi.yaml"]
9 wifi-host-wake-gpios:
12 bus-select-gpios:
16 wifi-reg-on-gpios goes high to select SPI bus mode.
17 type: phandle-array
19 spi-half-duplex:
21 Use half-duplex communication; if not present, full-
22 duplex operation is assumed.
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/Zephyr-latest/include/zephyr/dt-bindings/spi/
Dspi.h4 * SPDX-License-Identifier: Apache-2.0
17 * @name SPI duplex mode
20 * Some controllers support half duplex transfer, which results in 3-wire usage.
21 * By default, full duplex will prevail.
/Zephyr-latest/dts/arm/xilinx/
Dzynqmp.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-r.dtsi>
9 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
10 #include <zephyr/dt-bindings/ethernet/xlnx_gem.h>
16 compatible = "xlnx,pinctrl-zynqmp";
19 compatible = "soc-nv-flash";
24 compatible = "mmio-sram";
29 compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
31 zephyr,memory-region = "OCM";
40 interrupt-names = "irq_0";
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Dzynq7000.dtsi3 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-a.dtsi>
8 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
9 #include <zephyr/dt-bindings/ethernet/xlnx_gem.h>
13 interrupt-parent = <&gic>;
16 compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
18 zephyr,memory-region = "OCM_LOW";
22 compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
24 zephyr,memory-region = "OCM_HIGH";
28 compatible = "arm,armv8-timer";
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/Zephyr-latest/boards/shields/mikroe_eth_click/
Dmikroe_eth_click.overlay2 * SPDX-License-Identifier: Apache-2.0
11 full-duplex;
12 local-mac-address = [00 00 00 01 02 03];
14 spi-max-frequency = <10000000>;
15 int-gpios = <&mikrobus_header 7 GPIO_ACTIVE_LOW>; /* INT */
/Zephyr-latest/boards/shields/mikroe_eth_click/boards/
Dlpcxpresso55s69_lpc55s69_cpu0.overlay4 * SPDX-License-Identifier: Apache-2.0
7 /delete-node/ &eth_click;
12 cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>,
21 full-duplex;
22 local-mac-address = [00 00 00 01 02 03];
24 spi-max-frequency = <10000000>;
25 int-gpios = <&mikrobus_header 7 GPIO_ACTIVE_LOW>; /* INT */
/Zephyr-latest/drivers/ethernet/
Dphy_xlnx_gem.c6 * - Marvell Alaska 88E1111 (QEMU simulated PHY)
7 * - Marvell Alaska 88E1510/88E1518/88E1512/88E1514 (Zedboard)
8 * - Texas Instruments TLK105
9 * - Texas Instruments DP83822
12 * SPDX-License-Identifier: Apache-2.0
34 * @return 16-bit data word received from the PHY
44 * MDIO read operation as described in Zynq-7000 TRM, in phy_xlnx_gem_mdio_read()
81 * Wait until gem.net_status[phy_mgmt_idle] == 1 -> current command in phy_xlnx_gem_mdio_read()
99 * Read the data returned by the PHY -> lower 16 bits of the PHY main- in phy_xlnx_gem_mdio_read()
113 * @param value 16-bit data word to be written to the target register
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DKconfig.stm32_hal5 # SPDX-License-Identifier: Apache-2.0
84 PHY's carrier status is re-evaluated.
109 bool "Half duplex mode"
111 Set this if using half duplex when autonegotiation is disabled otherwise
112 duplex mode is full duplex
Dphy_cyclonev.c4 * SPDX-License-Identifier: Apache-2.0
8 * downloads/en/DeviceDoc/KSZ9021RL-RN-Data-Sheet-DS00003050A.pdf)
28 /* Speed and Duplex mask values */
51 #define PHY_AUTOCAP BIT(3) /* Auto-negotiation capability */
55 /* Auto-Negotiation Advertisement */
64 /* 1000Base-T Control */
103 return -1; in alt_eth_phy_write_register()
122 sys_write32(phy_value & 0xffff, EMAC_GMAC_GMII_DATA_ADDR(p->base_addr)); in alt_eth_phy_write_register()
124 sys_write32(tmpreg & 0xffff, EMAC_GMAC_GMII_ADDR_ADDR(p->base_addr)); in alt_eth_phy_write_register()
130 tmpreg = sys_read32(EMAC_GMAC_GMII_ADDR_ADDR(p->base_addr)); in alt_eth_phy_write_register()
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/Zephyr-latest/dts/bindings/mspi/
Dmspi-controller.yaml2 # SPDX-License-Identifier: Apache-2.0
11 clock-frequency:
15 "#address-cells":
18 "#size-cells":
22 op-mode:
25 - "MSPI_CONTROLLER"
26 - "MSPI_PERIPHERAL"
31 duplex:
34 - "MSPI_HALF_DUPLEX"
35 - "MSPI_FULL_DUPLEX"
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/Zephyr-latest/doc/connectivity/networking/api/
Dethernet.rst28 * Half/full duplex
33 * :ref:`Priority queues <traffic-class-support>`
39 see what is supported by ``net iface`` net-shell command. It will print
/Zephyr-latest/boards/intel/socfpga/agilex5_socdk/
Dintel_socfpga_agilex5_socdk.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
13 compatible = "intel,socfpga-agilex5";
14 #address-cells = <1>;
15 #size-cells = <1>;
19 zephyr,shell-uart = &uart0;
28 compatible = "zephyr,sdmmc-disk";
29 disk-name = "SD";
36 current-speed = <115200>;
40 full-duplex-mode-en;
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/Zephyr-latest/soc/microchip/mec/
DKconfig5 # SPDX-License-Identifier: Apache-2.0
18 Boot-ROM. Use the full Microchip SPI image generator program for
19 authentication and all other Boot-ROM loader features. Refer to the MCHP
65 bool "SPI flash operates full-duplex with frequency (< 25 MHz)"
68 bool "SPI flash operates full-duplex with fast reading mode"
227 or other non-JTAG alternate functions.
251 ETM re-assigns 5 pins for clock and 4-bit data bus.
/Zephyr-latest/subsys/net/l2/ethernet/gptp/
Dgptp_md.h4 * SPDX-License-Identifier: Apache-2.0
9 * @brief GPTP Media Dependent interface for full duplex and point to point
/Zephyr-latest/samples/boards/nxp/s32/netc/
DREADME.rst1 .. zephyr:code-sample:: nxp_s32_netc
10 for the different use-cases:
18 The sample enables the net-shell and mdio-shell (only available when Zephyr
28 To run this sample is needed to set-up a host machine running GNU/Linux or Windows
35 To build and run the sample application for use-case 1:
37 .. zephyr-app-commands::
38 :zephyr-app: samples/boards/nxp/s32/netc
44 .. code-block:: console
52 [00:00:07.595,000] <inf> phy_mii: PHY (7) Link speed 1000 Mb, full duplex
58 To build and run the sample application for use-case 2:
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