1/*
2 * Copyright (c) 2024, Intel Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8
9#include <intel/intel_socfpga_agilex5.dtsi>
10
11/ {
12	model = "Intel SoC FPGA Agilex5";
13	compatible = "intel,socfpga-agilex5";
14	#address-cells = <1>;
15	#size-cells = <1>;
16
17	chosen {
18		zephyr,console = &uart0;
19		zephyr,shell-uart = &uart0;
20		zephyr,sram = &mem0;
21	};
22};
23
24&sdmmc {
25	status = "okay";
26	mmc {
27		/*SD Disk Access */
28		compatible = "zephyr,sdmmc-disk";
29		disk-name = "SD";
30		status = "okay";
31	};
32};
33
34&uart0 {
35	status = "okay";
36	current-speed = <115200>;
37};
38
39&xgmac0 {
40	full-duplex-mode-en;
41	num-dma-ch   = <1>;
42	num-tx-queues = <1>;
43	num-rx-queues = <1>;
44	num-tc = <1>;
45	dma-ch-rdrl = <128>;
46	dma-ch-tdrl = <128>;
47	max-speed = <1000>;
48	max-frame-size = <9018>;
49	jumbo-pkt-en;
50	zephyr,random-mac-address;
51	phy-handle = <&phy0>;
52};
53
54&mdio0  {
55	csr-clock-indx = <4>;
56
57	phy0: phy@0 {
58		compatible = "ethernet-phy";
59		reg = <0>;
60	};
61};
62