| /Zephyr-latest/dts/bindings/clock/ |
| D | st,stm32wb0-lsi-clock.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 The STM32WB0 MCUs are equipped with a regular RC LSI clock with a frequency of 24~40kHz.
8 The SoCs are also equipped with hardware to perform LSI frequency measurement, which
9 allows to adapt all frequency-based calculations to a somewhat accurate value, ensuring
10 that the software does not get too much out of sync with real-world time.
12 Several LSI frequency measurement options can be configured via Kconfig.
14 compatible: "st,stm32wb0-lsi-clock"
16 include: [fixed-clock.yaml]
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| D | st,stm32wba-rcc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
13 Core clock frequency should also be defined, using "clock-frequency" property.
15 Core clock frequency = SYSCLK / AHB prescaler
21 ahb-prescaler = <2>;
22 clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
23 apb1-presacler = <1>;
24 apb2-presacler = <1>;
25 apb7-presacler = <7>;
55 compatible: "st,stm32wba-rcc"
57 include: [clock-controller.yaml, base.yaml]
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| D | st,stm32f1-rcc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 For more description confere st,stm32-rcc.yaml
9 compatible: "st,stm32f1-rcc"
11 include: st,stm32-rcc.yaml
14 adc-prescaler:
17 - 2
18 - 4
19 - 6
20 - 8
22 ADC prescaler. Defines ADC core clock frequency
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| D | st,stm32wb0-rcc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 compatible: "st,stm32wb0-rcc"
11 include: [clock-controller.yaml, base.yaml]
17 "#clock-cells":
20 clock-frequency:
24 default frequency in Hz for clock output
26 slow-clock:
35 clksys-prescaler:
39 - 1
40 - 2
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| D | adi,max32-gcr.yaml | 1 # Copyright (c) 2023-2024 Analog Devices, Inc.
2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "adi,max32-gcr"
8 include: [clock-controller.yaml, base.yaml]
14 "#clock-cells":
17 sysclk-prescaler:
20 - 1
21 - 2
22 - 4
23 - 8
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| D | st,stm32-rcc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
13 Core clock frequency should also be defined, using "clock-frequency" property.
15 Core clock frequency = SYSCLK / AHB prescaler
21 ahb-prescaler = <2>;
22 clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
23 apb1-prescaler = <1>;
24 apb2-prescaler = <1>;
74 frequency divided by 2) is done with following clock property:
81 compatible: "st,stm32-rcc"
83 include: [clock-controller.yaml, base.yaml]
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| /Zephyr-latest/dts/bindings/audio/ |
| D | nxp,dmic.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 include: [base.yaml, pinctrl-device.yaml]
17 pinctrl-0:
27 the required PDM bit clock frequency by a factor of two, and can reduce
31 child-binding:
36 compatible: "nxp,dmic-channel"
48 data by, as a positive or negative number. Range of [-15,15]. Default
51 compensation-2fs:
55 - "zero"
56 - "-0.16"
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| /Zephyr-latest/drivers/timer/ |
| D | Kconfig.mec5 | 2 # SPDX-License-Identifier: Apache-2.0
14 The 32-bit 32 KHz based RTOS timer which is operational in
15 full power and deep sleep. Basic timer 5 is a 48 MHz based
16 32-bit down counter with frequency divider used for the
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| D | Kconfig.x86 | 1 # Copyright (c) 2014-2015 Wind River Systems, Inc.
3 # Copyright (c) 2019-2023 Intel Corp.
4 # SPDX-License-Identifier: Apache-2.0
44 Extremely simple timer driver based the local APIC TSC
45 deadline capability. The use of a free-running 64 bit
47 from the handling, and the near-instruction-cycle resolution
50 logic). SMP-safe and very fast, this should be the obvious
63 local APIC in one-shot mode as the timeout event source.
64 You must know the ratio of the TSC frequency to the local APIC
65 timer frequency.
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| /Zephyr-latest/dts/bindings/auxdisplay/ |
| D | sparkfun,serlcd.yaml | 2 # SPDX-License-Identifier: Apache-2.0
14 command-delay-ms = <10>;
15 special-command-delay-ms = <50>;
21 include: [auxdisplay-device.yaml, i2c-device.yaml]
28 - 16
29 - 20
35 - 2
36 - 4
38 command-delay-ms:
43 The default value is based on the original SparkFun SerLCD library
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| /Zephyr-latest/dts/bindings/mdio/ |
| D | mdio-controller.yaml | 1 # Copyright (c) 2021 IP-Logix Inc.
2 # SPDX-License-Identifier: Apache-2.0
11 "#address-cells":
15 "#size-cells":
19 suppress-preamble:
22 When present, the SMA suppresses the 32-bit preamble and transmits
26 clock-frequency:
30 Some MDIO controllers have the ability to configure the MDC frequency.
31 If present, this property may be used to specify the MDC frequency based
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| /Zephyr-latest/drivers/ethernet/ |
| D | Kconfig.stm32_hal | 5 # SPDX-License-Identifier: Apache-2.0
19 Enable STM32 HAL based Ethernet driver. It is available for
37 Driver version based on legacy HAL version as the current official API version.
84 PHY's carrier status is re-evaluated.
126 int "Frequency of the clock source for the PTP timer"
130 Set the frequency in Hz sourced to the PTP timer.
134 int "Lower bound of clock frequency adjustment (in percent)"
141 int "Upper bound of clock frequency adjustment (in percent)"
163 based on a computed hash of the destination MAC address of
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| /Zephyr-latest/drivers/sensor/st/lsm9ds0_gyro/ |
| D | Kconfig | 4 # SPDX-License-Identifier: Apache-2.0
12 Enable driver for LSM9DS0 I2C-based gyroscope sensor.
19 prompt "Default full-scale"
22 Specify the default full-scale.
36 bool "Dynamic full-scale"
38 Enable alteration of full-scale attribute at runtime.
41 prompt "Default sampling rate frequency"
44 Specify the default sampling rate frequency.
63 Enable alteration of sampling rate frequency at runtime.
70 depends on $(dt_compat_any_has_prop,$(DT_COMPAT_ST_LSM9DS0_GYRO),irq-gpios)
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| /Zephyr-latest/drivers/clock_control/ |
| D | clock_control_agilex5_ll.c | 2 * Copyright (c) 2022-2024, Intel Corporation.
4 * SPDX-License-Identifier: Apache-2.0
31 * Based on the clock source, read the values from System Manager boot in get_ref_clk()
32 * scratch registers. These values are filled by boot loader based on in get_ref_clk()
33 * hand-off data. in get_ref_clk()
68 /* Calculate clock frequency based on parameter */
158 uint8_t cpu_id = arch_curr_cpu()->id; in get_mpu_clk()
196 /* Calculate clock frequency to be used for watchdog timer */
207 /* Get clock frequency to be used for UART driver */
213 /* Calculate clock frequency to be used for SDMMC driver */
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| D | clock_agilex_ll.c | 2 * Copyright (c) 2019-2021, Intel Corporation. All rights reserved.
4 * SPDX-License-Identifier: Apache-2.0
13 * Intel SoC re-use Arm Trusted Firmware (ATF) driver code in Zephyr.
16 * register access. This allow Zephyr to re-use the ATF driver codes
53 /* Calculate clock frequency based on parameter */
95 /* Calculate clock frequency to be used for mpu */
105 /* Calculate clock frequency to be used for watchdog timer */
116 /* Calculate clock frequency to be used for UART driver */
131 /* Calculate clock frequency to be used for SDMMC driver */
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| /Zephyr-latest/soc/nxp/imxrt/imxrt118x/ |
| D | flexspi.c | 4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
35 return -ENOTSUP; in flexspi_clock_set_freq()
39 /* Get clock root frequency */ in flexspi_clock_set_freq()
41 /* Select a divider based on root clock frequency. We round the in flexspi_clock_set_freq()
42 * divider up, so that the resulting clock frequency is lower than in flexspi_clock_set_freq()
43 * requested when we can't output the exact requested frequency in flexspi_clock_set_freq()
45 divider = ((root_rate + (rate - 1)) / rate); in flexspi_clock_set_freq()
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| /Zephyr-latest/soc/nxp/imxrt/imxrt11xx/ |
| D | flexspi.c | 4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
35 return -ENOTSUP; in flexspi_clock_set_freq()
39 /* Get clock root frequency */ in flexspi_clock_set_freq()
41 /* Select a divider based on root clock frequency. We round the in flexspi_clock_set_freq()
42 * divider up, so that the resulting clock frequency is lower than in flexspi_clock_set_freq()
43 * requested when we can't output the exact requested frequency in flexspi_clock_set_freq()
45 divider = ((root_rate + (rate - 1)) / rate); in flexspi_clock_set_freq()
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| /Zephyr-latest/soc/silabs/ |
| D | Kconfig | 3 # SPDX-License-Identifier: Apache-2.0
18 Set if the Back-Up Real Time Counter (BURTC) HAL module is used.
54 Set if the Inter-Integrated Circuit Interface (I2C) HAL module is used.
187 Enable Entropy driver based on the CRYPTO_ACC module for Silicon Labs
203 Enable counter driver based on the Sleep Timer driver for Silicon Labs
217 in on-demand mode, after SoC is initialized.
220 prompt "High Frequency Clock Selection"
224 bool "External high frequency crystal oscillator"
226 Set this option to use the external high frequency crystal oscillator
227 as high frequency clock.
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| /Zephyr-latest/soc/nxp/imxrt/imxrt10xx/ |
| D | flexspi.c | 4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/dt-bindings/clock/imx_ccm.h>
24 /* Get clock root frequency */ in flexspi_clock_set_freq()
33 /* Get clock root frequency */ in flexspi_clock_set_freq()
42 return -ENOTSUP; in flexspi_clock_set_freq()
44 /* Select a divider based on root frequency. in flexspi_clock_set_freq()
47 divider = ((root_rate + (rate - 1)) / rate) - 1; in flexspi_clock_set_freq()
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| /Zephyr-latest/arch/arm/core/cortex_m/ |
| D | timing.c | 5 * SPDX-License-Identifier: Apache-2.0
10 * @brief ARM Cortex-M Timing functions interface based on DWT
22 * @brief Return the current frequency of the cycle counter
24 * This routine returns the current frequency of the DWT Cycle Counter
27 * @return the cycle counter frequency value
33 * DWT frequency is taken directly from the in z_arm_dwt_freq_get()
34 * System Core clock (CPU) frequency, if the in z_arm_dwt_freq_get()
41 /* SysTick and DWT both run at CPU frequency, in z_arm_dwt_freq_get()
66 * cycles are in 32-bit, and delta must be in z_arm_dwt_freq_get()
67 * calculated in 32-bit precision. Or it would be in z_arm_dwt_freq_get()
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| /Zephyr-latest/soc/nxp/rw/ |
| D | flexspi_clock_setup.c | 2 * Copyright 2022-2023 NXP
3 * SPDX-License-Identifier: Apache-2.0
15 * @brief Set flexspi clock to given frequency
19 * is used by the clock control framework to set the clock frequency of
30 root_rate = ((CLKCTL0->FLEXSPIFCLKDIV & CLKCTL0_FLEXSPIFCLKDIV_DIV_MASK) + 1) * in flexspi_clock_set_freq()
33 /* Select a divider based on root frequency. in flexspi_clock_set_freq()
36 divider = ((root_rate + (rate - 1)) / rate) - 1; in flexspi_clock_set_freq()
45 set_flexspi_clock(FLEXSPI, (CLKCTL0->FLEXSPIFCLKSEL & in flexspi_clock_set_freq()
62 CLKCTL0->FLEXSPIFCLKSEL = CLKCTL0_FLEXSPIFCLKSEL_SEL(src); in set_flexspi_clock()
63 CLKCTL0->FLEXSPIFCLKDIV |= in set_flexspi_clock()
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| /Zephyr-latest/drivers/sensor/st/lsm303dlhc_magn/ |
| D | Kconfig | 4 # SPDX-License-Identifier: Apache-2.0
12 Enable driver for LSM303DLHC I2C-based triaxial magnetometer sensor.
20 1: +/-1.3 gauss
21 2: +/-1.9 gauss
22 3: +/-2.5 gauss
23 4: +/-4 gauss
24 5: +/-4.7 gauss
25 6: +/-5.6 gauss
26 7: +/-8.1 gauss
29 int "Data rate frequency"
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| /Zephyr-latest/dts/bindings/led_strip/ |
| D | worldsemi,ws2812-rpi_pico-pio.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 compatible: "worldsemi,ws2812-rpi_pico-pio"
9 include: pinctrl-device.yaml
12 bit-waveform:
15 This property defines the waveform for sending 1-bit data.
19 The T1 is equal to (T1H-T0H) or (T0L-T1L) in the datasheet.
21 Code-0
22 +------+ +---
26 ---+ +-----------------+
28 Code-1
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| /Zephyr-latest/samples/basic/blinky_pwm/ |
| D | README.rst | 1 .. zephyr:code-sample:: pwm-blinky
3 :relevant-api: pwm_interface
11 :zephyr:code-sample:`blinky` for a GPIO-based sample.
13 The LED starts blinking at a 1 Hz frequency. The frequency doubles every 4
14 seconds until it reaches 128 Hz. The frequency will then be halved every 4
16 faster-then-slower blinking cycle then repeats forever.
19 frequency of 1 Hz. This sample calibrates itself to what the hardware supports
28 <dt-guide>` alias, usually in the :ref:`BOARD.dts file
29 <devicetree-in-out-files>`.
39 .. list-table::
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| /Zephyr-latest/drivers/wifi/nrf_wifi/ |
| D | Kconfig.nrfwifi | 1 # Nordic Wi-Fi driver for nRF70 series SoCs
5 # SPDX-License-Identifier: Apache-2.0
21 Nordic Wi-Fi Driver
124 bool "Wi-Fi interface auto start on boot"
145 bool "Low power mode in nRF Wi-Fi chipsets"
169 module-dep = LOG
170 module-str = Log level for Wi-Fi nRF70 driver
171 module-help = Sets log level for Wi-Fi nRF70 driver
193 # Wi-Fi and SR Coexistence Hardware configuration.
195 bool "Wi-Fi and SR coexistence support"
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