1# Copyright 2023 NXP
2# SPDX-License-Identifier: Apache-2.0
3
4description: NXP DMIC
5
6compatible: "nxp,dmic"
7
8include: [base.yaml, pinctrl-device.yaml]
9
10properties:
11  reg:
12    required: true
13
14  interrupts:
15    required: true
16
17  pinctrl-0:
18    required: true
19
20  clocks:
21    required: true
22
23  use2fs:
24    type: boolean
25    description: |
26      Use 2FS output, and bypass final half band decimator. This will reduce
27      the required PDM bit clock frequency by a factor of two, and can reduce
28      power consumption.
29
30# Child binding definition, describes each channel of the DMIC
31child-binding:
32  description: |
33    NXP DMIC channel. Can be used to configure filtering and gain attributes
34    of each channel
35  include: base.yaml
36  compatible: "nxp,dmic-channel"
37  properties:
38    reg:
39      required: true
40    dmas:
41      required: true
42
43    gainshift:
44      type: int
45      default: 0
46      description: |
47        Decimator gain shift. Sets the number of bits to shift decimated PCM
48        data by, as a positive or negative number. Range of [-15,15]. Default
49        is reset value of register
50
51    compensation-2fs:
52      type: string
53      default: "zero"
54      enum:
55        - "zero"
56        - "-0.16"
57        - "-0.15"
58        - "-0.13"
59      description: |
60        2FS compensation filter. See SOC reference manual for filter response
61        of each value. Default value is reset value of register, and
62        recommended filter setting.
63
64    compensation-4fs:
65      type: string
66      default: "zero"
67      enum:
68        - "zero"
69        - "-0.16"
70        - "-0.15"
71        - "-0.13"
72      description: |
73        4FS compensation filter. See SOC reference manual for filter response
74        of each value. Default value is reset value of register, and
75        recommended filter setting.
76
77    dc-cutoff:
78      type: string
79      default: "flat"
80      enum:
81        - "flat"
82        - "155hz"
83        - "78hz"
84        - "39hz"
85      description: |
86        DC cutoff filter setting. Default is reset value of register. Note that
87        each cutoff frequency is based on a sample frequency of 16KHz, so
88        actual cutoff values will scale up or down based on your sampling
89        frequency
90
91    dc-gain:
92      type: int
93      default: 0
94      description: |
95        DC gain fine adjustment. Number of bits to downshift the final
96        conversion result. Max value of 15. Default is reset value of
97        register
98