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/Zephyr-latest/include/zephyr/arch/xtensa/
Dmpu.h4 * SPDX-License-Identifier: Apache-2.0
12 #include <xtensa/config/core-isa.h>
18 * @defgroup xtensa_mpu_apis Xtensa Memory Protection Unit (MPU) APIs
27 * @name MPU memory region access rights.
37 /** Kernel mode execution only. */
40 /** User mode execution only. */
46 /** Kernel mode read and execution. */
52 /** Kernel mode read, write and execution. */
58 /** Kernel mode read, write. User mode read, write and execution. */
64 /** Kernel mode read, write and execution. User mode read and execution. */
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Dxtensa_mmu.h4 * SPDX-License-Identifier: Apache-2.0
13 * @defgroup xtensa_mmu_apis Xtensa Memory Management Unit (MMU) APIs
19 * @name Memory region permission and caching mode.
23 /** Memory region is executable. */
26 /** Memory region is writable. */
29 /** Memory region is both executable and writable */
32 /** Memory region has write-back cache. */
35 /** Memory region has write-through cache. */
43 * @name Memory domain and partitions
53 /* Read-Write access permission attributes */
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/Zephyr-latest/include/zephyr/portability/
Dcmsis_os2.h2 * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
4 * SPDX-License-Identifier: Apache-2.0
10 * www.apache.org/licenses/LICENSE-2.0
18 * ----------------------------------------------------------------------
23 * Project: CMSIS-RTOS2 API
28 * - osKernelGetInfo, osKernelGetState
31 * - osKernelGetTickCount, osKernelGetTickFreq
33 * - updated: osKernelGetTickCount, osDelayUntil
36 * - updated: osKernelLock, osKernelUnlock
37 * - added: osKernelRestoreLock
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Dcmsis_os.h1 /* ----------------------------------------------------------------------
5 * Project: CMSIS-RTOS API
17 * - const attribute removed from the osXxxxDef_t typedef's
18 * - const attribute added to the osXxxxDef macros
25 *----------------------------------------------------------------------------
27 * Copyright (c) 2013-2017 ARM LIMITED
29 * SPDX-License-Identifier: Apache-2.0
35 * www.apache.org/licenses/LICENSE-2.0
42 *---------------------------------------------------------------------------*/
48 /// \note MUST REMAIN UNCHANGED: \b osCMSIS identifies the CMSIS-RTOS API version.
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/Zephyr-latest/doc/hardware/arch/
Dx86.rst10 x86-based platforms.
12 Virtual Memory
17 memory are identity mapped and thus giving the appearance of execution
23 is being placed in the memory, and its counterpart
29 On 32-bit x86, it is possible to have separate physical and virtual
31 but are still loaded in physical memory. However, during boot, code
34 After ``vm_enter``, code execution is done via virtual addresses
39 to the physical memory. Later in the boot process,
42 the identity mapping of physical memory. This unmapping must be done
44 restricted memory via physical addresses. Since the identity mapping
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/Zephyr-latest/dts/bindings/riscv/
Dnordic,nrf-vpr-coprocessor.yaml2 # SPDX-License-Identifier: Apache-2.0
4 compatible: "nordic,nrf-vpr-coprocessor"
9 VPR is a RISC-V CPU implementation. VPR instances are exposed to other CPUs as
15 execution-memory:
19 Memory area from which the VPR core will execute.
21 source-memory:
24 Memory area or partition from which the VPR code will be loaded.
/Zephyr-latest/snippets/nordic-flpr-xip/soc/
Dnrf54h20_cpuapp.overlay3 * SPDX-License-Identifier: Apache-2.0
7 execution-memory = <&cpuflpr_code_partition>;
8 /delete-property/ source-memory;
13 interrupt-parent = <&cpuflpr_clic>;
Dnrf54l15_cpuapp.overlay3 * SPDX-License-Identifier: Apache-2.0
8 reserved-memory {
9 #address-cells = <1>;
10 #size-cells = <1>;
24 execution-memory = <&cpuflpr_code_partition>;
/Zephyr-latest/snippets/nordic-ppr-xip/soc/
Dnrf54h20_cpuapp.overlay3 * SPDX-License-Identifier: Apache-2.0
11 execution-memory = <&cpuppr_code_partition>;
12 /delete-property/ source-memory;
Dnrf9280_cpuapp.overlay3 * SPDX-License-Identifier: Apache-2.0
11 execution-memory = <&cpuppr_code_partition>;
12 /delete-property/ source-memory;
/Zephyr-latest/doc/kernel/memory_management/
Ddemand_paging.rst7 memory as required by current execution context. The physical memory is
8 conceptually divided in page-sized page frames as regions to hold data.
11 one of the page frames, the execution continues without any interruptions.
15 the corresponding data page from backing store into physical memory if
25 page into the free page frame. Now the data page is in physical memory
26 and execution can continue.
33 memory, and thus minimizing latency. :c:func:`k_mem_page_out()` can be
43 A data page is a page-sized region of data. It may exist in a page frame,
50 A page frame is a page-sized physical memory region in RAM. It is a
60 * ``K_MEM_PAGE_FRAME_PINNED`` indicates a page frame is pinned in memory
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/Zephyr-latest/arch/arm64/core/
DKconfig4 # SPDX-License-Identifier: Apache-2.0
18 This option signifies the use of a CPU of the Cortex-A family.
31 This option signifies the use of a CPU of the Cortex-R 64-bit family.
38 This option signifies the use of a Cortex-A53 CPU
45 This option signifies the use of a Cortex-A55 CPU
52 This option signifies the use of a Cortex-A57 CPU
59 This option signifies the use of a Cortex-A72 CPU
66 This option signifies the use of a Cortex-A76 CPU
73 This option signifies the use of a Cortex-A76 and A55 big little CPU cluster
80 This option signifies the use of a Cortex-R82 CPU
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Dthread.c4 * SPDX-License-Identifier: Apache-2.0
9 * @brief New thread creation for ARM64 Cortex-A
11 * Core thread related primitives for the ARM64 Cortex-A
23 * - kernel threads are running in EL1 using SP_EL1 as stack pointer during
24 * normal execution and during exceptions. They are by definition already
27 * - user threads are running in EL0 using SP_EL0 as stack pointer during
28 * normal execution. When at exception is taken or a syscall is called the
29 * stack pointer switches to SP_EL1 and the execution starts using the
33 * - a stack guard region will be added bellow the kernel stack when
43 * High memory addresses
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/Zephyr-latest/kernel/
DKconfig.vm3 # SPDX-License-Identifier: Apache-2.0
5 menu "Virtual Memory Support"
10 Hidden option to enable virtual memory Kconfigs.
23 address from DTS, in which case RAM will be identity-mapped. Some
28 this for non-pinned page frames).
30 Otherwise, if RAM isn't identity-mapped:
36 regions if RAM is not identity-mapped, or the virtual and physical
38 double-linking of paging structures to make the instruction pointer
42 page tables are in use, they all have the same virtual-to-physical
53 build-time cases, or when a physical address cannot be looked up
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/Zephyr-latest/snippets/nordic-flpr/soc/
Dnrf54l15_cpuapp.overlay3 * SPDX-License-Identifier: Apache-2.0
8 reserved-memory {
9 #address-cells = <1>;
10 #size-cells = <1>;
17 cpuflpr_sram_code_data: memory@20028000 {
18 compatible = "mmio-sram";
20 #address-cells = <1>;
21 #size-cells = <1>;
37 execution-memory = <&cpuflpr_sram_code_data>;
38 source-memory = <&cpuflpr_code_partition>;
/Zephyr-latest/tests/kernel/mem_protect/mem_map/
Dprj_x86_64_coverage_exec.conf3 # Enable large memory model to avoid relative addressing
4 # so the execution test can run with the function at
6 CONFIG_COMPILER_OPT="-mcmodel=large"
/Zephyr-latest/dts/bindings/flash_controller/
Drenesas,smartbond-flash-controller.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "renesas,smartbond-flash-controller"
8 include: flash-controller.yaml
11 read-cs-idle-delay:
15 instructions to the flash memory, the SPI bus stays
19 erase-cs-idle-delay:
22 After the execution of instructions: write enable,
/Zephyr-latest/subsys/retention/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
10 Enables support for the retention system, which uses retained memory
20 priorities for retained memory drivers).
49 Adds a boot mode system that allows for changing execution flow
51 e.g. button-less bootloader serial recovery mode entering from the
55 byte must be created and set as the "zephyr,boot-mode" chosen node
63 module-str = retention
/Zephyr-latest/include/zephyr/arch/arm/mpu/
Darm_mpu_v8.h5 * SPDX-License-Identifier: Apache-2.0
10 /* Convenience macros to represent the ARMv8-M-specific
11 * configuration for memory access permission and
12 * cache-ability attribution.
66 /* Attribute flag for not-allowing execution (eXecute Never) */
69 /* Attribute flags for share-ability */
82 (((base & MPU_RBAR_BASE_Msk) + size - 1) & MPU_RLAR_LIMIT_Msk)
84 /* Attribute flags for cache-ability */
86 /* Memory Attributes for Device Memory
99 * Indicates to the memory system whether a buffer can send
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/Zephyr-latest/samples/boards/espressif/light_sleep/
DREADME.rst1 .. zephyr:code-sample:: esp32-light-sleep
4 Use light sleep mode on ESP32 to save power while preserving the state of the memory, CPU, and
11 light sleep preserves the state of the memory, CPU, and peripherals. Execution
13 When the chip exits light sleep mode, execution continues at the point where it
27 button, an external button can be connected, along with a 10k pull-up resistor,
33 .. zephyr-app-commands::
34 :zephyr-app: samples/boards/espressif/light_sleep
42 -----------------
48 .. code-block:: console
50 *** Booting Zephyr OS build zephyr-v3.1.0-3667-gb42e2b225ecf ***
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/Zephyr-latest/doc/kernel/services/threads/
Dindex.rst25 * A **stack area**, which is a region of memory used for the thread's stack.
28 stack memory regions.
46 * An **execution mode**, which can either be supervisor or user mode.
48 privileged CPU instructions, the entire memory address space, and
67 to start thread execution immediately. Alternatively, the kernel can be
68 instructed to delay execution of the thread by specifying a timeout
69 value -- for example, to allow device hardware used by the thread
75 re-spawned before it can be used.
81 synchronously end its execution by returning from its entry point function.
85 it may own (such as mutexes and dynamically allocated memory)
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/Zephyr-latest/arch/x86/
DKconfig3 # Copyright (c) 2014-2015 Wind River Systems, Inc.
4 # SPDX-License-Identifier: Apache-2.0
13 # CPU Families - the SoC configuration should select the right one.
61 # Configuration common to both IA32 and Intel64 sub-architectures.
65 bool "Run in 64-bit mode"
163 bool "Compiler-generated SSEx instructions for floating point math"
183 A lot of x86 that resemble PCs have many reserved physical memory
185 beginning of RAM to load the kernel in physical memory, avoiding these
189 bootstrap code within the first 64K of physical memory.
191 This value normally need to be page-aligned.
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/Zephyr-latest/boards/native/doc/
Darch_soc.rst22 Zephyr application, eliminating the need for architecture-specific
56 You must have the 32-bit C library installed in your system
57 (in Ubuntu 16.04 install the gcc-multilib package)
67 for Linux (WSL1) because WSL1 does not support native 32-bit binaries.
72 <https://github.com/microsoft/WSL/issues/2468#issuecomment-374904520>`_ it
102 - There can **not** be busy wait loops in the application code that wait for
105 will stall the execution. For example, the following busy wait loop code,
106 which could be interrupted on actual hardware, will stall the execution of
109 .. code-block:: c
117 .. code-block:: c
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/Zephyr-latest/arch/
DKconfig3 # Copyright (c) 2014-2015 Wind River Systems, Inc.
6 # SPDX-License-Identifier: Apache-2.0
18 # Should be 'select'ed by low-level symbols like SOC_SERIES_* or, lacking that,
37 # is really only necessary for Cortex-M with ARM MPU!
158 # POSIX arch based targets get their memory cleared on entry by the host OS
173 symbols above. See the top-level CMakeLists.txt.
180 module-str = arch
186 This option tells the build system that the target system is big-endian.
187 Little-endian architecture is the default and should leave this option
195 # Hidden Kconfig option representing the default little-endian architecture
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/Zephyr-latest/lib/heap/
DKconfig3 # SPDX-License-Identifier: Apache-2.0
5 menu "Heap and Memory Allocation"
14 environments that require sensitive detection of memory
60 such as memory allocation and de-allocation.
75 Heaps using reduced-size chunk headers can accommodate so called
78 Heaps using full-size chunk headers can have a total size up to
81 On 32-bit system the tradeoff is selectable between:
83 - "small" heaps with low memory and runtime overhead;
85 - "big" heaps with bigger memory overhead even for small heaps;
87 - "auto" providing optimal memory overhead in all cases but with
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