Lines Matching +full:execution +full:- +full:memory

4 # SPDX-License-Identifier: Apache-2.0
18 This option signifies the use of a CPU of the Cortex-A family.
31 This option signifies the use of a CPU of the Cortex-R 64-bit family.
38 This option signifies the use of a Cortex-A53 CPU
45 This option signifies the use of a Cortex-A55 CPU
52 This option signifies the use of a Cortex-A57 CPU
59 This option signifies the use of a Cortex-A72 CPU
66 This option signifies the use of a Cortex-A76 CPU
73 This option signifies the use of a Cortex-A76 and A55 big little CPU cluster
80 This option signifies the use of a Cortex-R82 CPU
123 and understood by loaders such as u-boot on Xen xl tool.
136 execution
203 bool "ARMv8-A Normal World (Non-Secure world of Trustzone)"
206 Non-Secure state
215 This option signifies the use of an ARMv8-A processor
218 From https://developer.arm.com/products/architecture/cpu-architecture/a-profile:
219 The Armv8-A architecture introduces the ability to use 64-bit and
220 32-bit Execution states, known as AArch64 and AArch32 respectively.
221 The AArch64 Execution state supports the A64 instruction set, holds
222 addresses in 64-bit registers and allows instructions in the base
223 instruction set to use 64-bit registers for their processing. The AArch32
224 Execution state is a 32-bit Execution state that preserves backwards
225 compatibility with the Armv7-A architecture and enhances that profile
241 This option signifies the use of an ARMv8-R processor
244 From https://developer.arm.com/products/architecture/cpu-architecture/r-profile:
245 The Armv8-R architecture targets at the Real-time profile. It introduces
247 Protected Memory System Architecture (PMSA) based on a Memory Protection
271 Memory Management Unit support.
298 bool "32-bit"
301 bool "36-bit"
304 bool "40-bit"
307 bool "42-bit"
310 bool "48-bit"
329 bool "32-bit"
332 bool "36-bit"
335 bool "40-bit"
338 bool "42-bit"
341 bool "48-bit"
364 memory regions (both normal and device memory) are present on given
366 attributes to these memory regions.