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/Zephyr-latest/dts/bindings/mtd/
Djedec,jesd216.yaml2 # Copyright (c) 2019-2020 Nordic Semiconductor ASA
3 # SPDX-License-Identifier: Apache-2.0
21 jedec-id:
22 type: uint8-array
29 sfdp-bfp:
30 type: uint8-array
32 Contains the 32-bit words in little-endian byte order from the
34 Parameters table. This provides flash-specific configuration
38 quad-enable-requirements:
41 - "NONE"
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Djedec,spi-nor-common.yaml3 # SPDX-License-Identifier: Apache-2.0
5 # Common properties used by nodes describing M25P80-compatible SPI NOR
8 # This extends JESD216-defined features with additional functionality
9 # that may be specific to the vendor of a M25P80-compatible device and
17 requires-ulbpr:
23 protection register that initializes to write-protected. Use this
27 has-dpd:
33 Power-Down mode that is entered by command 0xB9 to reduce power
37 Electronic Signature; see t-enter-dpd).
39 dpd-wakeup-sequence:
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/Zephyr-latest/tests/drivers/flash/common/boards/
Dnrf52840dk_mx25l51245g.overlay4 * SPDX-License-Identifier: Apache-2.0
7 /delete-node/ &mx25r64;
27 low-power-enable;
31 low-power-enable;
32 bias-pull-up;
38 pinctrl-0 = <&qspi_default>;
39 pinctrl-1 = <&qspi_sleep>;
40 pinctrl-names = "default", "sleep";
43 compatible = "nordic,qspi-nor";
49 sck-frequency = <2000000>;
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/Zephyr-latest/drivers/cache/
Dcache_aspeed.c4 * SPDX-License-Identifier: Apache-2.0
14 * 0: no-cache
28 #define CACHED_SRAM_END (CACHED_SRAM_ADDR + CACHED_SRAM_SIZE - 1)
33 #define DCACHE_INVALID(addr) (BIT(31) | ((addr & GENMASK(10, 0)) << 16)) argument
34 #define ICACHE_INVALID(addr) (BIT(15) | ((addr & GENMASK(10, 0)) << 0)) argument
40 /* cache size = 32B * 128 = 4KB */
44 #define CACHE_ALIGNED_ADDR(addr) \ argument
45 ((addr >> CACHE_LINE_SIZE_LOG2) << CACHE_LINE_SIZE_LOG2)
55 /* set all cache areas to no-cache by default */ in aspeed_cache_init()
59 max_bit = 8 * sizeof(uint32_t) - 1; in aspeed_cache_init()
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/Zephyr-latest/include/zephyr/drivers/i3c/
Dccc.h5 * SPDX-License-Identifier: Apache-2.0
46 * Enter Activity State
54 * Enter Activity State 0
61 * Enter Activity State 1
68 * Enter Activity State 2
75 * Enter Activity State 3
84 /** Enter Dynamic Address Assignment (Broadcast) */
104 /** Enter Test Mode (Broadcast) */
117 /** Enter HDR Mode (HDR-DDR) (Broadcast) */
120 /** Enter HDR Mode 0 (HDR-DDR) (Broadcast) */
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/Zephyr-latest/drivers/flash/
Dflash_ite_it8xxx2.c4 * SPDX-License-Identifier: Apache-2.0
19 #include <zephyr/linker/linker-defs.h>
50 * ILM(ILM -> CPU)instead of flash(flash -> I-Cache -> CPU) if enabled.
56 /* sector erase command (erase size is 4KB) */
98 /* I-Cache tag sram reset */ in ramcode_reset_i_cache()
99 gctrl_regs->GCTRL_MCCR |= IT8XXX2_GCTRL_ICACHE_RESET; in ramcode_reset_i_cache()
100 /* Make sure the I-Cache is reset */ in ramcode_reset_i_cache()
103 gctrl_regs->GCTRL_MCCR &= ~IT8XXX2_GCTRL_ICACHE_RESET; in ramcode_reset_i_cache()
111 * ECINDAR3-0 are EC-indirect memory address registers. in ramcode_flash_follow_mode()
113 * Enter follow mode by writing 0xf to low nibble of ECINDAR3 register, in ramcode_flash_follow_mode()
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Dspi_nor.c2 * Copyright (c) 2018 Savoir-Faire Linux.
8 * SPDX-License-Identifier: Apache-2.0
36 * * Some devices support a Deep Power-Down mode which reduces current
41 * * PM_DEVICE_STATE_SUSPENDED corresponds to deep-power-down mode;
45 #define SPI_NOR_MAX_ADDR_WIDTH 4
63 #define DEV_CFG(_dev_) ((const struct spi_nor_config * const) (_dev_)->config)
66 /* MXICY Low-power/high perf mode is second bit in configuration register 2 */
72 /* Build-time data associated with the device. */
92 /* Expected JEDEC ID, from jedec-id property */
96 /* Optional support for entering 32-bit address mode. */
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Dnrf_qspi_nor.c2 * Copyright (c) 2019-2024, Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
69 #error "No size specified. 'size' or 'size-in-bytes' must be set"
73 "Node " DT_NODE_PATH(DT_DRV_INST(0)) " has both size and size-in-bytes "
80 * frequencies 2 - 32 MHz and the nRF53 one supports 6 - 96 MHz.
93 * On nRF53 Series SoCs, the default /4 divider for the HFCLK192M clock can
108 INST_0_SCK_FREQUENCY) - 1)
121 INST_0_SCK_FREQUENCY) - 1)
140 INST_0_SCK_FREQUENCY) - 1)
178 … "Driver only supports NONE, S1B6, S2B1v1, S2B1v4, S2B1v5 or S2B1v6 for quad-enable-requirements");
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Dflash_mcux_flexspi_nor.c4 * SPDX-License-Identifier: Apache-2.0
39 read-while-write hazards. This configuration is not recommended."
91 /* 1S-1S-1S flash read command, should be compatible with all SPI nor flashes */
107 /* Standard 1S-1S-1S flash write command, can be switched to 1S-1S-4S when QE is set */
155 .port = data->port, in flash_flexspi_nor_read_id_helper()
165 ret = memc_flexspi_transfer(&data->controller, &transfer); in flash_flexspi_nor_read_id_helper()
177 struct flash_flexspi_nor_data *data = dev->data; in flash_flexspi_nor_read_id()
187 .port = data->port, in flash_flexspi_nor_read_status()
197 return memc_flexspi_transfer(&data->controller, &transfer); in flash_flexspi_nor_read_status()
204 .port = data->port, in flash_flexspi_nor_write_enable()
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Dflash_stm32_qspi.c6 * SPDX-License-Identifier: Apache-2.0
28 DT_INST_PROP(0, spi_bus_width) == 4
58 /* In dual-flash mode, total size is twice the size of one flash component */
125 * If set addressed operations should use 32-bit rather than
126 * 24-bit addresses.
138 struct flash_stm32_qspi_data *dev_data = dev->data; in qspi_lock_thread()
140 k_sem_take(&dev_data->sem, K_FOREVER); in qspi_lock_thread()
145 struct flash_stm32_qspi_data *dev_data = dev->data; in qspi_unlock_thread()
147 k_sem_give(&dev_data->sem); in qspi_unlock_thread()
153 struct flash_stm32_qspi_data *dev_data = dev->data; in qspi_set_address_size()
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/Zephyr-latest/samples/drivers/jesd216/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
40 [JESD216_MODE_111] = "1-1-1",
41 [JESD216_MODE_112] = "1-1-2",
42 [JESD216_MODE_114] = "1-1-4",
43 [JESD216_MODE_118] = "1-1-8",
44 [JESD216_MODE_122] = "1-2-2",
45 [JESD216_MODE_144] = "1-4-4",
46 [JESD216_MODE_188] = "1-8-8",
47 [JESD216_MODE_222] = "2-2-2",
48 [JESD216_MODE_444] = "4-4-4",
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/Zephyr-latest/subsys/debug/gdbstub/
Dgdbstub.c4 * SPDX-License-Identifier: Apache-2.0
52 * @param addr Starting address of the memory block
61 #pragma GCC diagnostic ignored "-Warray-bounds"
65 struct gdb_mem_region *find_memory_region(const uintptr_t addr, const size_t len) in find_memory_region() argument
73 if ((addr >= r->start) && in find_memory_region()
74 (addr < r->end) && in find_memory_region()
75 ((addr + len) >= r->start) && in find_memory_region()
76 ((addr + len) < r->end)) { in find_memory_region()
89 bool gdb_mem_can_read(const uintptr_t addr, const size_t len, uint8_t *align) in gdb_mem_can_read() argument
103 r = find_memory_region(addr, len); in gdb_mem_can_read()
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/Zephyr-latest/boards/beagle/beaglev_fire/doc/
Dindex.rst6 BeagleV®-Fire is a revolutionary single-board computer (SBC) powered by the Microchip’s
7 PolarFire® MPFS025T 5x core RISC-V System on Chip (SoC) with FPGA fabric. BeagleV®-Fire opens up new
8 horizons for developers, tinkerers, and the open-source community to explore the vast potential of
9 RISC-V architecture and FPGA technology. It has the same P8 & P9 cape header pins as BeagleBone
11 Built around the powerful and energy-efficient RISC-V instruction set architecture (ISA) along with
12 its versatile FPGA fabric, BeagleV®-Fire SBC offers unparalleled opportunities for developers,
13 hobbyists, and researchers to explore and experiment with RISC-V technology.
18 There are three board configurations provided for the BeagleV-Fire:
26 .. zephyr-app-commands::
27 :zephyr-app: samples/hello_world
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/Zephyr-latest/drivers/i2c/
Di2c_ite_it8xxx2.c4 * SPDX-License-Identifier: Apache-2.0
18 #include <zephyr/dt-bindings/i2c/it8xxx2-i2c.h>
25 #include "i2c-priv.h"
79 /* Read or write byte counts. */
114 /* Time-out error */
116 /* Byte done status */
121 /* W/C for next byte */
134 const struct i2c_it8xxx2_config *config = dev->config; in i2c_parsing_return_value()
135 struct i2c_it8xxx2_data *data = dev->data; in i2c_parsing_return_value()
137 if (!data->err) { in i2c_parsing_return_value()
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Di2c_ite_enhance.c4 * SPDX-License-Identifier: Apache-2.0
23 #include "i2c-priv.h"
34 #define I2C_CQ_MODE_TX_MAX_PAYLOAD_SIZE (CONFIG_I2C_CQ_MODE_MAX_PAYLOAD_SIZE - 5)
46 #define I2C_CQ_CMD_L_E BIT(4)
97 uint8_t i2c_cq_mode_tx_dlm[CONFIG_I2C_CQ_MODE_MAX_PAYLOAD_SIZE] __aligned(4);
99 uint8_t i2c_cq_mode_rx_dlm[CONFIG_I2C_CQ_MODE_MAX_PAYLOAD_SIZE] __aligned(4);
105 * is one byte more than the maximum buffer size. Therefore, it is necessary to
108 #define PROTECT_MEM_BUF 4
111 uint8_t __aligned(4)
114 uint8_t __aligned(4)
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Di2c_mchp_xec_v2.c5 * SPDX-License-Identifier: Apache-2.0
25 #include "i2c-priv.h"
112 * i2c_baud_clk_period/bus_clk_period - 2 = (low_period + hi_period)
113 * bus_clk_reg (16MHz/100KHz -2) = 0x4F + 0x4F
114 * (16MHz/400KHz -2) = 0x0F + 0x17
115 * (16MHz/1MHz -2) = 0x05 + 0x09
144 (const struct i2c_xec_config *const) (dev->config); in i2c_ctl_wr()
146 (struct i2c_xec_data *const) (dev->data); in i2c_ctl_wr()
147 struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr; in i2c_ctl_wr()
149 data->i2c_ctrl = ctrl; in i2c_ctl_wr()
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/Zephyr-latest/include/zephyr/drivers/
Di2c.h10 * SPDX-License-Identifier: Apache-2.0
65 /** Use 10-bit addressing. DEPRECATED - Use I2C_MSG_ADDR_10_BITS instead. */
69 #define I2C_MODE_CONTROLLER BIT(4)
75 * @param addr is the target address
79 uint16_t addr; member
94 .addr = DT_PROP_BY_IDX(node_id, reg, 0)
108 .addr = DT_REG_ADDR(node_id)
160 * that follows a write, or vice-versa. Some drivers will merge
165 /** Use 10-bit addressing for this message.
199 * @param result Result code of the transfer request. 0 is success, -errno for failure.
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/Zephyr-latest/drivers/sensor/bosch/bmi270/
Dbmi270.c5 * SPDX-License-Identifier: Apache-2.0
29 const struct bmi270_config *cfg = dev->config; in bmi270_bus_check()
31 return cfg->bus_io->check(&cfg->bus); in bmi270_bus_check()
36 const struct bmi270_config *cfg = dev->config; in bmi270_bus_init()
38 return cfg->bus_io->init(&cfg->bus); in bmi270_bus_init()
43 const struct bmi270_config *cfg = dev->config; in bmi270_reg_read()
45 return cfg->bus_io->read(&cfg->bus, reg, data, length); in bmi270_reg_read()
51 const struct bmi270_config *cfg = dev->config; in bmi270_reg_write()
53 return cfg->bus_io->write(&cfg->bus, reg, data, length); in bmi270_reg_write()
78 val->val1 = raw_val / 1000000LL; in channel_accel_convert()
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/Zephyr-latest/subsys/bluetooth/host/shell/
Dbt.c11 * SPDX-License-Identifier: Apache-2.0
76 * See BT Core Spec V5.2 Vol. 4, Part E, section 7.8.37
119 static void print_le_addr(const char *desc, const bt_addr_le_t *addr) in print_le_addr() argument
123 const char *addr_desc = bt_addr_le_is_identity(addr) ? "identity" : in print_le_addr()
124 bt_addr_le_is_rpa(addr) ? "resolvable" : in print_le_addr()
125 "non-resolvable"; in print_le_addr()
127 bt_addr_le_to_str(addr, addr_str, sizeof(addr_str)); in print_le_addr()
218 bt_addr_le_t addr; member
249 char addr[BT_ADDR_STR_LEN]; member
310 switch (data->type) { in data_cb()
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/Zephyr-latest/drivers/usb/udc/
Dudc_dwc2.c4 * SPDX-License-Identifier: Apache-2.0
36 /* Core should enter hibernation */
44 /* Minimum RX FIFO size in 32-bit words considering the largest used OUT packet
48 #define UDC_DWC2_GRXFSIZ_FS_DEFAULT (15U + 512U/4U)
49 /* Default Rx FIFO size in 32-bit words calculated to support High-Speed with:
52 * * Space for 3 * 1024 packets: ((1024/4) + 1) * 3 = 774 locations
57 /* TX FIFO0 depth in 32-bit words (used by control IN endpoint)
105 /* Transfer triggers (IN on bits 0-15, OUT on bits 16-31) */
107 /* Finished transactions (IN on bits 0-15, OUT on bits 16-31) */
143 const struct udc_dwc2_config *const config = dev->config; in dwc2_init_pinctrl()
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/Zephyr-latest/drivers/ieee802154/
Dieee802154_nrf5.c1 /* ieee802154_nrf5.c - nRF5 802.15.4 driver */
4 * Copyright (c) 2017-2023 Nordic Semiconductor ASA
6 * SPDX-License-Identifier: Apache-2.0
77 #error "NRF_UICR->OTP is not supported to read from non-secure"
79 #define EUI64_ADDR (NRF_UICR->OTP)
82 #define EUI64_ADDR (NRF_UICR->CUSTOMER)
96 ((struct nrf5_802154_data * const)(dev)->data)
99 ((const struct nrf5_802154_config * const)(dev)->config)
124 /* Set the MAC Address Block Larger (MA-L) formerly called OUI. */ in nrf5_get_eui64()
130 /* Can't access SICR with device id on a radio core. Use BLE.ADDR. */ in nrf5_get_eui64()
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/Zephyr-latest/drivers/disk/nvme/
Dnvme.h3 * SPDX-License-Identifier: Apache-2.0
27 uint64_t asq; /* admin submission queue base addr */
28 uint64_t acq; /* admin completion queue base addr */
36 uint8_t reserved3[3492]; /* 5Ch - DFFh */
44 uint8_t reserved4[484]; /* E1Ch - FFFh */
56 /** Max Power Scale, Non-Operational State */
98 /* bytes 0-255: controller capabilities and features */
121 /** multi-interface capabilities */
136 /** RTD3 Enter Latency */
167 /* bytes 256-511: admin command set attributes */
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/Zephyr-latest/tests/bluetooth/tester/src/
Dbtp_gap.c1 /* gap.c - Bluetooth GAP Tester */
4 * Copyright (c) 2015-2016 Intel Corporation
6 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/bluetooth/addr.h>
61 bt_addr_le_t addr; member
95 if (bt_addr_le_eq(info.le.dst, &cars[i].addr)) { in read_car_cb()
139 const bt_addr_le_t *addr = bt_conn_get_dst(conn); in le_disconnected() local
145 bt_addr_le_copy(&ev.address, addr); in le_disconnected()
165 const bt_addr_le_t *addr = bt_conn_get_dst(conn); in le_param_updated() local
167 bt_addr_le_copy(&ev.address, addr); in le_param_updated()
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/Zephyr-latest/drivers/gpio/
Dgpio_pca_series.c4 * SPDX-License-Identifier: Apache-2.0
8 * @file Driver for PCA(L)xxxx SERIES I2C-based GPIO expander.
34 #define PCA_HAS_OUT_CONFIG BIT(4) /** + input_status, + output_config */
70 * - Type 0: PCA953X, PCA955X
71 * - Type 1: PCAL953X, PCAL955X, PCAL64XXA
72 * - Type 2: PCA957X
73 * - Type 3: PCAL65XX
103 * port-level "pin output configuration" register.
144 uint8_t port_no; /* number of 8-pin ports on device */
171 * - if CONFIG_GPIO_PCA_SERIES_CACHE_ALL is set,
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/Zephyr-latest/include/zephyr/arch/
Darch_interface.h4 * SPDX-License-Identifier: Apache-2.0
8 * @defgroup arch-interface Architecture Interface
13 * call architecture-specific API so will have the prototypes for the
14 * architecture-specific APIs here. Architecture APIs that aren't used in this
17 * The set of architecture-specific APIs used internally by public macros and
53 * @defgroup arch-timing Architecture timing APIs
54 * @ingroup arch-interface
82 * through the full 64 bit space, wrapping at 2^64-1. Hardware with
92 * @addtogroup arch-threads
126 * buffer, defined as the area usable for thread stack context and thread-
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