4  * SPDX-License-Identifier: Apache-2.0
14  *	0: no-cache
28 #define CACHED_SRAM_END		(CACHED_SRAM_ADDR + CACHED_SRAM_SIZE - 1)
33 #define DCACHE_INVALID(addr)	(BIT(31) | ((addr & GENMASK(10, 0)) << 16))  argument
34 #define ICACHE_INVALID(addr)	(BIT(15) | ((addr & GENMASK(10, 0)) << 0))  argument
40 /* cache size = 32B * 128 = 4KB */
44 #define CACHE_ALIGNED_ADDR(addr) \  argument
45 	((addr >> CACHE_LINE_SIZE_LOG2) << CACHE_LINE_SIZE_LOG2)
55 	/* set all cache areas to no-cache by default */  in aspeed_cache_init()
59 	max_bit = 8 * sizeof(uint32_t) - 1;  in aspeed_cache_init()
70  * @param [IN] addr - start address to be invalidated
71  * @param [IN] size - size in byte
72  * @param [OUT] p_aligned_addr - pointer to the cacheline aligned address variable
75  *  * addr
76  *   |--------size-------------|
77  * |-----|-----|-----|-----|-----|
82  * addr = 0x100 (cacheline aligned), size = 64
87  * addr = 0x104 (cacheline unaligned), size = 64
91 static uint32_t get_n_cacheline(uint32_t addr, uint32_t size, uint32_t *p_head)  in get_n_cacheline()  argument
97 	*p_head = CACHE_ALIGNED_ADDR(addr);  in get_n_cacheline()
100 	tail = addr + size + (CACHE_LINE_SIZE - 1);  in get_n_cacheline()
103 	n = (tail - *p_head) >> CACHE_LINE_SIZE_LOG2;  in get_n_cacheline()
140 	/* enter critical section */  in cache_data_invd_all()
161 int cache_data_invd_range(void *addr, size_t size)  in cache_data_invd_range()  argument
167 	if (((uint32_t)addr < CACHED_SRAM_ADDR) ||  in cache_data_invd_range()
168 	    ((uint32_t)addr > CACHED_SRAM_END)) {  in cache_data_invd_range()
172 	/* enter critical section */  in cache_data_invd_range()
177 	n = get_n_cacheline((uint32_t)addr, size, &aligned_addr);  in cache_data_invd_range()
202 	/* enter critical section */  in cache_instr_invd_all()
222 int cache_instr_invd_range(void *addr, size_t size)  in cache_instr_invd_range()  argument
228 	if (((uint32_t)addr < CACHED_SRAM_ADDR) ||  in cache_instr_invd_range()
229 	    ((uint32_t)addr > CACHED_SRAM_END)) {  in cache_instr_invd_range()
233 	n = get_n_cacheline((uint32_t)addr, size, &aligned_addr);  in cache_instr_invd_range()
235 	/* enter critical section */  in cache_instr_invd_range()
257 	return -ENOTSUP;  in cache_data_flush_all()
262 	return -ENOTSUP;  in cache_data_flush_and_invd_all()
265 int cache_data_flush_range(void *addr, size_t size)  in cache_data_flush_range()  argument
267 	ARG_UNUSED(addr);  in cache_data_flush_range()
270 	return -ENOTSUP;  in cache_data_flush_range()
273 int cache_data_flush_and_invd_range(void *addr, size_t size)  in cache_data_flush_and_invd_range()  argument
275 	ARG_UNUSED(addr);  in cache_data_flush_and_invd_range()
278 	return -ENOTSUP;  in cache_data_flush_and_invd_range()
283 	return -ENOTSUP;  in cache_instr_flush_all()
288 	return -ENOTSUP;  in cache_instr_flush_and_invd_all()
291 int cache_instr_flush_range(void *addr, size_t size)  in cache_instr_flush_range()  argument
293 	ARG_UNUSED(addr);  in cache_instr_flush_range()
296 	return -ENOTSUP;  in cache_instr_flush_range()
299 int cache_instr_flush_and_invd_range(void *addr, size_t size)  in cache_instr_flush_and_invd_range()  argument
301 	ARG_UNUSED(addr);  in cache_instr_flush_and_invd_range()
304 	return -ENOTSUP;  in cache_instr_flush_and_invd_range()