1# Copyright (c) 2018 Peter Bigot Consulting, LLC 2# Copyright (c) 2019 Nordic Semiconductor ASA 3# SPDX-License-Identifier: Apache-2.0 4 5# Common properties used by nodes describing M25P80-compatible SPI NOR 6# serial flash devices, regardless of which Zephyr driver is being used. 7# 8# This extends JESD216-defined features with additional functionality 9# that may be specific to the vendor of a M25P80-compatible device and 10# only supported in certain drivers. Any information that can be 11# obtained from standardized SFDP parameter blocks should be in 12# jedec,jesd216.yaml instead. 13 14include: "jedec,jesd216.yaml" 15 16properties: 17 requires-ulbpr: 18 type: boolean 19 description: | 20 Indicates the device requires the ULBPR (0x98) command. 21 22 Some flash chips such as the Microchip SST26VF series have a block 23 protection register that initializes to write-protected. Use this 24 property to indicate that the BPR must be unlocked before write 25 operations can proceed. 26 27 has-dpd: 28 type: boolean 29 description: | 30 Indicates the device supports the DPD (0xB9) command. 31 32 Use this property to indicate the flash chip supports the Deep 33 Power-Down mode that is entered by command 0xB9 to reduce power 34 consumption below normal standby levels. Use of this property 35 implies that the RDPD (0xAB) Release from Deep Power Down command 36 is also supported. (On some chips this command functions as Read 37 Electronic Signature; see t-enter-dpd). 38 39 dpd-wakeup-sequence: 40 type: array 41 description: | 42 Specifies wakeup durations for devices without RDPD. 43 44 Some devices (Macronix MX25R in particular) wake from deep power 45 down by a timed sequence of CSn toggles rather than the RDPD 46 command. This property specifies three durations measured in 47 nanoseconds, in this order: 48 (1) tDPDD (Delay Time for Release from Deep Power-Down Mode) 49 (2) tCDRP (CSn Toggling Time before Release from Deep Power-Down Mode) 50 (3) tRDP (Recovery Time for Release from Deep Power-Down Mode) 51 52 Absence of this property indicates that the RDPD command should be 53 used to wake the chip from Deep Power-Down mode. 54 55 t-enter-dpd: 56 type: int 57 description: | 58 Duration required to complete the DPD command. 59 60 This provides the duration, in nanoseconds, that CSn must be 61 remain deasserted after issuing DPD before the chip will enter 62 deep power down. 63 64 If not provided the driver does not enforce a delay. 65 66 t-exit-dpd: 67 type: int 68 description: | 69 Duration required to complete the RDPD command. 70 71 This provides the duration, in nanoseconds, that CSn must be 72 remain deasserted after issuing RDPD before the chip will exit 73 deep power down and be ready to receive additional commands. 74 75 If not provided the driver does not enforce a delay. 76 77 has-lock: 78 type: int 79 description: | 80 Bit mask of bits of the status register that should be cleared on 81 startup. 82 83 Some devices from certain vendors power-up with block protect bits 84 set in the status register, which prevent any erase or program 85 operation from working. Devices that have this behavior need to 86 clear those bits on startup. However, other devices have 87 non-volatile bits in the status register that should not be 88 cleared. 89 90 This value, when present, identifies bits in the status register 91 that should be cleared when the device is initialized. 92 93 mxicy,mx25r-power-mode: 94 type: string 95 enum: 96 - "low-power" 97 - "high-performance" 98 description: 99 Select to configure flash to use ultra low power mode or high 100 performance mode (L/H switch). The high performance mode has 101 faster write and erase performance, but use more power than ultra 102 low power mode. 103 104 Only supported on Macronix MX25R Ultra Low Power series. 105 106 use-4b-addr-opcodes: 107 type: boolean 108 description: | 109 Indicates the device uses special 4-byte address opcodes. 110 Instead of switching to 4-byte addressing mode, the device uses 111 special opcodes for 4-byte addressing. 112 113 Some devices support 4-byte address opcodes for read/write/erase 114 operations. Use this property to indicate that the device supports 115 4-byte address opcodes. 116