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/Zephyr-latest/dts/bindings/sensor/
Dlm77.yaml2 # SPDX-License-Identifier: Apache-2.0
9 include: [sensor-device.yaml, i2c-device.yaml]
12 int-gpios:
13 type: phandle-array
15 Identifies the INT signal, which is active-low open drain by default
18 int-inverted:
21 When present, the polarity on the INT signal is inverted (active-high).
23 tcrita-inverted:
26 When present, the polarity on the T_CRIT_A signal is inverted
27 (active-high).
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/Zephyr-latest/boards/shields/lcd_par_s035/boards/
Drd_rw612_bga.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
11 * - Depopulate resistors R78, R604, R598, R15, R245, R243, R11, R20, R237,
13 * - Populate resistors R286, R19, R246, R242, R123, R239, R124, R125, R236,
15 * - Remove jumper JP30
16 * - Set jumper JP40 to postion 1-2, JP38 to 1-2, and JP16 to position 2-3
21 * ON-ON-OFF (8 bit 8080 mode), and connect the following pins
23 * |-----------|-------------|----------|
62 slew-rate = "ultra";
67 mipi-mode = "MIPI_DBI_MODE_8080_BUS_8_BIT";
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/Zephyr-latest/soc/nuvoton/npcx/common/
Dscfg.c4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/pinctrl/npcx-pinctrl.h>
28 * GPIO in pin-mux init function.
30 * def-io-conf-list {
39 .inverted = DT_PHA(DT_PROP_BY_IDX(node_id, prop, idx), alts, inv), \
58 /* Pin-control local functions */
62 uint8_t alt_mask = BIT(alt->bit); in npcx_pinctrl_alt_sel()
66 * inverted == 0: in npcx_pinctrl_alt_sel()
68 * inverted == 1: in npcx_pinctrl_alt_sel()
71 if (!!alt_func != !!alt->inverted) { in npcx_pinctrl_alt_sel()
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Dsoc_pins.h4 * SPDX-License-Identifier: Apache-2.0
19 * @brief NPCX pin-mux configuration structure
22 * pin-muxing and its polarity to enable alternative functionality.
27 uint8_t inverted:1; member
32 * @brief NPCX low-voltage configuration structure
35 * low-voltage detection.
38 uint8_t ctrl:5; /** Related register index for low-voltage conf. */
39 uint8_t bit:3; /** Related register bit for low-voltage conf. */
51 * @brief Force the internal SPI flash write-protect pin (WP) to low level to
64 * @brief Enable low-voltage input detection
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/Zephyr-latest/drivers/serial/
Duart_pl011_registers.h6 * SPDX-License-Identifier: Apache-2.0
45 #define PL011_BIT_MASK(x, y) (((2 << x) - 1) << y)
48 #define PL011_FR_CTS BIT(0) /* clear to send - inverted */
49 #define PL011_FR_DSR BIT(1) /* data set ready - inverted */
50 #define PL011_FR_DCD BIT(2) /* data carrier detect - inverted */
56 #define PL011_FR_RI BIT(8) /* ring indicator - inverted */
76 #define PL011_LCRH_PEN BIT(1) /* enable parity */
79 #define PL011_LCRH_FEN BIT(4) /* enable FIFOs */
84 #define PL011_LCRH_WLEN_SIZE(x) (x - 5)
95 #define PL011_CR_UARTEN BIT(0) /* enable uart operations */
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/Zephyr-latest/drivers/pwm/
Dpwm_sam0_tc.c7 * SPDX-License-Identifier: Apache-2.0
14 * The 8-bit counter operates in Normal PWM (NPWM) mode, it supports pulse width and period
16 * however, it is not suitable for high-precision or low-frequency applications.
18 * The 16-bit counter operates in Match PWM (MPWM) mode to generate the PWM signal.
56 while (regs->COUNT8.SYNCBUSY.reg != 0) { in wait_synchronization()
59 while (regs->COUNT16.SYNCBUSY.reg != 0) { in wait_synchronization()
67 const struct pwm_sam0_config *const cfg = dev->config; in pwm_sam0_get_cycles_per_sec()
69 if (channel >= cfg->channels) { in pwm_sam0_get_cycles_per_sec()
70 return -EINVAL; in pwm_sam0_get_cycles_per_sec()
73 *cycles = cfg->freq; in pwm_sam0_get_cycles_per_sec()
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Dpwm_sam0_tcc.c4 * SPDX-License-Identifier: Apache-2.0
42 while (regs->SYNCBUSY.reg != 0) { in wait_synchronization()
49 const struct pwm_sam0_config *const cfg = dev->config; in pwm_sam0_get_cycles_per_sec()
51 if (channel >= cfg->channels) { in pwm_sam0_get_cycles_per_sec()
52 return -EINVAL; in pwm_sam0_get_cycles_per_sec()
54 *cycles = cfg->freq; in pwm_sam0_get_cycles_per_sec()
63 const struct pwm_sam0_config *const cfg = dev->config; in pwm_sam0_set_cycles()
64 Tcc *regs = cfg->regs; in pwm_sam0_set_cycles()
65 uint32_t top = 1 << cfg->counter_size; in pwm_sam0_set_cycles()
68 bool inverted = ((regs->DRVCTRL.vec.INVEN & invert_mask) != 0); in pwm_sam0_set_cycles() local
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Dpwm_mc_esp32.c4 * SPDX-License-Identifier: Apache-2.0
81 bool inverted; member
105 struct mcpwm_esp32_config *config = (struct mcpwm_esp32_config *)dev->config; in mcpwm_esp32_duty_set()
106 struct mcpwm_esp32_data *data = (struct mcpwm_esp32_data *const)(dev)->data; in mcpwm_esp32_duty_set()
110 if (channel->inverted) { in mcpwm_esp32_duty_set()
111 duty_type = channel->duty == 0 ? in mcpwm_esp32_duty_set()
112 MCPWM_HAL_GENERATOR_MODE_FORCE_HIGH : channel->duty == 100 ? in mcpwm_esp32_duty_set()
115 duty_type = channel->duty == 0 ? in mcpwm_esp32_duty_set()
116 MCPWM_HAL_GENERATOR_MODE_FORCE_LOW : channel->duty == 100 ? in mcpwm_esp32_duty_set()
120 uint32_t timer_clk_hz = data->mcpwm_clk_hz / config->prescale / channel->prescale; in mcpwm_esp32_duty_set()
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Dpwm_npcx.c4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/clock/npcx_clock.h>
20 /* 16-bit period cycles/prescaler in NPCX PWM modules */
30 /* PWM heart-beat mode selection */
55 const struct pwm_npcx_config *config = dev->config; in pwm_npcx_configure()
56 struct pwm_reg *inst = config->base; in pwm_npcx_configure()
59 inst->PWMCTL &= ~BIT(NPCX_PWMCTL_PWR); in pwm_npcx_configure()
62 inst->PWMCTL &= ~BIT(NPCX_PWMCTL_INVP); in pwm_npcx_configure()
64 /* Turn off PWM heart-beat mode */ in pwm_npcx_configure()
65 SET_FIELD(inst->PWMCTL, NPCX_PWMCTL_HB_DC_CTL_FIELD, in pwm_npcx_configure()
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Dpwm_ite_it8xxx2.c4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/dt-bindings/pwm/it8xxx2_pwm.h>
54 const struct pwm_it8xxx2_cfg *config = dev->config; in pwm_enable()
55 volatile uint8_t *reg_pcsgr = (uint8_t *)config->reg_pcsgr; in pwm_enable()
56 int ch = config->channel; in pwm_enable()
74 * 1) pwm_set_cycles_usec() -> pwm_set_cycles_cycles() -> pwm_it8xxx2_set_cycles() in pwm_it8xxx2_get_cycles_per_sec()
78 * 2) pwm_set_cycles_nsec() -> pwm_set_cycles_cycles() -> pwm_it8xxx2_set_cycles() in pwm_it8xxx2_get_cycles_per_sec()
82 * 3) pwm_set_cycles_cycles() -> pwm_it8xxx2_set_cycles() in pwm_it8xxx2_get_cycles_per_sec()
99 const struct pwm_it8xxx2_cfg *config = dev->config; in pwm_it8xxx2_set_cycles()
100 struct pwm_it8xxx2_regs *const inst = config->base; in pwm_it8xxx2_set_cycles()
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/Zephyr-latest/dts/bindings/display/
Dsitronix,st7735r.yaml1 # Copyright (c) 2020, Kim Bøndergaard <kim@fam-boendergaard.dk>
2 # SPDX-License-Identifier: Apache-2.0
8 include: [mipi-dbi-spi-device.yaml, display-controller.yaml]
11 x-offset:
16 y-offset:
32 type: uint8-array
37 type: uint8-array
42 type: uint8-array
47 type: uint8-array
52 type: uint8-array
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/Zephyr-latest/soc/nxp/imxrt/imxrt5xx/cm33/
Dsoc.h2 * Copyright 2022-2023, NXP
4 * SPDX-License-Identifier: Apache-2.0
11 * This header file is used to specify and describe board-level aspects for the
54 /*!<@brief Input function is not inverted */
56 /*!<@brief Input function is inverted */
62 /*!<@brief Enable pull-down function */
64 /*!<@brief Enable pull-up function */
66 /*!<@brief Disable pull-up / pull-down function */
68 /*!<@brief Enable pull-up / pull-down function */
/Zephyr-latest/soc/nxp/imxrt/imxrt6xx/cm33/
Dsoc.h4 * SPDX-License-Identifier: Apache-2.0
11 * This header file is used to specify and describe board-level aspects for the
57 /*!<@brief Input function is not inverted */
59 /*!<@brief Input function is inverted */
65 /*!<@brief Enable pull-down function */
67 /*!<@brief Enable pull-up function */
69 /*!<@brief Disable pull-up / pull-down function */
71 /*!<@brief Enable pull-up / pull-down function */
/Zephyr-latest/boards/particle/boron/
Dparticle_boron.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include "particle_boron-pinctrl.dtsi"
19 vctl1-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
20 /* on Boron VCTL2 is inverted VCTL1 signal via SN74LVC1G04
21 * single inverter gate -- requires a definition below,
23 vctl2-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
27 en_buff_pwr: enable-buff-pwr {
28 compatible = "regulator-fixed";
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/Zephyr-latest/dts/bindings/serial/
Dst,stm32-uart-base.yaml2 # SPDX-License-Identifier: Apache-2.0
5 description: STM32 UART-BASE
8 - name: uart-controller.yaml
9 property-blocklist:
10 - clock-frequency
11 - name: pinctrl-device.yaml
12 - name: reset-device.yaml
13 - name: uart-controller-pin-inversion.yaml
28 single-wire:
31 Enable the single wire half-duplex communication.
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/Zephyr-latest/samples/sensor/qdec/
DREADME.rst1 .. zephyr:code-sample:: qdec
3 :relevant-api: sensor_interface
23 * enable the quadrature decoder device in your board's DT file or board overlay
30 .. code-block:: dts
43 pinctrl-0 = <&tim3_ch1_pa6 &tim3_ch2_pa7>;
44 pinctrl-names = "default";
45 st,input-polarity-inverted;
46 st,input-filter-level = <FDIV32_N8>;
47 st,counts-per-revolution = <16>;
57 .. code-block:: console
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/Zephyr-latest/dts/bindings/regulator/
Dnxp,pca9420.yaml2 # SPDX-License-Identifier: Apache-2.0
34 nxp,enable-modesel-pins:
40 nxp,vin-ilim-microamp:
44 - 85000
45 - 255000
46 - 425000
47 - 595000
48 - 765000
49 - 935000
50 - 1105000
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/Zephyr-latest/drivers/display/
Ddisplay_st7796s.c4 * SPDX-License-Identifier: Apache-2.0
33 bool inverted; /* Display color inversion */ member
49 uint8_t te_mode; /* Tearing enable mode */
50 uint32_t te_delay; /* Tearing enable delay */
57 const struct st7796s_config *config = dev->config; in st7796s_send_cmd()
59 return mipi_dbi_command_write(config->mipi_dbi, &config->dbi_config, in st7796s_send_cmd()
72 addr_data[1] = sys_cpu_to_be16(x + width - 1); in st7796s_set_cursor()
82 addr_data[1] = sys_cpu_to_be16(y + height - 1); in st7796s_set_cursor()
100 const struct st7796s_config *config = dev->config; in st7796s_get_pixelfmt()
103 * Invert the pixel format for 8-bit 8080 Parallel Interface. in st7796s_get_pixelfmt()
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/Zephyr-latest/dts/bindings/qspi/
Dnxp,s32-qspi.yaml2 # SPDX-License-Identifier: Apache-2.0
10 compatible: "nxp,s32-qspi"
12 include: [base.yaml, pinctrl-device.yaml]
20 "#address-cells":
23 "#size-cells":
26 data-rate:
29 - SDR
30 - DDR
33 - Single Data Rate (SDR): sampling of incoming data occurs on single edges.
34 - Double Data Rate (DDR): sampling of incoming data occurs on both edges.
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/Zephyr-latest/soc/mediatek/mt8xxx/
Dsoc.c2 * SPDX-License-Identifier: Apache-2.0
6 #include <zephyr/sys/libc-hooks.h>
33 * just an enable and status register needed, like its
50 * 0-5 0-5 1 (L1 is shared w/exceptions, poor choice)
51 * 6-7 7-8 1
52 * 8-10 9-11 2
53 * 11-13 16-18 3
90 struct intc64 status; /* Latched input, inverted (active == 1) */
91 struct intc64 enable; /* Interrupt enable */ member
105 volatile uint32_t *p = bit < 32 ? &g->lo : &g->hi; in set_group_bit()
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/Zephyr-latest/drivers/input/
Dinput_stmpe811.c3 * SPDX-License-Identifier: Apache-2.0
54 /* Global interrupt enable bit */
84 * - bits [1-3] X, Y only acquisition mode
89 * Analog-to-digital Converter
91 * - bit [3] selects 12 bit ADC
92 * - bits [4-6] select ADC conversion time = 80
99 * - 00 : 1.625 MHz
100 * - 01 : 3.25 MHz
101 * - 10 : 6.5 MHz
102 * - 11 : 6.5 MHz
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/Zephyr-latest/drivers/dai/intel/ssp/
Dssp.c4 * SPDX-License-Identifier: Apache-2.0
22 #define dai_set_drvdata(dai, data) (dai->priv_data = data)
23 #define dai_get_drvdata(dai) dai->priv_data
24 #define dai_get_plat_data(dai) dai->ssp_plat_data
25 #define dai_get_mn(dai) dai->ssp_plat_data->mn_inst
26 #define dai_get_ftable(dai) dai->ssp_plat_data->ftable
27 #define dai_get_fsources(dai) dai->ssp_plat_data->fsources
28 #define dai_mn_base(dai) dai->ssp_plat_data->mn_inst->base
29 #define dai_base(dai) dai->ssp_plat_data->base
30 #define dai_ip_base(dai) dai->ssp_plat_data->ip_base
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/Zephyr-latest/samples/drivers/jesd216/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
40 [JESD216_MODE_111] = "1-1-1",
41 [JESD216_MODE_112] = "1-1-2",
42 [JESD216_MODE_114] = "1-1-4",
43 [JESD216_MODE_118] = "1-1-8",
44 [JESD216_MODE_122] = "1-2-2",
45 [JESD216_MODE_144] = "1-4-4",
46 [JESD216_MODE_188] = "1-8-8",
47 [JESD216_MODE_222] = "2-2-2",
48 [JESD216_MODE_444] = "4-4-4",
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/Zephyr-latest/drivers/gpio/
Dgpio_lpc11u6x.c5 * SPDX-License-Identifier: Apache-2.0
78 * This structure is included by all the per-port private configuration.
108 const struct gpio_lpc11u6x_config *config = port->config; in gpio_lpc11u6x_pin_configure()
110 (config->shared->gpio_base + LPC11U6X_GPIO_REGS); in gpio_lpc11u6x_pin_configure()
111 uint8_t port_num = config->port_num; in gpio_lpc11u6x_pin_configure()
115 if (pin >= config->ngpios) { in gpio_lpc11u6x_pin_configure()
116 return -EINVAL; in gpio_lpc11u6x_pin_configure()
122 * and with no pull-down or pull-up resistor enabled. in gpio_lpc11u6x_pin_configure()
127 return -EINVAL; in gpio_lpc11u6x_pin_configure()
131 * For PIO0_0 and PIO0_[10-15] function 1 enables GPIO mode. For all in gpio_lpc11u6x_pin_configure()
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/Zephyr-latest/drivers/mfd/
Dmfd_tle9104.c4 * SPDX-License-Identifier: Apache-2.0
22 …* https://www.infineon.com/dgdl/Infineon-TLE9104SH-DataSheet-v01_31-EN.pdf?fileId=5546d462766cbe86…
121 *destination &= ~GENMASK(pos + length - 1, pos); in tle9104_set_register_bits()
122 *destination |= FIELD_PREP(GENMASK(pos + length - 1, pos), value); in tle9104_set_register_bits()
127 return FIELD_GET(GENMASK(pos + length - 1, pos), value); in tle9104_get_register_bits()
135 parity--; in tle9104_calculate_parity()
159 const struct tle9104_config *config = dev->config; in tle9104_transceive_frame()
160 struct tle9104_data *data = dev->data; in tle9104_transceive_frame()
191 result = spi_transceive_dt(&config->bus, &tx, &rx); in tle9104_transceive_frame()
202 return -EIO; in tle9104_transceive_frame()
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