Lines Matching +full:enable +full:- +full:inverted

4  * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/pinctrl/npcx-pinctrl.h>
28 * GPIO in pin-mux init function.
30 * def-io-conf-list {
39 .inverted = DT_PHA(DT_PROP_BY_IDX(node_id, prop, idx), alts, inv), \
58 /* Pin-control local functions */
62 uint8_t alt_mask = BIT(alt->bit); in npcx_pinctrl_alt_sel()
66 * inverted == 0: in npcx_pinctrl_alt_sel()
68 * inverted == 1: in npcx_pinctrl_alt_sel()
71 if (!!alt_func != !!alt->inverted) { in npcx_pinctrl_alt_sel()
72 NPCX_DEVALT(scfg_base, alt->group) |= alt_mask; in npcx_pinctrl_alt_sel()
74 NPCX_DEVALT(scfg_base, alt->group) &= ~alt_mask; in npcx_pinctrl_alt_sel()
78 /* Platform specific pin-control functions */
79 void npcx_lvol_set_detect_level(int lvol_ctrl, int lvol_bit, bool enable) in npcx_lvol_set_detect_level() argument
83 if (enable) { in npcx_lvol_set_detect_level()
102 inst_glue->SMB_SEL |= BIT(controller); in npcx_pinctrl_i2c_port_sel()
104 inst_glue->SMB_SEL &= ~BIT(controller); in npcx_pinctrl_i2c_port_sel()
112 inst_scfg->DEV_CTL4 |= BIT(NPCX_DEV_CTL4_WP_IF); in npcx_pinctrl_flash_write_protect_set()
113 if (!IS_BIT_SET(inst_scfg->DEV_CTL4, NPCX_DEV_CTL4_WP_IF)) { in npcx_pinctrl_flash_write_protect_set()
114 return -EIO; in npcx_pinctrl_flash_write_protect_set()
124 return IS_BIT_SET(inst_scfg->DEV_CTL4, NPCX_DEV_CTL4_WP_IF); in npcx_pinctrl_flash_write_protect_is_set()
131 SET_FIELD(inst_scfg->DEVCNT, NPCX_DEVCNT_HIF_TYP_SEL_FIELD, hif_type); in npcx_host_interface_sel()
134 void npcx_i3c_target_sel(uint8_t module_id, bool enable) in npcx_i3c_target_sel() argument
139 if (enable == true) { in npcx_i3c_target_sel()
140 inst_scfg->DEV_CTL3 |= NPCX_DEV_CTL3_I3C_MODE_BIT(module_id); in npcx_i3c_target_sel()
142 inst_scfg->DEV_CTL3 &= ~NPCX_DEV_CTL3_I3C_MODE_BIT(module_id); in npcx_i3c_target_sel()
149 void npcx_dbg_freeze_enable(bool enable) in npcx_dbg_freeze_enable() argument
153 if (enable) { in npcx_dbg_freeze_enable()
160 /* Pin-control driver registration */