4  * SPDX-License-Identifier: Apache-2.0
42 	while (regs->SYNCBUSY.reg != 0) {  in wait_synchronization()
49 	const struct pwm_sam0_config *const cfg = dev->config;  in pwm_sam0_get_cycles_per_sec()
51 	if (channel >= cfg->channels) {  in pwm_sam0_get_cycles_per_sec()
52 		return -EINVAL;  in pwm_sam0_get_cycles_per_sec()
54 	*cycles = cfg->freq;  in pwm_sam0_get_cycles_per_sec()
63 	const struct pwm_sam0_config *const cfg = dev->config;  in pwm_sam0_set_cycles()
64 	Tcc *regs = cfg->regs;  in pwm_sam0_set_cycles()
65 	uint32_t top = 1 << cfg->counter_size;  in pwm_sam0_set_cycles()
68 	bool inverted = ((regs->DRVCTRL.vec.INVEN & invert_mask) != 0);  in pwm_sam0_set_cycles()  local
70 	if (channel >= cfg->channels) {  in pwm_sam0_set_cycles()
71 		return -EINVAL;  in pwm_sam0_set_cycles()
74 		return -EINVAL;  in pwm_sam0_set_cycles()
83 	regs->CCBUF[channel].reg = TCC_CCBUF_CCBUF(pulse_cycles);  in pwm_sam0_set_cycles()
84 	regs->PERBUF.reg = TCC_PERBUF_PERBUF(period_cycles);  in pwm_sam0_set_cycles()
87 	regs->CCB[channel].reg = TCC_CCB_CCB(pulse_cycles);  in pwm_sam0_set_cycles()
88 	regs->PERB.reg = TCC_PERB_PERB(period_cycles);  in pwm_sam0_set_cycles()
91 	if (invert != inverted) {  in pwm_sam0_set_cycles()
92 		regs->CTRLA.bit.ENABLE = 0;  in pwm_sam0_set_cycles()
95 		regs->DRVCTRL.vec.INVEN ^= invert_mask;  in pwm_sam0_set_cycles()
96 		regs->CTRLA.bit.ENABLE = 1;  in pwm_sam0_set_cycles()
105 	const struct pwm_sam0_config *const cfg = dev->config;  in pwm_sam0_init()
106 	Tcc *regs = cfg->regs;  in pwm_sam0_init()
109 	/* Enable the clocks */  in pwm_sam0_init()
111 	GCLK->PCHCTRL[cfg->gclk_id].reg =  in pwm_sam0_init()
113 	*cfg->mclk |= cfg->mclk_mask;  in pwm_sam0_init()
115 	GCLK->CLKCTRL.reg = cfg->gclk_clkctrl_id | GCLK_CLKCTRL_GEN_GCLK0 |  in pwm_sam0_init()
117 	PM->APBCMASK.reg |= cfg->pm_apbcmask;  in pwm_sam0_init()
120 	retval = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);  in pwm_sam0_init()
125 	regs->CTRLA.bit.SWRST = 1;  in pwm_sam0_init()
128 	regs->CTRLA.reg = cfg->prescaler;  in pwm_sam0_init()
129 	regs->WAVE.reg = TCC_WAVE_WAVEGEN_NPWM;  in pwm_sam0_init()
130 	regs->PER.reg = TCC_PER_PER(1);  in pwm_sam0_init()
132 	regs->CTRLA.bit.ENABLE = 1;  in pwm_sam0_init()