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/Zephyr-latest/soc/espressif/common/
DKconfig.esptool2 # SPDX-License-Identifier: Apache-2.0
9 default n
14 default y
18 1. If the flash chip is an Octal one, even if one of "QIO", "QOUT", "DIO", "DOUT" options is
21 …2. If the flash chip is a Quad one, even if "OPI" is selected in `ESPTOOLPY_FLASHMODE`, our code w…
32 default ESPTOOLPY_FLASHMODE_DIO
33 default ESPTOOLPY_FLASHMODE_OPI if ESPTOOLPY_OCT_FLASH
35 Mode the flash chip is flashed in, as well as the default mode for the
48 bool "DOUT"
58 default ESPTOOLPY_FLASH_SAMPLE_MODE_DTR if ESPTOOLPY_OCT_FLASH
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/Zephyr-latest/dts/bindings/gpio/
Dxlnx,xps-gpio-1.00.a.yaml3 compatible: "xlnx,xps-gpio-1.00.a"
5 include: [gpio-controller.yaml, base.yaml]
7 bus: xlnx,xps-gpio-1.00.a
10 # https://github.com/Xilinx/device-tree-xlnx
16 xlnx,all-inputs:
21 xlnx,all-outputs:
26 xlnx,dout-default:
29 Default output value. If n-th bit is 1, GPIO-n default value is 1.
31 xlnx,gpio-width:
36 xlnx,tri-default:
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/Zephyr-latest/boards/digilent/arty_a7/dts/
Darty_a7_arm_designstart.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
9 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 zephyr,shell-uart = &uartlite0;
16 /* Use DTCM as SRAM by default */
32 compatible = "gpio-leds";
34 gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
94 gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
104 compatible = "gpio-keys";
116 gpios = <&gpio0_2 2 GPIO_ACTIVE_HIGH>;
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/Zephyr-latest/drivers/dp/
Dswdp_bitbang.c2 * Copyright (c) 2018-2019 PHYTEC Messtechnik GmbH
5 * SPDX-License-Identifier: Apache-2.0
9 * This file is based on SW_DP.c from CMSIS-DAP Source (Revision: V2.0.0)
10 * https://github.com/ARM-software/CMSIS_5/tree/develop/CMSIS/DAP/Firmware
11 * Copyright (c) 2013-2017, ARM Limited, All Rights Reserved
12 * SPDX-License-Identifier: Apache-2.0
16 /* Serial Wire Debug Port interface bit-bang driver */
30 ((CPU_CLOCK / 2U) / (port_write_cycles + delay_cycles))
33 * Default SWCLK frequency in Hz.
34 * sw_clock can be used to overwrite this default value.
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/Zephyr-latest/drivers/gpio/
Dgpio_xlnx_axi.c4 * SPDX-License-Identifier: Apache-2.0
53 uint32_t dout; member
60 /* Workaround to handle channel 2 interrupts from channel 1*/
67 const struct gpio_xlnx_axi_config *config = dev->config; in gpio_xlnx_axi_read_data()
69 return sys_read32(config->base + (config->channel * GPIO2_OFFSET) + GPIO_DATA_OFFSET); in gpio_xlnx_axi_read_data()
74 const struct gpio_xlnx_axi_config *config = dev->config; in gpio_xlnx_axi_write_data()
76 sys_write32(val, config->base + (config->channel * GPIO2_OFFSET) + GPIO_DATA_OFFSET); in gpio_xlnx_axi_write_data()
81 const struct gpio_xlnx_axi_config *config = dev->config; in gpio_xlnx_axi_write_tri()
83 sys_write32(val, config->base + (config->channel * GPIO2_OFFSET) + GPIO_TRI_OFFSET); in gpio_xlnx_axi_write_tri()
88 const struct gpio_xlnx_axi_config *config = dev->config; in gpio_xlnx_axi_pin_configure()
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Dgpio_numicro.c4 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/dt-bindings/gpio/numicro-gpio.h>
19 #define MODE_PIN_SHIFT(pin) ((pin) * 2)
23 #define PUSEL_PIN_SHIFT(pin) ((pin) * 2)
52 const struct gpio_numicro_config *cfg = dev->config; in gpio_numicro_configure()
53 GPIO_T * const regs = cfg->regs; in gpio_numicro_configure()
70 return -ENOTSUP; in gpio_numicro_configure()
103 regs->MODE = (regs->MODE & ~MODE_MASK(pin)) | in gpio_numicro_configure()
105 regs->DBEN = (regs->DBEN & ~BIT(pin)) | (debounce_enable << pin); in gpio_numicro_configure()
106 regs->SMTEN = (regs->SMTEN & ~BIT(pin)) | (schmitt_enable << pin); in gpio_numicro_configure()
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/Zephyr-latest/dts/bindings/pinctrl/
Dsilabs,dbus-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
7 node to route USART0 RX to pin PA1 and enable the pull-up resistor on the
9 for alternate function configuration, including Series 2 devices.
15 compatible = "silabs,gecko-usart";
16 pinctrl-0 = <&usart0_default>;
17 pinctrl-names = "default";
20 pinctrl-0 is a phandle that stores the pin settings for the peripheral, in
22 'pinctrl' node, typically in a board-pinctrl.dtsi file in the board
26 /* Configuration for USART0 peripheral, default state */
32 /* Configure GPIO to push-pull mode */
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/Zephyr-latest/include/zephyr/dt-bindings/mipi_dbi/
Dmipi_dbi.h4 * SPDX-License-Identifier: Apache-2.0
11 * @brief MIPI-DBI driver APIs
12 * @defgroup mipi_dbi_interface MIPI-DBI driver APIs
23 * .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-
24 * SCK -' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-'
26 * -.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.-
27 * DOUT |D/C| D7| D6| D5| D4| D3| D2| D1| D0|D/C| D7| D6| D5| D4|...|
28 * -'---'---'---'---'---'---'---'---'---'---'---'---'---'---'---'-
31 * -. .-
32 * CS '-----------------------------------------------------------'
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/Zephyr-latest/drivers/usb/udc/
Dudc_kinetis.c5 * SPDX-License-Identifier: Apache-2.0
31 #define USBFSOTG_BD_NINC BIT(2)
59 uint32_t reserved_1_0 : 2;
68 uint32_t reserved_1_0 : 2;
125 struct net_buf *out_buf[2];
126 bool busy[2];
137 const struct usbfsotg_config *config = dev->config; in usbfsotg_get_ebd()
140 bd_idx = USB_EP_GET_IDX(cfg->addr) * 4U + (cfg->stat.odd ^ opposite); in usbfsotg_get_ebd()
141 if (USB_EP_DIR_IS_IN(cfg->addr)) { in usbfsotg_get_ebd()
142 bd_idx += 2U; in usbfsotg_get_ebd()
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Dudc_rpi_pico.c5 * SPDX-License-Identifier: Apache-2.0
85 const struct rpi_pico_config *config = dev->config; in sie_status_clr()
86 usb_hw_t *base = config->base; in sie_status_clr()
88 rpi_pico_bit_clr((mm_reg_t)&base->sie_status, bit); in sie_status_clr()
93 const int idx = USB_EP_GET_IDX(ep) * 2 + USB_EP_DIR_IS_OUT(ep); in get_ep_mask()
101 const struct rpi_pico_config *config = dev->config; in get_ep_ctrl_reg()
102 usb_device_dpram_t *dpram = config->dpram; in get_ep_ctrl_reg()
109 return (uintptr_t)&dpram->ep_ctrl[USB_EP_GET_IDX(ep) - 1].out; in get_ep_ctrl_reg()
112 return (uintptr_t)&dpram->ep_ctrl[USB_EP_GET_IDX(ep) - 1].in; in get_ep_ctrl_reg()
118 const struct rpi_pico_config *config = dev->config; in get_buf_ctrl_reg()
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Dudc_ambiq.c4 * SPDX-License-Identifier: Apache-2.0
85 return -ENOMEM; in usbd_ctrl_feed_dout()
88 k_fifo_put(&cfg->fifo, buf); in usbd_ctrl_feed_dout()
90 udc_ambiq_rx(dev, cfg->addr, buf); in usbd_ctrl_feed_dout()
109 status = am_hal_usb_ep_xfer(priv->usb_handle, ep, NULL, 0); in udc_ambiq_tx()
111 status = am_hal_usb_ep_xfer(priv->usb_handle, ep, buf->data, buf->len); in udc_ambiq_tx()
117 return -EIO; in udc_ambiq_tx()
128 uint16_t rx_size = buf->size; in udc_ambiq_rx()
137 if ((ep != USB_CONTROL_EP_OUT) && (cfg->mps < rx_size)) { in udc_ambiq_rx()
138 rx_size = cfg->mps; in udc_ambiq_rx()
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Dudc_dwc2.c4 * SPDX-License-Identifier: Apache-2.0
44 /* Minimum RX FIFO size in 32-bit words considering the largest used OUT packet
49 /* Default Rx FIFO size in 32-bit words calculated to support High-Speed with:
53 * Driver adds 2 locations for each OUT endpoint to this value.
57 /* TX FIFO0 depth in 32-bit words (used by control IN endpoint)
58 * Try 2 * bMaxPacketSize0 to allow simultaneous operation with a fallback to
59 * whatever is available when 2 * bMaxPacketSize0 is not possible.
61 #define UDC_DWC2_FIFO0_DEPTH (2 * 16U)
105 /* Transfer triggers (IN on bits 0-15, OUT on bits 16-31) */
107 /* Finished transactions (IN on bits 0-15, OUT on bits 16-31) */
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/Zephyr-latest/drivers/adc/
Dadc_lmp90xxx.c4 * SPDX-License-Identifier: Apache-2.0
53 #define LMP90XXX_REG_CH_INPUTCN(ch) (0x20U + (2 * ch))
54 #define LMP90XXX_REG_CH_CONFIG(ch) (0x21U + (2 * ch))
57 #define LMP90XXX_URA(addr) ((addr >> 4U) & GENMASK(2, 0))
64 /* LMP90xxx instruction byte 2 (INST2) */
75 #define LMP90XXX_PWRCN(x) (x & BIT_MASK(2))
79 #define LMP90XXX_DRDYB_AFT_CRC(x) ((x & BIT(0)) << 2)
80 #define LMP90XXX_CH_SCAN_SEL(x) ((x & BIT_MASK(2)) << 6)
102 /* Default Output Data Rate (ODR) is 214.65 SPS */
106 #define LMP90XXX_HAS_DRDYB(config) (config->drdyb.port != NULL)
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/Zephyr-latest/drivers/usb/device/
Dusb_dc_sam_usbc.c4 * SPDX-License-Identifier: Apache-2.0
102 static struct sam_usbc_desc_table dev_desc[(NUM_OF_EP_MAX + 1) * 2];
110 "DOUT",
118 static uint32_t dev_ep_sta_dbg[2][NUM_OF_EP_MAX];
122 if (regs->UESTA[ep_idx] != dev_ep_sta_dbg[0][ep_idx]) { in usb_dc_sam_usbc_isr_sta_dbg()
123 dev_ep_sta_dbg[0][ep_idx] = regs->UESTA[ep_idx]; in usb_dc_sam_usbc_isr_sta_dbg()
128 regs->UDCON, regs->UDINT, regs->UDINTE, in usb_dc_sam_usbc_isr_sta_dbg()
129 regs->UECON[ep_idx], regs->UESTA[ep_idx], in usb_dc_sam_usbc_isr_sta_dbg()
136 regs->UDCON, regs->UDINT, regs->UDINTE, in usb_dc_sam_usbc_isr_sta_dbg()
137 regs->UECON[ep_idx], regs->UESTA[ep_idx]); in usb_dc_sam_usbc_isr_sta_dbg()
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