1 /*
2 * Copyright (c) 2018-2019 PHYTEC Messtechnik GmbH
3 * Copyright (c) 2023 Nordic Semiconductor ASA
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 /*
9 * This file is based on SW_DP.c from CMSIS-DAP Source (Revision: V2.0.0)
10 * https://github.com/ARM-software/CMSIS_5/tree/develop/CMSIS/DAP/Firmware
11 * Copyright (c) 2013-2017, ARM Limited, All Rights Reserved
12 * SPDX-License-Identifier: Apache-2.0
13 */
14
15
16 /* Serial Wire Debug Port interface bit-bang driver */
17
18 #define DT_DRV_COMPAT zephyr_swdp_gpio
19
20 #include <zephyr/kernel.h>
21 #include <zephyr/drivers/gpio.h>
22 #include <zephyr/drivers/swdp.h>
23
24 #include "swdp_ll_pin.h"
25
26 #include <zephyr/logging/log.h>
27 LOG_MODULE_REGISTER(swdp, CONFIG_DP_DRIVER_LOG_LEVEL);
28
29 #define MAX_SWJ_CLOCK(delay_cycles, port_write_cycles) \
30 ((CPU_CLOCK / 2U) / (port_write_cycles + delay_cycles))
31
32 /*
33 * Default SWCLK frequency in Hz.
34 * sw_clock can be used to overwrite this default value.
35 */
36 #define SWDP_DEFAULT_SWCLK_FREQUENCY 1000000U
37
38 #define DELAY_FAST_CYCLES 2U
39 #define DELAY_SLOW_CYCLES 3U
40
41 struct sw_config {
42 struct gpio_dt_spec clk;
43 struct gpio_dt_spec dout;
44 struct gpio_dt_spec dio;
45 struct gpio_dt_spec dnoe;
46 void *dout_reg;
47 void *dio_reg;
48 void *dnoe_reg;
49 struct gpio_dt_spec noe;
50 struct gpio_dt_spec reset;
51 uint32_t port_write_cycles;
52 void *clk_reg;
53 };
54
55 struct sw_cfg_data {
56 uint32_t clock_delay;
57 uint8_t turnaround;
58 bool data_phase;
59 bool fast_clock;
60 };
61
62 /*
63 * Move A[2:3], RnW, APnDP bits to their position,
64 * add start bit, stop bit(6), park bit and parity bit.
65 * For example, reading IDCODE would be APnDP=0, RnW=1, A2=0, A3=0.
66 * The request would be 0xa5, which is 10100101 in binary.
67 *
68 * For more information, see:
69 * - CMSIS-DAP Command Specification, DAP_Transfer
70 * - ARM Debug Interface v5 Architecture Specification
71 */
72 const static uint8_t sw_request_lut[16] = {
73 0x81, 0xa3, 0xa5, 0x87, 0xa9, 0x8b, 0x8d, 0xaf,
74 0xb1, 0x93, 0x95, 0xb7, 0x99, 0xbb, 0xbd, 0x9f
75 };
76
sw_get32bit_parity(uint32_t data)77 static ALWAYS_INLINE uint32_t sw_get32bit_parity(uint32_t data)
78 {
79 data ^= data >> 16;
80 data ^= data >> 8;
81 data ^= data >> 4;
82 data ^= data >> 2;
83 data ^= data >> 1;
84
85 return data & 1U;
86 }
87
88 /* Set SWCLK DAP hardware output pin to high level */
pin_swclk_set(const struct device * dev)89 static ALWAYS_INLINE void pin_swclk_set(const struct device *dev)
90 {
91 const struct sw_config *config = dev->config;
92
93 if (FAST_BITBANG_HW_SUPPORT) {
94 swdp_ll_pin_set(config->clk_reg, config->clk.pin);
95 } else {
96 gpio_pin_set_dt(&config->clk, 1);
97 }
98 }
99
100 /* Set SWCLK DAP hardware output pin to low level */
pin_swclk_clr(const struct device * dev)101 static ALWAYS_INLINE void pin_swclk_clr(const struct device *dev)
102 {
103 const struct sw_config *config = dev->config;
104
105 if (FAST_BITBANG_HW_SUPPORT) {
106 swdp_ll_pin_clr(config->clk_reg, config->clk.pin);
107 } else {
108 gpio_pin_set_dt(&config->clk, 0);
109 }
110 }
111
112 /* Set the SWDIO DAP hardware output pin to high level */
pin_swdio_set(const struct device * dev)113 static ALWAYS_INLINE void pin_swdio_set(const struct device *dev)
114 {
115 const struct sw_config *config = dev->config;
116
117 if (config->dout.port) {
118 if (FAST_BITBANG_HW_SUPPORT) {
119 swdp_ll_pin_set(config->dout_reg, config->dout.pin);
120 } else {
121 gpio_pin_set_dt(&config->dout, 1);
122 }
123 } else {
124 if (FAST_BITBANG_HW_SUPPORT) {
125 swdp_ll_pin_set(config->dio_reg, config->dio.pin);
126 } else {
127 gpio_pin_set_dt(&config->dio, 1);
128 }
129 }
130 }
131
132 /* Set the SWDIO DAP hardware output pin to low level */
pin_swdio_clr(const struct device * dev)133 static ALWAYS_INLINE void pin_swdio_clr(const struct device *dev)
134 {
135 const struct sw_config *config = dev->config;
136
137 if (config->dout.port) {
138 if (FAST_BITBANG_HW_SUPPORT) {
139 swdp_ll_pin_clr(config->dout_reg, config->dout.pin);
140 } else {
141 gpio_pin_set_dt(&config->dout, 0);
142 }
143 } else {
144 if (FAST_BITBANG_HW_SUPPORT) {
145 swdp_ll_pin_clr(config->dio_reg, config->dio.pin);
146 } else {
147 gpio_pin_set_dt(&config->dio, 0);
148 }
149 }
150 }
151
152 /* Set the SWDIO DAP hardware output pin to bit level */
pin_swdio_out(const struct device * dev,const uint32_t bit)153 static ALWAYS_INLINE void pin_swdio_out(const struct device *dev,
154 const uint32_t bit)
155 {
156 if (bit & 1U) {
157 pin_swdio_set(dev);
158 } else {
159 pin_swdio_clr(dev);
160 }
161 }
162
163 /* Return current level of the SWDIO DAP hardware input pin */
pin_swdio_in(const struct device * dev)164 static ALWAYS_INLINE uint32_t pin_swdio_in(const struct device *dev)
165 {
166 const struct sw_config *config = dev->config;
167
168 if (FAST_BITBANG_HW_SUPPORT) {
169 return swdp_ll_pin_get(config->dio_reg, config->dio.pin);
170 } else {
171 return gpio_pin_get_dt(&config->dio);
172 }
173 }
174
175 /*
176 * Configure the SWDIO DAP hardware to output mode.
177 * This is default configuration for every transfer.
178 */
pin_swdio_out_enable(const struct device * dev)179 static ALWAYS_INLINE void pin_swdio_out_enable(const struct device *dev)
180 {
181 const struct sw_config *config = dev->config;
182
183 if (config->dnoe.port) {
184 if (FAST_BITBANG_HW_SUPPORT) {
185 swdp_ll_pin_set(config->dnoe_reg, config->dnoe.pin);
186 } else {
187 gpio_pin_set_dt(&config->dnoe, 1);
188 }
189 } else {
190 if (FAST_BITBANG_HW_SUPPORT) {
191 swdp_ll_pin_output(config->dio_reg, config->dio.pin);
192 } else {
193 gpio_pin_configure_dt(&config->dio, GPIO_OUTPUT_ACTIVE);
194 }
195 }
196 }
197
198 /*
199 * Configure the SWDIO DAP hardware to input mode.
200 */
pin_swdio_out_disable(const struct device * dev)201 static ALWAYS_INLINE void pin_swdio_out_disable(const struct device *dev)
202 {
203 const struct sw_config *config = dev->config;
204
205 if (config->dnoe.port) {
206 if (FAST_BITBANG_HW_SUPPORT) {
207 swdp_ll_pin_clr(config->dnoe_reg, config->dnoe.pin);
208 } else {
209 gpio_pin_set_dt(&config->dnoe, 0);
210 }
211 } else {
212 if (FAST_BITBANG_HW_SUPPORT) {
213 swdp_ll_pin_input(config->dio_reg, config->dio.pin);
214 } else {
215 gpio_pin_configure_dt(&config->dio, GPIO_INPUT);
216 }
217 }
218 }
219
220 #define SW_CLOCK_CYCLE(dev, delay) \
221 do { \
222 pin_swclk_clr(dev); \
223 pin_delay_asm(delay); \
224 pin_swclk_set(dev); \
225 pin_delay_asm(delay); \
226 } while (0)
227
228 #define SW_WRITE_BIT(dev, bit, delay) \
229 do { \
230 pin_swdio_out(dev, bit); \
231 pin_swclk_clr(dev); \
232 pin_delay_asm(delay); \
233 pin_swclk_set(dev); \
234 pin_delay_asm(delay); \
235 } while (0)
236
237 #define SW_READ_BIT(dev, bit, delay) \
238 do { \
239 pin_swclk_clr(dev); \
240 pin_delay_asm(delay); \
241 bit = pin_swdio_in(dev); \
242 pin_swclk_set(dev); \
243 pin_delay_asm(delay); \
244 } while (0)
245
sw_output_sequence(const struct device * dev,uint32_t count,const uint8_t * data)246 static int sw_output_sequence(const struct device *dev, uint32_t count,
247 const uint8_t *data)
248 {
249 struct sw_cfg_data *sw_data = dev->data;
250 unsigned int key;
251 uint32_t val = 0; /* current byte */
252 uint32_t n = 0; /* bit counter */
253
254 LOG_DBG("writing %u bits", count);
255 LOG_HEXDUMP_DBG(data, count, "sequence bit data");
256 key = irq_lock();
257
258 pin_swdio_out_enable(dev);
259 while (count--) {
260 if (n == 0U) {
261 val = *data++;
262 n = 8U;
263 }
264 if (val & 1U) {
265 pin_swdio_set(dev);
266 } else {
267 pin_swdio_clr(dev);
268 }
269 SW_CLOCK_CYCLE(dev, sw_data->clock_delay);
270 val >>= 1;
271 n--;
272 }
273
274 irq_unlock(key);
275
276 return 0;
277 }
278
sw_input_sequence(const struct device * dev,uint32_t count,uint8_t * data)279 static int sw_input_sequence(const struct device *dev, uint32_t count,
280 uint8_t *data)
281 {
282 struct sw_cfg_data *sw_data = dev->data;
283 unsigned int key;
284 uint32_t val = 0U; /* current byte */
285 uint32_t n = 8U; /* bit counter */
286 uint32_t bit;
287
288 LOG_DBG("reading %u bits", count);
289 key = irq_lock();
290
291 pin_swdio_out_disable(dev);
292 while (count--) {
293 if (n == 0U) {
294 *data++ = val;
295 val = 0;
296 n = 8U;
297 }
298 SW_READ_BIT(dev, bit, sw_data->clock_delay);
299 LOG_DBG("Read bit: %d", bit);
300 val = (val << 1 | bit);
301 n--;
302 }
303
304 *data = val; /* write last byte */
305 irq_unlock(key);
306
307 return 0;
308 }
309
sw_cycle_turnaround(const struct device * dev)310 static ALWAYS_INLINE void sw_cycle_turnaround(const struct device *dev)
311 {
312 struct sw_cfg_data *sw_data = dev->data;
313 uint32_t n;
314
315 for (n = sw_data->turnaround; n; n--) {
316 SW_CLOCK_CYCLE(dev, sw_data->clock_delay);
317 }
318 }
319
sw_transfer(const struct device * dev,const uint8_t request,uint32_t * const data,const uint8_t idle_cycles,uint8_t * const response)320 static int sw_transfer(const struct device *dev,
321 const uint8_t request, uint32_t *const data,
322 const uint8_t idle_cycles, uint8_t *const response)
323 {
324 struct sw_cfg_data *sw_data = dev->data;
325 unsigned int key;
326 uint32_t ack;
327 uint32_t bit;
328 uint32_t val;
329 uint32_t parity = 0;
330 uint32_t n;
331
332 pin_swdio_out_enable(dev);
333
334 LOG_DBG("request 0x%02x idle %u", request, idle_cycles);
335 if (!(request & SWDP_REQUEST_RnW)) {
336 LOG_DBG("write data 0x%08x", *data);
337 parity = sw_get32bit_parity(*data);
338 }
339
340 key = irq_lock();
341
342 val = sw_request_lut[request & 0xFU];
343 for (n = 8U; n; n--) {
344 SW_WRITE_BIT(dev, val, sw_data->clock_delay);
345 val >>= 1;
346 }
347
348 pin_swdio_out_disable(dev);
349 sw_cycle_turnaround(dev);
350
351 /* Acknowledge response */
352 SW_READ_BIT(dev, bit, sw_data->clock_delay);
353 ack = bit << 0;
354 SW_READ_BIT(dev, bit, sw_data->clock_delay);
355 ack |= bit << 1;
356 SW_READ_BIT(dev, bit, sw_data->clock_delay);
357 ack |= bit << 2;
358
359 if (ack == SWDP_ACK_OK) {
360 /* Data transfer */
361 if (request & SWDP_REQUEST_RnW) {
362 /* Read data */
363 val = 0U;
364 for (n = 32U; n; n--) {
365 /* Read RDATA[0:31] */
366 SW_READ_BIT(dev, bit, sw_data->clock_delay);
367 val >>= 1;
368 val |= bit << 31;
369 }
370
371 /* Read parity bit */
372 SW_READ_BIT(dev, bit, sw_data->clock_delay);
373 sw_cycle_turnaround(dev);
374 pin_swdio_out_enable(dev);
375
376 if ((sw_get32bit_parity(val) ^ bit) & 1U) {
377 ack = SWDP_TRANSFER_ERROR;
378 }
379
380 if (data) {
381 *data = val;
382 }
383
384 } else {
385 sw_cycle_turnaround(dev);
386
387 pin_swdio_out_enable(dev);
388 /* Write data */
389 val = *data;
390 for (n = 32U; n; n--) {
391 SW_WRITE_BIT(dev, val, sw_data->clock_delay);
392 val >>= 1;
393 }
394
395 /* Write parity bit */
396 SW_WRITE_BIT(dev, parity, sw_data->clock_delay);
397 }
398 /* Idle cycles */
399 n = idle_cycles;
400 if (n) {
401 pin_swdio_out(dev, 0U);
402 for (; n; n--) {
403 SW_CLOCK_CYCLE(dev, sw_data->clock_delay);
404 }
405 }
406
407 pin_swdio_out(dev, 1U);
408 irq_unlock(key);
409 if (request & SWDP_REQUEST_RnW) {
410 LOG_DBG("read data 0x%08x", *data);
411 }
412
413 if (response) {
414 *response = (uint8_t)ack;
415 }
416
417 return 0;
418 }
419
420 if ((ack == SWDP_ACK_WAIT) || (ack == SWDP_ACK_FAULT)) {
421 /* WAIT OR fault response */
422 if (sw_data->data_phase) {
423 for (n = 32U + 1U + sw_data->turnaround; n; n--) {
424 /* Dummy Read RDATA[0:31] + Parity */
425 SW_CLOCK_CYCLE(dev, sw_data->clock_delay);
426 }
427 } else {
428 sw_cycle_turnaround(dev);
429 }
430
431 pin_swdio_out_enable(dev);
432 pin_swdio_out(dev, 1U);
433 irq_unlock(key);
434 LOG_DBG("Transfer wait or fault");
435 if (response) {
436 *response = (uint8_t)ack;
437 }
438
439 return 0;
440 }
441
442 /* Protocol error */
443 for (n = sw_data->turnaround + 32U + 1U; n; n--) {
444 /* Back off data phase */
445 SW_CLOCK_CYCLE(dev, sw_data->clock_delay);
446 }
447
448 pin_swdio_out_enable(dev);
449 pin_swdio_out(dev, 1U);
450 irq_unlock(key);
451 LOG_INF("Protocol error");
452 if (response) {
453 *response = (uint8_t)ack;
454 }
455
456 return 0;
457 }
458
sw_set_pins(const struct device * dev,const uint8_t pins,const uint8_t value)459 static int sw_set_pins(const struct device *dev,
460 const uint8_t pins, const uint8_t value)
461 {
462 const struct sw_config *config = dev->config;
463
464 LOG_DBG("pins 0x%02x value 0x%02x", pins, value);
465
466 if (pins & BIT(SWDP_SWCLK_PIN)) {
467 if (value & BIT(SWDP_SWCLK_PIN)) {
468 gpio_pin_set_dt(&config->clk, 1);
469 } else {
470 gpio_pin_set_dt(&config->clk, 0);
471 }
472 }
473
474 if (config->dout_reg != NULL) {
475 if (pins & BIT(SWDP_SWDIO_PIN)) {
476 if (value & BIT(SWDP_SWDIO_PIN)) {
477 gpio_pin_set_dt(&config->dout, 1);
478 } else {
479 gpio_pin_set_dt(&config->dout, 0);
480 }
481 }
482 } else {
483 if (pins & BIT(SWDP_SWDIO_PIN)) {
484 if (value & BIT(SWDP_SWDIO_PIN)) {
485 gpio_pin_set_dt(&config->dio, 1);
486 } else {
487 gpio_pin_set_dt(&config->dio, 0);
488 }
489 }
490 }
491
492 if (config->reset.port) {
493 if (pins & BIT(SWDP_nRESET_PIN)) {
494 if (value & BIT(SWDP_nRESET_PIN)) {
495 gpio_pin_set_dt(&config->reset, 1);
496 } else {
497 gpio_pin_set_dt(&config->reset, 0);
498 }
499 }
500 }
501
502 return 0;
503 }
504
sw_get_pins(const struct device * dev,uint8_t * const state)505 static int sw_get_pins(const struct device *dev, uint8_t *const state)
506 {
507 const struct sw_config *config = dev->config;
508 uint32_t val;
509
510 if (config->reset.port) {
511 val = gpio_pin_get_dt(&config->reset);
512 *state = val ? BIT(SWDP_nRESET_PIN) : 0;
513 }
514
515 val = gpio_pin_get_dt(&config->dio);
516 *state |= val ? BIT(SWDP_SWDIO_PIN) : 0;
517
518 val = gpio_pin_get_dt(&config->clk);
519 *state |= val ? BIT(SWDP_SWCLK_PIN) : 0;
520
521 LOG_DBG("pins state 0x%02x", *state);
522
523 return 0;
524 }
525
sw_set_clock(const struct device * dev,const uint32_t clock)526 static int sw_set_clock(const struct device *dev, const uint32_t clock)
527 {
528 const struct sw_config *config = dev->config;
529 struct sw_cfg_data *sw_data = dev->data;
530 uint32_t delay;
531
532 if (clock >= MAX_SWJ_CLOCK(DELAY_FAST_CYCLES, config->port_write_cycles)) {
533 sw_data->fast_clock = true;
534 delay = 1U;
535 } else {
536 sw_data->fast_clock = false;
537
538 delay = ((CPU_CLOCK / 2U) + (clock - 1U)) / clock;
539 if (delay > config->port_write_cycles) {
540 delay -= config->port_write_cycles;
541 delay = (delay + (DELAY_SLOW_CYCLES - 1U)) / DELAY_SLOW_CYCLES;
542 } else {
543 delay = 1U;
544 }
545 }
546
547 sw_data->clock_delay = delay;
548
549 LOG_WRN("cpu_clock %d, delay %d", CPU_CLOCK, sw_data->clock_delay);
550
551 return 0;
552 }
553
sw_configure(const struct device * dev,const uint8_t turnaround,const bool data_phase)554 static int sw_configure(const struct device *dev,
555 const uint8_t turnaround, const bool data_phase)
556 {
557 struct sw_cfg_data *sw_data = dev->data;
558
559 sw_data->turnaround = turnaround;
560 sw_data->data_phase = data_phase;
561
562 LOG_INF("turnaround %d, data_phase %d",
563 sw_data->turnaround, sw_data->data_phase);
564
565 return 0;
566 }
567
sw_port_on(const struct device * dev)568 static int sw_port_on(const struct device *dev)
569 {
570 const struct sw_config *config = dev->config;
571 int ret;
572
573 if (config->dnoe.port) {
574 ret = gpio_pin_configure_dt(&config->dnoe, GPIO_OUTPUT_ACTIVE);
575 if (ret) {
576 return ret;
577 }
578 }
579
580 if (config->dout.port) {
581 ret = gpio_pin_configure_dt(&config->dout, GPIO_OUTPUT_ACTIVE);
582 if (ret) {
583 return ret;
584 }
585 }
586
587 ret = gpio_pin_configure_dt(&config->dio, GPIO_INPUT);
588 if (ret) {
589 return ret;
590 }
591
592 if (config->noe.port) {
593 ret = gpio_pin_configure_dt(&config->noe, GPIO_OUTPUT_ACTIVE);
594 if (ret) {
595 return ret;
596 }
597 }
598
599 ret = gpio_pin_configure_dt(&config->clk, GPIO_OUTPUT_ACTIVE);
600 if (ret) {
601 return ret;
602 }
603
604 if (config->reset.port) {
605 ret = gpio_pin_configure_dt(&config->reset, GPIO_OUTPUT_ACTIVE);
606 if (ret) {
607 return ret;
608 }
609 }
610
611 return 0;
612 }
613
sw_port_off(const struct device * dev)614 static int sw_port_off(const struct device *dev)
615 {
616 const struct sw_config *config = dev->config;
617 int ret;
618
619 /* If there is a transceiver connected to IO, pins should always be driven. */
620 if (config->dnoe.port) {
621 ret = gpio_pin_configure_dt(&config->dnoe, GPIO_OUTPUT_INACTIVE);
622 if (ret) {
623 return ret;
624 }
625
626 if (config->dout.port) {
627 ret = gpio_pin_configure_dt(&config->dout, GPIO_OUTPUT_ACTIVE);
628 if (ret) {
629 return ret;
630 }
631 }
632
633 ret = gpio_pin_configure_dt(&config->dio, GPIO_INPUT);
634 if (ret) {
635 return ret;
636 }
637 } else {
638 if (config->dout.port) {
639 ret = gpio_pin_configure_dt(&config->dout, GPIO_DISCONNECTED);
640 if (ret) {
641 return ret;
642 }
643 }
644
645 ret = gpio_pin_configure_dt(&config->dio, GPIO_DISCONNECTED);
646 if (ret) {
647 return ret;
648 }
649 }
650
651 /* If there is a transceiver connected to CLK, pins should always be driven. */
652 if (config->noe.port) {
653 ret = gpio_pin_configure_dt(&config->noe, GPIO_OUTPUT_INACTIVE);
654 if (ret) {
655 return ret;
656 }
657
658 ret = gpio_pin_configure_dt(&config->clk, GPIO_OUTPUT_ACTIVE);
659 if (ret) {
660 return ret;
661 }
662
663 } else {
664 ret = gpio_pin_configure_dt(&config->clk, GPIO_DISCONNECTED);
665 if (ret) {
666 return ret;
667 }
668 }
669
670 if (config->reset.port) {
671 ret = gpio_pin_configure_dt(&config->reset, GPIO_DISCONNECTED);
672 if (ret) {
673 return ret;
674 }
675 }
676
677 return 0;
678 }
679
sw_gpio_init(const struct device * dev)680 static int sw_gpio_init(const struct device *dev)
681 {
682 struct sw_cfg_data *sw_data = dev->data;
683 int ret;
684
685 /* start with the port turned off */
686 ret = sw_port_off(dev);
687 if (ret) {
688 return ret;
689 }
690
691 sw_data->turnaround = 1U;
692 sw_data->data_phase = false;
693 sw_data->fast_clock = false;
694 sw_set_clock(dev, SWDP_DEFAULT_SWCLK_FREQUENCY);
695
696 return 0;
697 }
698
699 static struct swdp_api swdp_bitbang_api = {
700 .swdp_output_sequence = sw_output_sequence,
701 .swdp_input_sequence = sw_input_sequence,
702 .swdp_transfer = sw_transfer,
703 .swdp_set_pins = sw_set_pins,
704 .swdp_get_pins = sw_get_pins,
705 .swdp_set_clock = sw_set_clock,
706 .swdp_configure = sw_configure,
707 .swdp_port_on = sw_port_on,
708 .swdp_port_off = sw_port_off,
709 };
710
711 #define SW_GPIOS_GET_REG(n, gpios) \
712 COND_CODE_1(DT_INST_NODE_HAS_PROP(n, gpios), \
713 (INT_TO_POINTER(DT_REG_ADDR(DT_PHANDLE(DT_DRV_INST(n), gpios)))), \
714 (NULL))
715
716 #define SW_DEVICE_DEFINE(n) \
717 BUILD_ASSERT((DT_INST_NODE_HAS_PROP(n, dout_gpios)) == \
718 (DT_INST_NODE_HAS_PROP(n, dnoe_gpios)), \
719 "Either the dout-gpios or dnoe-gpios property is missing."); \
720 \
721 static const struct sw_config sw_cfg_##n = { \
722 .clk = GPIO_DT_SPEC_INST_GET(n, clk_gpios), \
723 .clk_reg = SW_GPIOS_GET_REG(n, clk_gpios), \
724 .dio = GPIO_DT_SPEC_INST_GET(n, dio_gpios), \
725 .dio_reg = SW_GPIOS_GET_REG(n, dio_gpios), \
726 .dout = GPIO_DT_SPEC_INST_GET_OR(n, dout_gpios, {0}), \
727 .dout_reg = SW_GPIOS_GET_REG(n, dout_gpios), \
728 .dnoe = GPIO_DT_SPEC_INST_GET_OR(n, dnoe_gpios, {0}), \
729 .dnoe_reg = SW_GPIOS_GET_REG(n, dnoe_gpios), \
730 .noe = GPIO_DT_SPEC_INST_GET_OR(n, noe_gpios, {0}), \
731 .reset = GPIO_DT_SPEC_INST_GET_OR(n, reset_gpios, {0}), \
732 .port_write_cycles = DT_INST_PROP(n, port_write_cycles), \
733 }; \
734 \
735 static struct sw_cfg_data sw_data_##n; \
736 \
737 DEVICE_DT_INST_DEFINE(n, sw_gpio_init, NULL, \
738 &sw_data_##n, &sw_cfg_##n, \
739 POST_KERNEL, CONFIG_DP_DRIVER_INIT_PRIO, \
740 &swdp_bitbang_api);
741
742 DT_INST_FOREACH_STATUS_OKAY(SW_DEVICE_DEFINE)
743
