| /Zephyr-latest/drivers/dma/ |
| D | Kconfig.dw_common | 1 # DesignWare DMA common configuration options
4 # SPDX-License-Identifier: Apache-2.0
15 The number of LLI structs in a statically allocated pool. Each channel has its own
31 Rather than immediately stopping a DMA channel the channel is suspended
33 before stopping the channel.
36 int "memory space mask"
39 Some instances of the DesignWare DMAC require a mask applied to source/destination
43 int "dw max channel count"
46 Channel count for designware DMA instances.
|
| D | dma_dw_common.h | 4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/drivers/dma.h>
17 #define MASK(b_hi, b_lo) \ macro
18 (((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL) << (b_lo))
21 (((x) & ((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL)) << (b_lo))
83 /* channel bits */
84 #define DW_CHAN_WRITE_EN_ALL MASK(2 * DW_MAX_CHAN - 1, DW_MAX_CHAN)
86 #define DW_CHAN_ALL MASK(DW_MAX_CHAN - 1, 0)
137 #define DW_CTLL_SRC_WIDTH_MASK MASK(6, 4)
139 #define DW_CTLL_DST_WIDTH_MASK MASK(3, 1)
[all …]
|
| D | dma_dw_axi.c | 4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/drivers/dma.h>
17 #define DEV_CFG(_dev) ((const struct dma_dw_axi_dev_cfg *)(_dev)->config)
18 #define DEV_DATA(_dev) ((struct dma_dw_axi_dev_data *const)(_dev)->data)
20 /* mask for block transfer size */
29 #define DMA_DW_AXI_GET_MSIZE(blen) ((blen == 1) ? (0U) : (find_msb_set(blen) - 2U))
44 /* Channel enable by setting ch_en and ch_en_we */
46 /* Channel enable by setting ch_susp and ch_susp_we */
48 /* Channel enable by setting ch_abort and ch_abort_we */
51 /* channel susp/resume write enable pos */
[all …]
|
| D | dma_smartbond.c | 4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/drivers/dma.h>
16 #include <zephyr/drivers/dma/dma_smartbond.h>
28 #define DMA_CHANNELS_COUNT DT_PROP(DT_NODELABEL(dma), dma_channels)
29 #define DMA_BLOCK_COUNT DT_PROP(DT_NODELABEL(dma), block_count)
40 #define DMA_CHN2REG(_idx) (&((struct channel_regs *)DMA)[(_idx)])
45 DMA->DMA_REQ_MUX_REG = \
46 (DMA->DMA_REQ_MUX_REG & ~(0xf << DMA_MUX_SHIFT((_idx)))) | \
50 ((DMA->DMA_REQ_MUX_REG >> DMA_MUX_SHIFT((_idx))) & 0xf)
58 * DMA channel priority level. The smaller the value the lower the priority granted to a channel
[all …]
|
| D | dma_dw_common.c | 4 * SPDX-License-Identifier: Apache-2.0
14 #include <zephyr/drivers/dma.h>
29 const struct dw_dma_dev_cfg *const dev_cfg = dev->config; in dw_dma_isr()
30 struct dw_dma_dev_data *const dev_data = dev->data; in dw_dma_isr()
37 uint32_t channel; in dw_dma_isr() local
39 status_intr = dw_read(dev_cfg->base, DW_INTR_STATUS); in dw_dma_isr()
41 LOG_ERR("%s: status_intr = %d", dev->name, status_intr); in dw_dma_isr()
45 status_block = dw_read(dev_cfg->base, DW_STATUS_BLOCK); in dw_dma_isr()
46 status_tfr = dw_read(dev_cfg->base, DW_STATUS_TFR); in dw_dma_isr()
49 status_err = dw_read(dev_cfg->base, DW_STATUS_ERR); in dw_dma_isr()
[all …]
|
| /Zephyr-latest/dts/bindings/dma/ |
| D | raspberrypi,pico-dma.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 Raspberry Pi Pico DMA
7 channel: Select channel for data transmitting
10 Use the definitions defined in `zephyr/dt-bindings/dma/rpi-pico-dma-rp2040.h`,
11 or `zephyr/dt-bindings/dma/rpi-pico-dma-rp2350.h`
13 channel-config: A 32bit mask specifying the DMA channel configuration
14 - bit 3: Enable Quiet IRQ
15 - bit 1: Enable Byte Swap
16 - bit 0: Enable High Priority
18 compatible: "raspberrypi,pico-dma"
[all …]
|
| D | st,stm32u5-dma.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 STM32 DMA controller for the stm32U5 soc family
7 It is present on stm32U5 devices as a GP DMA
9 DMA clients connected to the STM32 DMA controller must use a three-cell
10 specifier for each channel.
12 Tx using channel 0 with request 7
13 Rx using channel 1 with request 6
17 dma-names = "tx", "rx";
19 It is a phandle to the DMA controller plus the following three integer cells
20 1. channel: the stream or channel from 0 to (<dma-channels> - 1).
[all …]
|
| D | dma-controller.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 # Common fields for DMA controllers
8 bus: dma
11 "#dma-cells":
14 description: Number of items to expect in a DMA specifier
16 dma-channel-mask:
19 Bitmask of available DMA channels in ascending order that are
21 kernel. i.e. first channel corresponds to LSB.
23 dma-channels:
25 description: Number of DMA channels supported by the controller
[all …]
|
| D | andestech,atcdmac300.yaml | 4 # SPDX-License-Identifier: Apache-2.0
8 include: dma-controller.yaml
17 chain-transfer:
20 "#dma-cells":
23 dma-cells:
24 - channel
25 - slot
26 - channel-config
29 Andes DMA controller
30 channel: a phandle to the DMA controller plus the following four integer cells:
[all …]
|
| D | gd,gd32-dma.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 GD32 DMA controller
7 channel: Select channel for data transmitting
9 config: A 32bit mask specifying the DMA channel configuration
10 - bit 6-7: Direction (see dma.h)
11 - 0x0: MEMORY to MEMORY
12 - 0x1: MEMORY to PERIPH
13 - 0x2: PERIPH to MEMORY
14 - 0x3: reserved for PERIPH to PERIPH
16 - bit 9: Peripheral address increase
[all …]
|
| D | st,stm32-dma-v2bis.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 STM32 DMA controller (V2bis) for the stm32F0, stm32F1 and stm32L1 soc families
7 This DMA controller includes several channels with different requests.
8 All the requests ar ORed before entering the DMA, so that only one request
10 DMA clients connected to the STM32 DMA controller must use the format
11 described in the dma.txt file, using a 2-cell specifier for each
12 channel: a phandle to the DMA controller plus the following four integer cells:
13 1. channel: the dma stream from 1 to <dma-requests>
14 2. channel-config: A 32bit mask specifying the DMA channel configuration
15 A name custom DMA flags for channel configuration is used
[all …]
|
| D | st,stm32-dmamux.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 capable of supporting independent DMA channels.
9 DMAMUX clients connected to the STM32 DMA ultiplexer must use a two-cell specifier
10 for each dmamux channel: a phandle to the DMA multiplexer plus the following 2 integer cells:
11 1. channel: the mux channel from 0 to <dma-channels> - 1
13 3. channel-config: A 32bit mask specifying the DMA channel configuration
15 -bit 6-7 : Direction (see dma.h)
20 -bit 9 : Peripheral Increment Address
23 -bit 10 : Memory Increment Address
26 -bit 11-12 : Peripheral data size
[all …]
|
| D | st,stm32-bdma.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 The STM32 BDMA is a general-purpose direct memory access controller
9 Each channel can have up to 8 requests.
11 described in the dma.txt file, using a four-cell specifier for each
12 channel: a phandle to the BDMA controller plus the following four integer cells:
13 1. channel: the bdma stream from 0 to <bdma-requests>
15 3. channel-config: A 32bit mask specifying the BDMA channel configuration
17 -bit 6-7 : Direction (see dma.h)
22 -bit 9 : Peripheral Increment Address
25 -bit 10 : Memory Increment Address
[all …]
|
| D | st,stm32-dma-v1.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 STM32 DMA controller (V1)
8 This DMA controller includes FIFO control registers.
9 DMA clients connected to the STM32 DMA controller must use the format
10 described in the dma.txt file, using a four-cell specifier for each
11 channel: a phandle to the DMA controller plus the following four integer cells:
12 1. channel: the dma stream from 0 to <dma-requests>
13 2. slot: DMA periph request ID, which is written in the DMAREQ_ID of the DMAMUX_CxCR
14 this value is 0 for Memory-to-memory transfers
15 or a value between <1> .. <dma-generators> (not supported yet)
[all …]
|
| D | st,stm32-dma-v2.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 STM32 DMA controller (V2)
8 This DMA controller includes several channels with different requests.
9 DMA clients connected to the STM32 DMA controller must use the format
10 described in the dma.txt file, using a four-cell specifier for each
11 capable of supporting 5 or 6 or 7 or 8 independent DMA channels.
12 DMA clients connected to the STM32 DMA controller must use the format
13 described in the dma.txt file, using a 3-cell specifier for each
14 channel: a phandle to the DMA controller plus the following four integer cells:
15 1. channel: the dma stream from 1 to <dma-requests>
[all …]
|
| D | gd,gd32-dma-v1.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 GD32 DMA controller with FIFO
7 channel: Select channel for data transmitting
9 slot: Select peripheral to connect DMA
11 config: A 32bit mask specifying the DMA channel configuration
12 - bit 6-7: Direction (see dma.h)
13 - 0x0: MEMORY to MEMORY
14 - 0x1: MEMORY to PERIPH
15 - 0x2: PERIPH to MEMORY
16 - 0x3: reserved for PERIPH to PERIPH
[all …]
|
| /Zephyr-latest/drivers/serial/ |
| D | uart_mcux_flexcomm.c | 2 * Copyright (c) 2017, 2022-2023 NXP
4 * SPDX-License-Identifier: Apache-2.0
23 #include <zephyr/drivers/dma.h>
31 uint8_t channel; member
93 const struct mcux_flexcomm_config *config = dev->config; in mcux_flexcomm_poll_in()
94 uint32_t flags = USART_GetStatusFlags(config->base); in mcux_flexcomm_poll_in()
95 int ret = -1; in mcux_flexcomm_poll_in()
98 *c = USART_ReadByte(config->base); in mcux_flexcomm_poll_in()
108 const struct mcux_flexcomm_config *config = dev->config; in mcux_flexcomm_poll_out()
111 while (!(USART_GetStatusFlags(config->base) & kUSART_TxFifoEmptyFlag)) { in mcux_flexcomm_poll_out()
[all …]
|
| D | uart_mcux_lpuart.c | 2 * Copyright 2017,2021,2023-2024 NXP
5 * SPDX-License-Identifier: Apache-2.0
19 #include <zephyr/drivers/dma.h>
133 struct mcux_lpuart_data *data = dev->data; in mcux_lpuart_pm_policy_state_lock_get()
135 if (!data->pm_state_lock_on) { in mcux_lpuart_pm_policy_state_lock_get()
136 data->pm_state_lock_on = true; in mcux_lpuart_pm_policy_state_lock_get()
143 struct mcux_lpuart_data *data = dev->data; in mcux_lpuart_pm_policy_state_lock_put()
145 if (data->pm_state_lock_on) { in mcux_lpuart_pm_policy_state_lock_put()
146 data->pm_state_lock_on = false; in mcux_lpuart_pm_policy_state_lock_put()
154 const struct mcux_lpuart_config *config = dev->config; in mcux_lpuart_poll_in()
[all …]
|
| /Zephyr-latest/drivers/audio/ |
| D | dmic_mcux.c | 7 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/drivers/dma.h>
27 const struct device *dma; member
57 * - DMIC DIVHFCLK is set to 0x0 (divide by 1) in dmic_mcux_get_osr()
58 * - DMIC PHY_HALF is set to 0x0 (standard sample rate) in dmic_mcux_get_osr()
63 /* Gets hardware channel index from logical channel */
70 /* This function assigns hardware channel "n" to the left channel, in dmic_mcux_hw_chan()
71 * and hardware channel "n+1" to the right channel. This choice is in dmic_mcux_hw_chan()
74 dmic_parse_channel_map(drv_data->chan_map_lo, in dmic_mcux_hw_chan()
75 drv_data->chan_map_hi, in dmic_mcux_hw_chan()
[all …]
|
| /Zephyr-latest/drivers/spi/ |
| D | spi_pl022.c | 4 * SPDX-License-Identifier: Apache-2.0
22 #include <zephyr/drivers/dma.h>
130 * Interrupt Mask Set/Clear Register
141 /* Receive Overrun Interrupt mask */
143 /* Receive timeout Interrupt mask */
145 /* Receive FIFO Interrupt mask */
147 /* Transmit FIFO Interrupt mask */
206 * DMA Control Register
213 /* Receive DMA Enable bit */
215 /* Transmit DMA Enable bit */
[all …]
|
| D | spi_gd32.c | 4 * SPDX-License-Identifier: Apache-2.0
18 #include <zephyr/drivers/dma.h>
19 #include <zephyr/drivers/dma/dma_gd32.h>
30 /* SPI error status mask. */
45 uint32_t channel; member
65 const struct spi_gd32_dma_config dma[NUM_OF_DIRECTION]; member
75 struct spi_gd32_dma_data dma[NUM_OF_DIRECTION]; member
86 const struct spi_gd32_config *cfg = dev->config; in spi_gd32_dma_enabled()
88 if (cfg->dma[TX].dev && cfg->dma[RX].dev) { in spi_gd32_dma_enabled()
104 uint32_t stat = SPI_STAT(cfg->reg); in spi_gd32_get_err()
[all …]
|
| /Zephyr-latest/drivers/crypto/ |
| D | crypto_si32.c | 4 * SPDX-License-Identifier: Apache-2.0
7 * - As there is only one AES controller, this implementation is not using a device configuration.
10 * - If not noted otherwise, chapter numbers refer to the SiM3U1XX/SiM3C1XX reference manual
11 * (SiM3U1xx-SiM3C1xx-RM.pdf, revision 1.0)
12 * - Each DMA channel has one word of unused data (=> 3 x 4 = 12 bytes of unused RAM)
23 #include <zephyr/drivers/dma.h>
42 #define DMA_CHANNEL_ID_RX DT_INST_DMAS_CELL_BY_NAME(0, rx, channel)
43 #define DMA_CHANNEL_ID_TX DT_INST_DMAS_CELL_BY_NAME(0, tx, channel)
44 #define DMA_CHANNEL_ID_XOR DT_INST_DMAS_CELL_BY_NAME(0, xor, channel)
46 BUILD_ASSERT(DMA_CHANNEL_ID_RX < DMA_CHANNEL_COUNT, "Too few DMA channels");
[all …]
|
| /Zephyr-latest/drivers/mipi_dbi/ |
| D | mipi_dbi_nxp_lcdic.c | 4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/drivers/dma.h>
16 #include <zephyr/drivers/dma/dma_mcux_lpc.h>
92 uint32_t channel; member
153 const struct mipi_dbi_lcdic_config *config = dev->config; in mipi_dbi_lcdic_reset_state()
154 LCDIC_Type *base = config->base; in mipi_dbi_lcdic_reset_state()
156 base->CTRL &= ~LCDIC_CTRL_LCDIC_EN_MASK; in mipi_dbi_lcdic_reset_state()
158 base->CTRL |= LCDIC_CTRL_LCDIC_EN_MASK; in mipi_dbi_lcdic_reset_state()
165 /* Start DMA to send data using LCDIC TX FIFO */
168 const struct mipi_dbi_lcdic_config *config = dev->config; in mipi_dbi_lcdic_start_dma()
[all …]
|
| /Zephyr-latest/drivers/adc/ |
| D | adc_mcux_adc16.c | 2 * Copyright (c) 2017-2018, 2020, NXP
4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/drivers/dma.h>
36 uint32_t dma_slot; /* ADC DMA MUX slot */
73 #define SIM_SOPT7_ADCSET(x, shifts, mask) \ argument
74 (((uint32_t)(((uint32_t)(x)) << shifts)) & mask)
79 uint32_t channel, int status) in adc_dma_callback() argument
82 struct mcux_adc16_data *data = dev->data; in adc_dma_callback()
84 LOG_DBG("DMA done"); in adc_dma_callback()
85 data->buffer++; in adc_dma_callback()
[all …]
|
| /Zephyr-latest/dts/arm/nxp/ |
| D | nxp_s32k344_m7.dtsi | 2 * Copyright 2023-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/clock/nxp_s32k344_clock.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-m7";
25 compatible = "arm,cortex-m7";
30 compatible = "arm,armv7m-mpu";
[all …]
|
