| /Zephyr-latest/dts/bindings/timer/ |
| D | nxp,os-timer.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: NXP OS Timer on i.MX-RT5xx/6xx
6 compatible: "nxp,os-timer"
17 deep-sleep-counter:
20 Instance of a counter peripheral. The OS Timer maybe powered off in
21 certain deep power down modes. The OS Timer driver will use this
22 counter to wakeup and also to keep track of system time.
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| /Zephyr-latest/samples/boards/microchip/mec15xxevb_assy6853/power_management/src/ |
| D | power_mgmt.c | 4 * SPDX-License-Identifier: Apache-2.0
21 /* Sleep time should be lower than SUSPEND_TO_IDLE residency time */
28 /* Sleep some extra time than minimum residency */
48 /* Track entry/exit to sleep */
59 * JP99 7-8 closed
60 * JP99 10-11 closed
61 * JP75 29-30 closed
62 * JP75 32-33 closed
65 * JP25.3 (GPIO012_LT) light sleep
66 * JP25.5 (GPIO013_DP) deep sleep
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| /Zephyr-latest/tests/subsys/pm/power_mgmt_soc/src/ |
| D | power_mgmt.c | 4 * SPDX-License-Identifier: Apache-2.0
19 /* Sleep time should be lower than SUSPEND_TO_IDLE */
26 /* Sleep some extra time than minimum residency:
27 * - for light it should be very little so that we get only into light sleep
28 * and not accidentally into a deep sleep.
29 * - for deep sleep it can be very long as we want to ensure that we enter
30 * the deepest sleep state possible.
52 /* Track entry/exit to sleep */
65 latency = k_uptime_get() - trigger_time; in pm_latency_check()
70 "Sleep entry latency is too high: %d.%03d s.", in pm_latency_check()
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| /Zephyr-latest/soc/nuvoton/npcx/common/ |
| D | soc_clock.h | 4 * SPDX-License-Identifier: Apache-2.0
38 #define FPRED_VAL (DT_PROP(DT_NODELABEL(pcc), core_prescaler) - 1)
40 #define APB1DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb1_prescaler) - 1)
42 #define APB2DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb2_prescaler) - 1)
44 #define APB3DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb3_prescaler) - 1)
48 #define APB4DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb4_prescaler) - 1)
54 /* Construct a uint8_t array from 'pwdwn-ctl-val' prop for PWDWN_CTL initialization. */
67 * - OFMCLK > MAX_OFMCLK/2, XF_RANGE should be 1, else 0.
68 * - CORE_CLK > MAX_OFMCLK/2, AHB6DIV should be 1, else 0.
69 * - CORE_CLK > MAX_OFMCLK/2, FIUDIV should be 1, else 0.
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| /Zephyr-latest/drivers/timer/ |
| D | Kconfig.mec5 | 2 # SPDX-License-Identifier: Apache-2.0
14 The 32-bit 32 KHz based RTOS timer which is operational in
15 full power and deep sleep. Basic timer 5 is a 48 MHz based
16 32-bit down counter with frequency divider used for the
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| D | npcx_itim_timer.c | 4 * SPDX-License-Identifier: Apache-2.0
14 * 64/32-bit timers in Nuvoton NPCX series. Via these two kinds of timers, the
18 * - A system timer based on an ITIM64 (Internal 64-bit timer) instance, clocked
20 * - Provide a 64-bit cycles reading and ticks computation based on it.
21 * - Its prescaler is set to 1 and provide the kernel cycles reading without
23 * - After ec entered "sleep/deep sleep" power state which is used for better
26 * - A event timer based on an ITIM32 (Internal 32-bit timer) instance, clocked
28 * "sleep/deep sleep" power state.
29 * - Provide a system clock timeout notification. In its ISR, the driver informs
31 * - Its prescaler is set to 1 and the formula between event timer's cycles and
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| D | mcux_os_timer.c | 4 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/drivers/counter.h>
26 #define MAX_TICKS ((MAX_CYC - CYC_PER_TICK) / CYC_PER_TICK)
34 /* Total cycles of the timer compensated to include the time lost in "sleep/deep sleep" modes.
36 * certain deep sleep modes and the time elapsed when it is powered off.
54 uint32_t dticks = (uint32_t)((now - last_count) / CYC_PER_TICK); in mcux_lpc_ostick_isr()
57 base->OSEVENT_CTRL &= ~OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; in mcux_lpc_ostick_isr()
64 if ((int64_t)(next - now) < MIN_DELAY) { in mcux_lpc_ostick_isr()
78 * OS Timer to save off the count if needed and also start a wakeup counter
79 * that would wakeup the system from deep power down modes.
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| /Zephyr-latest/drivers/counter/ |
| D | timer_tmr_cmsdk_apb.c | 4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/drivers/counter.h>
27 /* Timer Clock control in Sleep State */
29 /* Timer Clock control in Deep Sleep State */
43 dev->config; in tmr_cmsdk_apb_start()
44 struct tmr_cmsdk_apb_dev_data *data = dev->data; in tmr_cmsdk_apb_start()
47 cfg->timer->reload = data->load; in tmr_cmsdk_apb_start()
49 cfg->timer->ctrl = TIMER_CTRL_EN; in tmr_cmsdk_apb_start()
57 dev->config; in tmr_cmsdk_apb_stop()
59 cfg->timer->ctrl = 0x0; in tmr_cmsdk_apb_stop()
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| D | timer_dtmr_cmsdk_apb.c | 4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/drivers/counter.h>
30 /* Dualtimer Clock control in Sleep State */
32 /* Dualtimer Clock control in Deep Sleep State */
44 const struct dtmr_cmsdk_apb_cfg * const cfg = dev->config; in dtmr_cmsdk_apb_start()
45 struct dtmr_cmsdk_apb_dev_data *data = dev->data; in dtmr_cmsdk_apb_start()
48 cfg->dtimer->timer1load = data->load; in dtmr_cmsdk_apb_start()
51 cfg->dtimer->timer1ctrl = (DUALTIMER_CTRL_EN | DUALTIMER_CTRL_SIZE_32); in dtmr_cmsdk_apb_start()
58 const struct dtmr_cmsdk_apb_cfg * const cfg = dev->config; in dtmr_cmsdk_apb_stop()
61 cfg->dtimer->timer1ctrl = 0x0; in dtmr_cmsdk_apb_stop()
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| /Zephyr-latest/doc/releases/ |
| D | release-notes-1.5.rst | 7 1.5.0. This is the first release to follow the 3-month release cadence.
13 - TCP Support
14 - Integration of the Paho MQTT Library support with QoS
15 - Flash Filesystem Support
16 - Integration of the mbedTLS library for encryption
17 - Improved BR/EDR support (for L2CAP, in particular).
18 - Support for the Altera Nios II/f soft CPU architecture
25 - Added nano_fifo_put_list() APIs, which allows queuing a list of elements
27 - Removed unused memory pool structure field.
28 - Enhanced memory pool code.
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| D | release-notes-2.3.rst | 18 with future support for features like 64-bit and absolute timeouts in mind
21 * Zephyr now integrates with the TF-M (Trusted Firmware M) PSA-compliant
24 * The CMSIS-DSP library is now included and integrated
33 * CVE-2020-10022: UpdateHub Module Copies a Variable-Sized Hash String
34 into a fixed-size array.
35 * CVE-2020-10059: UpdateHub Module Explicitly Disables TLS
37 * CVE-2020-10061: Improper handling of the full-buffer case in the
39 * CVE-2020-10062: Packet length decoding error in MQTT
40 * CVE-2020-10063: Remote Denial of Service in CoAP Option Parsing Due
42 * CVE-2020-10068: In the Zephyr project Bluetooth subsystem, certain
[all …]
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| D | release-notes-2.1.rst | 13 * Expanded support for ARMv6-M architecture.
50 hardware-based stack overflow detection) in ARMv6-M architecture
51 * Added QEMU support for ARMv6-M architecture
52 * Extended test coverage for ARM-specific kernel features in ARMv6-M
54 * Enhanced runtime MPU programming in ARMv8-M architecture, making
55 the full partitioning of kernel SRAM memory a user-configurable
57 * Added CMSIS support for Cortex-R architectures.
59 * Added missing Cortex-R CPU device tree bindings.
60 * Fixed incorrect Cortex-R device tree specification.
68 * RISC-V:
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| D | release-notes-2.7.rst | 17 * Support for M-Profile Vector Extensions (MVE) on ARMv8.1-M
18 * Improved thread safety for Newlib and C++ on SMP-capable systems
20 * New Action-based Power Management API
23 * Linker Support for Tightly-Coupled Memory in RISC-V
25 * Support for extended PCI / PCIe capabilities, improved MIS-X support
33 * The kernel now supports both 32- and 64-bit architectures
36 * We added support for Point-to-Point Protocol (PPP)
37 * We added support for UpdateHub, an end-to-end solution for over-the-air device updates
38 * We added support for ARM Cortex-R Architecture
40 * Expanded support for ARMv6-M architecture
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| D | release-notes-4.0.rst | 15 is now the standard way to provide device-specific protection to data at rest. (:github:`76222`)
18 :ref:`ZMS <zms_api>` is a new key-value storage subsystem compatible with all non-volatile storage
25 runtime configuration through vendor specific APIs. Initially the :dtcompatible:`nordic,nrf-comp`,
26 :dtcompatible:`nordic,nrf-lpcomp` and :dtcompatible:`nxp,kinetis-acmp` are supported.
31 Initially implemented drivers include a simple :dtcompatible:`zephyr,gpio-steppers` and a complex
32 sensor-less stall-detection capable with integrated ramp-controller :dtcompatible:`adi,tmc5041`.
50 directory for :zephyr:code-sample-category:`code samples <samples>`.
70 * :cve:`2024-8798`: Under embargo until 2024-11-22
71 * :cve:`2024-10395`: Under embargo until 2025-01-23
72 * :cve:`2024-11263` `Zephyr project bug tracker GHSA-jjf3-7x72-pqm9
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| /Zephyr-latest/drivers/clock_control/ |
| D | clock_control_mchp_xec.c | 4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
29 * Counter checks:
30 * 32KHz period counter minimum for pass/fail: 16-bit
31 * 32KHz period counter maximum for pass/fail: 16-bit
32 * 32KHz duty cycle variation max for pass/fail: 16-bit
33 * 32KHz valid count minimum: 8-bit
99 uint32_t RSVD4[(0x00c0 - 0x0094) / 4];
192 uint8_t core_clk_div; /* Cortex-M4 clock divider (CPU and NVIC) */
203 * Make sure PCR sleep enables are clear except for crypto
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| /Zephyr-latest/boards/espressif/esp32c6_devkitc/doc/ |
| D | index.rst | 6 ESP32-C6-DevKitC is an entry-level development board based on ESP32-C6-WROOM-1(U),
7 a general-purpose module with a 8 MB SPI flash. This board integrates complete Wi-Fi,
8 Bluetooth LE, Zigbee, and Thread functions. For more information, check `ESP32-C6-DevKitC`_.
13 ESP32-C6 is Espressif's first Wi-Fi 6 SoC integrating 2.4 GHz Wi-Fi 6, Bluetooth 5.3 (LE) and the
14 802.15.4 protocol. ESP32-C6 achieves an industry-leading RF performance, with reliable security
16 It consists of a high-performance (HP) 32-bit RISC-V processor, which can be clocked up to 160 MHz,
17 and a low-power (LP) 32-bit RISC-V processor, which can be clocked up to 20 MHz.
20 ESP32-C6-DevKitC is an entry-level development board based on ESP32-C6-WROOM-1(U),
21 a general-purpose module with a 8 MB SPI flash.
24 Developers can either connect peripherals with jumper wires or mount ESP32-C6-DevKitC on
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| /Zephyr-latest/subsys/bluetooth/controller/ll_sw/openisa/hal/RV32M1/radio/ |
| D | radio.c | 2 * Copyright (c) 2016 - 2019 Nordic Semiconductor ASA
4 * Copyright 2019 - 2020 NXP
6 * SPDX-License-Identifier: Apache-2.0
43 #define RADIO_AESCCM_HDR_MASK 0xE3 /* AES-CCM: NESN, SN, MD bits masked to 0 */
44 #define RADIO_PDU_LEN_MAX (BIT(8) - 1)
46 ((bytes) * 8 >> (__builtin_ffs(bits_per_usec) - 1))
52 #define RX_WTMRK 5 /* (AA + PDU header) - 1 */
85 static uint32_t dsm_ref; /* DSM reference counter */
137 uint64_t counter; member
138 uint8_t bytes[CAU3_AES_BLOCK_SIZE - 1 - 2];
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| /Zephyr-latest/boards/nxp/mimxrt595_evk/doc/ |
| D | index.rst | 7 for low-power HMI applications by combining a graphics engine and a streamlined
8 Cadence Tensilica Fusion F1 DSP core with a next-generation Arm Cortex-M33
9 core. These devices are designed to unlock the potential of display-based applications
10 with a secure, power-optimized embedded processor.
12 i.MX RT500 MCUs provides up to 5MB of on-chip SRAM and several high-bandwidth interfaces
13 to access off-chip flash, including an Octal/Quad SPI interface with an on-the-fly
20 - MIMXRT595SFFOC Cortex-M33 (275 MHz) core processor with Cadence Tensilica Fusion F1 DSP
21 - Onboard, high-speed USB, Link2 debug probe with CMSIS-DAP protocol (supporting Cortex M33 debug o…
22 - USB2.0 high-speed host and device with micro USB connector and external crystal
23 - Octal/Quad/pSRAM external memories via FlexSPI
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| /Zephyr-latest/include/zephyr/drivers/rtc/ |
| D | maxim_ds3231.h | 4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Real-time clock control based on the DS3231 counter API.
12 * DS3231](https://www.maximintegrated.com/en/products/analog/real-time-clocks/DS3231.html)
13 * is a high-precision real-time clock with temperature-compensated
16 * The core Zephyr API to this device is as a counter, with the
21 * * many other counter APIs, such as start/stop/set_top_value are not
28 * functionality exposed by this header to access the real-time-clock
37 #include <zephyr/drivers/counter.h>
210 * @brief RTC DS3231 Driver-Specific API
267 * component hours, minutes, seconds, day-of-week, and
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| /Zephyr-latest/boards/dptechnics/walter/doc/ |
| D | index.rst | 6 Walter is a compact IoT development board that combines an Espressif ESP32-S3 SoC
7 with a Sequans Monarch 2 GM02SP LTE-M/NB-IoT/GNSS modem.
14 ESP32-S3-WROOM-1-N16R2 microcontroller:
16 - Xtensa dual-core 32-bit LX7 CPU
17 - 16 MiB quad SPI flash memory
18 - 2 MiB quad SPI PSRAM
19 - 150 Mbps 802.11 b/g/n Wi-Fi 4 with on-board PCB antenna
20 - 2 Mbps Bluetooth 5 Low Energy with on-board PCB antenna
24 - Dual-mode LTE-M / NB-IoT (NB1, NB2)
25 - 3GPP LTE release 14 (Upgradable up to release 17)
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| /Zephyr-latest/drivers/serial/ |
| D | uart_npcx.c | 4 * SPDX-License-Identifier: Apache-2.0
33 /* int-mux configuration */
55 size_t counter; member
105 if (atomic_test_and_set_bit(data->pm_policy_state_flag, flag) == 0) { in uart_npcx_pm_policy_state_lock_get()
113 if (atomic_test_and_clear_bit(data->pm_policy_state_flag, flag) == 1) { in uart_npcx_pm_policy_state_lock_put()
124 * - 115200 in uart_set_npcx_baud_rate()
125 * - 3000000 in uart_set_npcx_baud_rate()
129 inst->UPSR = 0x38; in uart_set_npcx_baud_rate()
130 inst->UBAUD = 0x01; in uart_set_npcx_baud_rate()
132 inst->UPSR = 0x08; in uart_set_npcx_baud_rate()
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| /Zephyr-latest/boards/vcc-gnd/yd_esp32/doc/ |
| D | index.rst | 6 The YD-ESP32 development board is one of VCC-GND® Studio's official boards.
7 This board is based on the ESP32-WROOM-32E module, with the ESP32 as the core.
13 with integrated Wi-Fi & dual-mode Bluetooth. The ESP32 series employs a
14 Tensilica Xtensa LX6 microprocessor in both dual-core and single-core
16 Shanghai-based Chinese company, and is manufactured by TSMC using their 40nm
21 - Dual core Xtensa microprocessor (LX6), running at 160 or 240MHz
22 - 520KB of SRAM
23 - 802.11b/g/n/e/i
24 - Bluetooth v4.2 BR/EDR and BLE
25 - Various peripherals:
[all …]
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| /Zephyr-latest/boards/espressif/esp32_devkitc_wroom/doc/ |
| D | index.rst | 7 with integrated Wi-Fi & dual-mode Bluetooth. The ESP32 series employs a
8 Tensilica Xtensa LX6 microprocessor in both dual-core and single-core
10 Shanghai-based Chinese company, and is manufactured by TSMC using their 40nm
11 process. For more information, check `ESP32-DevKitC-WROOM`_.
15 - Dual core Xtensa microprocessor (LX6), running at 160 or 240MHz
16 - 520KB of SRAM
17 - 802.11b/g/n/e/i
18 - Bluetooth v4.2 BR/EDR and BLE
19 - Various peripherals:
21 - 12-bit ADC with up to 18 channels
[all …]
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| /Zephyr-latest/boards/espressif/esp32_devkitc_wrover/doc/ |
| D | index.rst | 7 with integrated Wi-Fi & dual-mode Bluetooth. The ESP32 series employs a
8 Tensilica Xtensa LX6 microprocessor in both dual-core and single-core
10 Shanghai-based Chinese company, and is manufactured by TSMC using their 40nm
11 process. For more information, check `ESP32-DevKitC-WROVER`_.
15 - Dual core Xtensa microprocessor (LX6), running at 160 or 240MHz
16 - 520KB of SRAM
17 - 802.11b/g/n/e/i
18 - Bluetooth v4.2 BR/EDR and BLE
19 - Various peripherals:
21 - 12-bit ADC with up to 18 channels
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| /Zephyr-latest/boards/m5stack/m5stack_core2/doc/ |
| D | index.rst | 6 M5Stack Core2 is an ESP32-based development board from M5Stack. It is the successor for the Core mo…
10 - ESP32-D0WDQ6-V3 chip (240MHz dual core, 600 DMIPS, 520KB SRAM, Wi-Fi)
11 - PSRAM 8MB
12 - Flash 16MB
13 - LCD IPS TFT 2", 320x240 px screen (ILI9342C)
14 - Touch screen (FT6336U)
15 - PMU AXP192
16 - Audio NS4168 amplifier (1W-092 speaker)
17 - Vibration motor
18 - RTC BM8563
[all …]
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