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/Zephyr-latest/dts/bindings/spi/
Dintel,penwell-spi.yaml3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "intel,penwell-spi"
9 include: [spi-controller.yaml, pcie-device.yaml]
15 cs-gpios:
18 pw,cs-mode:
27 pw,cs-output:
33 Chip select output possible values:
37 pw,fifo-depth:
Despressif,esp32-spi.yaml3 compatible: "espressif,esp32-spi"
5 include: [spi-controller.yaml, pinctrl-device.yaml]
11 pinctrl-0:
14 pinctrl-names:
17 half-duplex:
20 Enable half-duplex communication mode.
24 dummy-comp:
31 Enable 3-wire mode
35 dma-enabled:
39 dma-clk:
[all …]
/Zephyr-latest/samples/bluetooth/channel_sounding/
DREADME.rst1 .. zephyr:code-sample:: ble_cs
3 :relevant-api: bt_gap bluetooth
12 The CS Test sample shows how to us the CS test command to override randomization of certain channel
16 The connected CS sample shows how to set up regular channel sounding procedures on a connection
29 about 35-40 channels, assuming a single antenna path.
49 See :zephyr:code-sample-category:`bluetooth` samples for details.
57 Here is an example output from the connected CS sample:
61 .. code-block:: console
63 *** Using Zephyr OS v3.7.99-585fbd2e318c ***
68 UUID 87654321-4567-2389-1254-f67f9fedcba8
[all …]
/Zephyr-latest/samples/boards/ti/cc13x2_cc26x2/system_off/src/
Dext_flash.c5 * SPDX-License-Identifier: Apache-2.0
29 /* SPI Flash CS */ in CC1352R1_LAUNCHXL_sendExtFlashByte()
36 gpio_pin_set(dev, DIO9_PIN, (byte >> (7 - i)) & 0x01); in CC1352R1_LAUNCHXL_sendExtFlashByte()
48 gpio_pin_set(dev, DIO20_PIN, 1); /* CS */ in CC1352R1_LAUNCHXL_sendExtFlashByte()
51 * Keep CS high at least 40 us in CC1352R1_LAUNCHXL_sendExtFlashByte()
87 printk("%s: device not ready.\n", dev->name); in CC1352R1_LAUNCHXL_shutDownExtFlash()
91 /* Set SPI Flash CS pin as output */ in CC1352R1_LAUNCHXL_shutDownExtFlash()
93 /* Set SPI Flash CLK pin as output */ in CC1352R1_LAUNCHXL_shutDownExtFlash()
95 /* Set SPI Flash MOSI pin as output */ in CC1352R1_LAUNCHXL_shutDownExtFlash()
/Zephyr-latest/tests/drivers/spi/spi_loopback/boards/
Dintel_rpl_p_crb.overlay4 * SPDX-License-Identifier: Apache-2.0
10 pw,cs-mode = <0>;
11 pw,cs-output = <0>;
15 compatible = "test-spi-loopback-slow";
17 spi-max-frequency = <500000>;
21 compatible = "test-spi-loopback-fast";
23 spi-max-frequency = <16000000>;
Dintel_rpl_s_crb.overlay4 * SPDX-License-Identifier: Apache-2.0
10 pw,cs-mode = <0>;
11 pw,cs-output = <0>;
15 compatible = "test-spi-loopback-slow";
17 spi-max-frequency = <500000>;
20 compatible = "test-spi-loopback-fast";
22 spi-max-frequency = <16000000>;
/Zephyr-latest/boards/lilygo/ttgo_t7v1_5/
Dttgo_t7v1_5-pinctrl.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
8 #include <dt-bindings/pinctrl/esp32-pinctrl.h>
9 #include <zephyr/dt-bindings/pinctrl/esp32-gpio-sigmap.h>
15 output-high;
19 bias-pull-up;
28 /* GPIO5 is CS */
31 output-low;
39 bias-pull-up;
40 drive-open-drain;
[all …]
/Zephyr-latest/boards/lilygo/ttgo_t8c3/
Dttgo_t8c3-pinctrl.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
8 #include <dt-bindings/pinctrl/esp32c3-pinctrl.h>
9 #include <zephyr/dt-bindings/pinctrl/esp32c3-gpio-sigmap.h>
15 output-high;
19 bias-pull-up;
28 /* GPIO6 is CS */
31 output-low;
39 bias-pull-up;
40 drive-open-drain;
[all …]
/Zephyr-latest/dts/bindings/gpio/
Dmikro-bus.yaml2 # SPDX-License-Identifier: Apache-2.0
12 … https://download.mikroe.com/documents/standards/mikrobus/mikrobus-standard-specification-v200.pdf
15 numbered 0 - 5 (AN - MOSI), the right side pins are numbered 6 - 10
16 (PWM - SDA). The bottom 2 pins on each side are used for input voltage
19 Analog - AN PWM - PWM output
20 Reset - RST INT - Hardware Interrupt
21 SPI Chip Select - CS RX - UART Receive
22 SPI Clock - SCK TX - UART Transmit
23 SPI Master Input Slave Output - MISO SCL - I2C Clock
24 SPI Master Output Slave Input - MOSI SDA - I2C Data
[all …]
Dadi,max14916-gpio.yaml3 # SPDX-License-Identifier: Apache-2.0
5 description: ADI MAX14916 is octal industrial output with advanced diagnostics
7 compatible: "adi,max14916-gpio"
10 "#gpio-cells":
17 drdy-gpios:
19 High-Side Open-Drain Output. READY is passive low when the internal
22 type: phandle-array
23 fault-gpios:
27 type: phandle-array
28 sync-gpios:
[all …]
/Zephyr-latest/arch/x86/core/ia32/
Dcoredump.c4 * SPDX-License-Identifier: Apache-2.0
28 uint32_t cs; member
54 arch_blk.code = esf->errorCode; in arch_coredump_info_dump()
63 arch_blk.r.eax = esf->eax; in arch_coredump_info_dump()
64 arch_blk.r.ebx = esf->ebx; in arch_coredump_info_dump()
65 arch_blk.r.ecx = esf->ecx; in arch_coredump_info_dump()
66 arch_blk.r.edx = esf->edx; in arch_coredump_info_dump()
67 arch_blk.r.esp = esf->esp; in arch_coredump_info_dump()
68 arch_blk.r.ebp = esf->ebp; in arch_coredump_info_dump()
69 arch_blk.r.esi = esf->esi; in arch_coredump_info_dump()
[all …]
/Zephyr-latest/samples/drivers/spi_bitbang/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
20 * writes 5 9bit words, you can check the output with a logic analyzer
23 struct spi_cs_control *cs) in test_basic_write_9bit_words() argument
30 config.cs = *cs; in test_basic_write_9bit_words()
50 struct spi_cs_control *cs) in test_9bit_loopback_partial() argument
57 config.cs = *cs; in test_9bit_loopback_partial()
67 {.buf = buff + (2), .len = (datacount - 2)*stride}, in test_9bit_loopback_partial()
71 {.buf = rxdata, .len = (datacount - 2) * stride}, in test_9bit_loopback_partial()
89 void test_8bit_xfer(const struct device *dev, struct spi_cs_control *cs) in test_8bit_xfer() argument
96 config.cs = *cs; in test_8bit_xfer()
[all …]
/Zephyr-latest/boards/shields/semtech_sx1272mb2das/
Dsemtech_sx1272mb2das.overlay4 * SPDX-License-Identifier: Apache-2.0
16 cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */
21 spi-max-frequency = <3000000>;
23 reset-gpios = <&arduino_header 0 GPIO_ACTIVE_HIGH>; /* A0 */
25 dio-gpios = <&arduino_header 8 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* DIO0 is D2 */
30 power-amplifier-output = "rfo";
/Zephyr-latest/dts/x86/intel/
Dalder_lake.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/pcie/pcie.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "intel,alder-lake", "intel,x86_64";
22 d-cache-line-size = <64>;
28 compatible = "intel,alder-lake";
[all …]
Draptor_lake_p.dtsi3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
8 #include <zephyr/dt-bindings/pcie/pcie.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "intel,raptor-lake", "intel,x86_64";
20 d-cache-line-size = <64>;
33 interrupt-controller;
[all …]
Draptor_lake_s.dtsi3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
8 #include <zephyr/dt-bindings/i2c/i2c.h>
9 #include <zephyr/dt-bindings/pcie/pcie.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "intel,raptor-lake", "intel,x86_64";
20 d-cache-line-size = <64>;
33 #address-cells = <1>;
[all …]
/Zephyr-latest/dts/bindings/can/
Dmicrochip,mcp251xfd.yaml2 # SPDX-License-Identifier: Apache-2.0
11 cs-gpios = <&mikrobus_header 2 GPIO_ACTIVE_LOW>;
17 spi-max-frequency = <18000000>;
18 int-gpios = <&mikrobus_header 7 GPIO_ACTIVE_LOW>;
20 osc-freq = <40000000>;
27 include: [spi-device.yaml, can-fd-controller.yaml]
30 osc-freq:
35 int-gpios:
36 type: phandle-array
39 The interrupt signal from the controller is active low in push-pull mode.
[all …]
/Zephyr-latest/subsys/mgmt/ec_host_cmd/backends/
Dec_host_cmd_backend_shi_npcx.c4 * SPDX-License-Identifier: Apache-2.0
32 #define HAL_INSTANCE(dev) (struct shi_reg *)(((const struct shi_npcx_config *)(dev)->config)->base)
34 /* Full output buffer size */
40 /* Half output buffer size */
48 * This affects the slowest SPI clock we can support. A delay of 8192 us permits a 512-byte request
62 * Space allocation of the past-end status byte (EC_SHI_PAST_END) in the out_msg buffer.
72 * Offset of output parameters needs to account for pad and framing bytes and
73 * one last past-end byte at the end so any additional bytes clocked out by
79 * Our input and output msg buffers. These must be large enough for our largest
81 * overhead, as passed to the host command handler, must be 32-bit aligned.
[all …]
/Zephyr-latest/arch/x86/core/intel64/
Dcoredump.c4 * SPDX-License-Identifier: Apache-2.0
30 uint64_t cs; member
65 arch_blk.vector = esf->vector; in arch_coredump_info_dump()
66 arch_blk.code = esf->code; in arch_coredump_info_dump()
75 arch_blk.r.rax = esf->rax; in arch_coredump_info_dump()
76 arch_blk.r.rcx = esf->rcx; in arch_coredump_info_dump()
77 arch_blk.r.rdx = esf->rdx; in arch_coredump_info_dump()
78 arch_blk.r.rsi = esf->rsi; in arch_coredump_info_dump()
79 arch_blk.r.rdi = esf->rdi; in arch_coredump_info_dump()
80 arch_blk.r.rsp = esf->rsp; in arch_coredump_info_dump()
[all …]
/Zephyr-latest/tests/drivers/build_all/lora/
Dsx1272.overlay3 * SPDX-License-Identifier: Apache-2.0
8 #address-cells = <1>;
9 #size-cells = <1>;
13 gpio-controller;
15 #gpio-cells = <0x2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
26 cs-gpios = <&test_gpio 0 0>,
34 spi-max-frequency = <3000000>;
36 reset-gpios = <&test_gpio 0 0>;
[all …]
/Zephyr-latest/dts/bindings/qspi/
Dnxp,s32-qspi.yaml2 # SPDX-License-Identifier: Apache-2.0
10 compatible: "nxp,s32-qspi"
12 include: [base.yaml, pinctrl-device.yaml]
20 "#address-cells":
23 "#size-cells":
26 data-rate:
29 - SDR
30 - DDR
33 - Single Data Rate (SDR): sampling of incoming data occurs on single edges.
34 - Double Data Rate (DDR): sampling of incoming data occurs on both edges.
[all …]
/Zephyr-latest/dts/arm/acsip/
Ds76s.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 #include <st/l0/stm32l073r(b-z)tx-pinctrl.dtsi>
13 pinctrl-0 = <&spi2_sck_pb13 &spi2_miso_pb14 &spi2_mosi_pb15>;
14 pinctrl-names = "default";
15 cs-gpios = <&gpiob 12 GPIO_ACTIVE_LOW>;
22 reset-gpios = <&gpiob 10 GPIO_ACTIVE_LOW>;
23 dio-gpios =
36 spi-max-frequency = <1000000>;
37 power-amplifier-output = "pa-boost";
/Zephyr-latest/boards/st/st25dv_mb1283_disco/doc/
Dindex.rst11 The ST25DV-DISCOVERY is a demonstration kit to evaluate the features and capabilities
24 - Main board: ST25DV_Discovery_Mboard:
26 - STM32F405VGT6 LQFP100 32-bit microcontroller, with 1 Mbyte Flash memory, 192 + 4 Kbytes SRAM.
27 - LCD color screen (320 x 200 pixels)
28 - Touch screen driver
29 - Different color LEDs (power, user, ST link)
30 - User push button
31 - Joystick for menu selection
32 - Reset button
33 - On board ST link for microcontroller firmware upgrade and debug
[all …]
/Zephyr-latest/include/zephyr/bluetooth/
Dcs.h8 * SPDX-License-Identifier: Apache-2.0
14 * @brief LE Channel Sounding (CS)
15 * @defgroup bt_le_cs Channel Sounding (CS)
31 * @brief Macro for getting a specific channel bit in CS channel map
41 * @brief Macro for setting a specific channel bit value in CS channel map
65 /** Default CS settings in the local Controller */
67 /** Enable CS initiator role. */
69 /** Enable CS reflector role. */
74 /** Maximum output power (Effective Isotropic Radiated Power) to be used
75 * for all CS transmissions.
[all …]
/Zephyr-latest/boards/arm/v2m_beetle/
Dpinmux.c4 * SPDX-License-Identifier: Apache-2.0
18 * are responsible for pin muxing, input/output, pull-up, etc.
25 * Pins 0 - 15 are for GPIO0
26 * Pins 16 - 31 are for GPIO1
108 CMSDK_AHB_GPIO0_DEV->altfuncset = gpio_0; in arm_v2m_beetle_pinmux_defaults()
119 gpio_1 |= (1<<8); /* QSPI CS 2 */ in arm_v2m_beetle_pinmux_defaults()
120 gpio_1 |= (1<<9); /* QSPI CS 1 */ in arm_v2m_beetle_pinmux_defaults()
127 CMSDK_AHB_GPIO1_DEV->altfuncset = gpio_1; in arm_v2m_beetle_pinmux_defaults()
129 /* Set the ARD_PWR_EN GPIO1[15] as an output */ in arm_v2m_beetle_pinmux_defaults()
130 CMSDK_AHB_GPIO1_DEV->outenableset |= (0x1 << 15); in arm_v2m_beetle_pinmux_defaults()
[all …]

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