Home
last modified time | relevance | path

Searched +full:cpu1 +full:- +full:prescaler (Results 1 – 15 of 15) sorted by relevance

/Zephyr-latest/dts/bindings/clock/
Dst,stm32wb-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 For more description confere st,stm32-rcc.yaml
8 compatible: "st,stm32wb-rcc"
11 - name: st,stm32-rcc.yaml
12 property-blocklist:
13 - ahb-prescaler
16 cpu1-prescaler:
20 - 1
21 - 2
22 - 3
[all …]
Dst,stm32h7-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
14 "clock-frequency" property.
16 prescaler properties.
20 clock-frequency = <DT_FREQ_M(480)>; /* SYSCLK runs at 480MHz */
29 Confere st,stm32-rcc binding for information about domain clocks configuration.
31 compatible: "st,stm32h7-rcc"
33 include: [clock-controller.yaml, base.yaml]
39 "#clock-cells":
42 clock-frequency:
52 - 1
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/
Dwb_i2c1_sysclk_lptim1_lsi.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
21 /delete-property/ hsi-div;
26 /delete-property/ msi-range;
30 /delete-property/ div-m;
31 /delete-property/ mul-n;
32 /delete-property/ div-p;
[all …]
Dwl_i2c1_sysclk_lptim1_lsi.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
21 /delete-property/ hsi-div;
26 /delete-property/ msi-range;
30 /delete-property/ div-m;
31 /delete-property/ mul-n;
32 /delete-property/ div-p;
[all …]
Dwb_i2c1_hsi_lptim1_lse.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
21 /delete-property/ hsi-div;
26 /delete-property/ msi-range;
30 /delete-property/ div-m;
31 /delete-property/ mul-n;
32 /delete-property/ div-p;
[all …]
Dwl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
21 /delete-property/ hsi-div;
26 /delete-property/ msi-range;
30 /delete-property/ div-m;
31 /delete-property/ mul-n;
32 /delete-property/ div-p;
[all …]
/Zephyr-latest/boards/st/stm32wb5mmg/
Dstm32wb5mmg.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/wb/stm32wb55vgyx-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
18 zephyr,shell-uart = &usart1;
19 zephyr,bt-mon-uart = &lpuart1;
20 zephyr,bt-c2h-uart = &lpuart1;
23 zephyr,code-partition = &slot0_partition;
47 clock-frequency = <DT_FREQ_M(32)>;
48 cpu1-prescaler = <1>;
[all …]
/Zephyr-latest/boards/seeed/lora_e5_mini/
Dlora_e5_mini.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
8 #include <seeed_studio/lora-e5.dtsi>
9 #include <zephyr/dt-bindings/input/input-event-codes.h>
12 model = "Seeed Studio LoRa-E5 mini";
13 compatible = "seeed,lora-e5-mini";
17 zephyr,shell-uart = &usart1;
20 zephyr,code-partition = &slot0_partition;
24 compatible = "gpio-leds";
32 compatible = "gpio-keys";
[all …]
/Zephyr-latest/boards/olimex/lora_stm32wl_devkit/
Dolimex_lora_stm32wl_devkit.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
8 #include <olimex/bb-stm32wl.dtsi>
9 #include <zephyr/dt-bindings/input/input-event-codes.h>
13 compatible = "olimex,lora-stm32wl-devkit";
17 zephyr,shell-uart = &usart1;
20 zephyr,code-partition = &slot0_partition;
24 compatible = "gpio-leds";
32 compatible = "gpio-keys";
59 div-m = <1>;
[all …]
/Zephyr-latest/boards/st/stm32wb5mm_dk/
Dstm32wb5mm_dk.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/wb/stm32wb55vgyx-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
11 #include <zephyr/dt-bindings/led/led.h>
12 #include <zephyr/dt-bindings/sensor/ism330dhcx.h>
16 compatible = "st,stm32wb5mm-dk";
20 zephyr,shell-uart = &usart1;
21 zephyr,bt-mon-uart = &lpuart1;
22 zephyr,bt-c2h-uart = &lpuart1;
[all …]
/Zephyr-latest/boards/st/nucleo_wl55jc/
Dnucleo_wl55jc.dts2 * Copyright (c) 2020-2024 STMicroelectronics
4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/wl/stm32wl55jcix-pinctrl.dtsi>
12 #include <zephyr/dt-bindings/input/input-event-codes.h>
15 model = "STMicroelectronics STM32WL55JC-NUCLEO board";
16 compatible = "st,stm32wl55-nucleo";
20 zephyr,shell-uart = &lpuart1;
23 zephyr,code-partition = &slot0_partition;
27 compatible = "gpio-leds";
[all …]
/Zephyr-latest/boards/st/nucleo_wb55rg/
Dnucleo_wb55rg.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/wb/stm32wb55rgvx-pinctrl.dtsi>
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 model = "STMicroelectronics STM32WB55RG-NUCLEO board";
15 compatible = "st,stm32wb55rg-nucleo";
19 zephyr,shell-uart = &usart1;
20 zephyr,bt-mon-uart = &lpuart1;
21 zephyr,bt-c2h-uart = &lpuart1;
24 zephyr,code-partition = &slot0_partition;
[all …]
/Zephyr-latest/boards/seeed/lora_e5_dev_board/
Dlora_e5_dev_board.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
8 #include <seeed_studio/lora-e5.dtsi>
9 #include <zephyr/dt-bindings/input/input-event-codes.h>
12 model = "Seeed Studio LoRa-E5 Dev Board";
13 compatible = "seeed,lora-e5-dev-board";
17 zephyr,shell-uart = &usart1;
20 zephyr,code-partition = &slot0_partition;
24 compatible = "gpio-leds";
33 compatible = "gpio-keys";
[all …]
/Zephyr-latest/dts/arm/nxp/
Dnxp_rt11xx.dtsi2 * Copyright 2021,2023-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/power/imx_spc.h>
15 #include <zephyr/dt-bindings/mipi_dsi/mipi_dsi.h>
[all …]
/Zephyr-latest/dts/riscv/andes/
Dandes_v5_ae350.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
8 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
19 compatible = "andestech,andescore-v5", "riscv";
24 mmu-type = "riscv,sv32";
25 clock-frequency = <60000000>;
[all …]