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/Zephyr-latest/drivers/clock_control/
DKconfig1 # Clock controller driver configuration options
4 # SPDX-License-Identifier: Apache-2.0
7 # Clock controller drivers
10 bool "Clock controller drivers"
12 Enable support for hardware clock controller. Such hardware can
13 provide clock for other subsystem, and thus can be also used for
14 power efficiency by controlling their clock. Note that this has
20 int "Clock control init priority"
23 Clock control driver device initialization priority.
26 module-str = clock control
[all …]
DKconfig.lpc11u6x1 # LPC11U6X MCU clock control driver config
4 # SPDX-License-Identifier: Apache-2.0
7 bool "LPC11U6X Reset and clock control"
12 Enable driver for reset and clock control used in
28 prompt "LPC11U6X PLL Clock source"
33 Use the internal oscillator as the clock source for the PLL
38 Use the system oscillator as the clock source for the PLL
Dclock_control_lpc11u6x.h4 * SPDX-License-Identifier: Apache-2.0
70 volatile uint32_t sys_pll_clk_sel; /* System PLL clock source */
71 volatile uint32_t sys_pll_clk_uen; /* System PLL source update */
72 volatile uint32_t usb_pll_clk_sel; /* USB PLL clock source */
73 volatile uint32_t usb_pll_clk_uen; /* USB PLL clock source
77 volatile uint32_t main_clk_sel; /* Main clock select */
78 volatile uint32_t main_clk_uen; /* Main clock update */
79 volatile uint32_t sys_ahb_clk_div; /* System clock divider */
81 volatile uint32_t sys_ahb_clk_ctrl; /* System clock control */
83 volatile uint32_t ssp0_clk_div; /* SSP0 clock divider */
[all …]
/Zephyr-latest/drivers/timer/
DKconfig.nrf_xrtc4 # SPDX-License-Identifier: Apache-2.0
8 prompt "Clock startup policy"
14 System clock source is initiated but does not wait for clock readiness.
15 When this option is picked, system clock may not be ready when code relying
22 System clock source initialization waits until clock is available. In some
23 systems, clock initially runs from less accurate source which has faster
24 startup time and then seamlessly switches to the target clock source when
25 it is ready. When this option is picked, system clock is available after
26 system clock driver initialization but it may be less accurate. Option is
27 equivalent to waiting for stability if clock source does not have
[all …]
DKconfig3 # Copyright (c) 2014-2015 Wind River Systems, Inc.
6 # SPDX-License-Identifier: Apache-2.0
16 available to provide values from a 64-bit cycle counter.
25 bool "Timer allowed to skew uptime clock during idle"
34 int "System clock driver initialization priority"
38 value for the system clock driver. As driver initialization might need
39 the clock to be running already, you should let the default value as it
66 source "drivers/timer/Kconfig.altera_avalon"
67 source "drivers/timer/Kconfig.ambiq"
68 source "drivers/timer/Kconfig.x86"
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/Zephyr-latest/dts/bindings/clock/
Dst,stm32-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Reset and Clock controller node.
6 This node is in charge of system clock ('SYSCLK') source selection and controlling
9 Configuring STM32 Reset and Clock controller node:
11 System clock source should be selected amongst the clock nodes available in "clocks"
13 Core clock frequency should also be defined, using "clock-frequency" property.
15 Core clock frequency = SYSCLK / AHB prescaler
20 clocks = <&pll>; /* Select 80MHz pll as SYSCLK source */
21 ahb-prescaler = <2>;
22 clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
[all …]
Dst,stm32wba-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Reset and Clock controller node.
6 This node is in charge of system clock ('SYSCLK') source selection and controlling
9 Configuring STM32 Reset and Clock controller node:
11 System clock source should be selected amongst the clock nodes available in "clocks"
13 Core clock frequency should also be defined, using "clock-frequency" property.
15 Core clock frequency = SYSCLK / AHB prescaler
20 clocks = <&pll>; /* Select pll as SYSCLK source */
21 ahb-prescaler = <2>;
22 clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
[all …]
Dnordic,nrf-lfclk.yaml2 # SPDX-License-Identifier: Apache-2.0
5 nRF LFCLK (Low Frequency CLocK)
7 The LFCLK can use the following clocks as clock sources:
9 - HFXO: The HFXO clock is used as a clock source if the
10 LFCLK SYNTH mode is selected and the LFXO clock is not
11 available. The HFXO clock is used indirectly through
12 the FLL16M clock in BYPASS mode.
14 - LFXO: The LFXO clock is used as a clock source if the
15 LFCLK SYNTH mode is selected and the LFXO clock is
16 available. The LFXO clock is used indirectly through
[all …]
Dst,stm32wb0-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32WB0 Reset and Clock controller node for STM32WB0 devices
6 This node is in charge of the system clock ('SYSCLK') source
9 compatible: "st,stm32wb0-rcc"
11 include: [clock-controller.yaml, base.yaml]
17 "#clock-cells":
20 clock-frequency:
24 default frequency in Hz for clock output
26 slow-clock:
29 Slow clock source selection.
[all …]
Dnordic,nrf-fll16m.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The FLL16M can use the following clocks as clock sources:
9 - HFXO: The HFXO clock is used as a clock source if the
11 closed-loop and the LFXO clock is not available.
13 - LFXO: The LFXO clock is used as a clock source if the
14 FLL16M mode is closed-loop and the LFXO clock is
20 open-loop-accuracy-ppm = <20000>;
21 closed-loop-base-accuracy-ppm = <5000>;
23 clock-names = "hfxo", "lfxo";
26 compatible: "nordic,nrf-fll16m"
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Dmicrochip,xec-pcr.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Microchip XEC Power Clock Reset and VBAT register (PCR)
6 compatible: "microchip,xec-pcr"
8 include: [clock-controller.yaml, pinctrl-device.yaml, base.yaml]
14 core-clock-div:
17 description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock
19 slow-clock-div:
22 PWM and TACH clock domain divided down from 48 MHz AHB clock. The
25 pll-32k-src:
28 description: 32 KHz clock source for PLL
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/Zephyr-latest/dts/bindings/usb/uac2/
Dzephyr,uac2-clock-source.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: USB Audio Class 2 Clock Source entity
6 compatible: "zephyr,uac2-clock-source"
9 clock-type:
13 Clock Type indicating whether the Clock Source represents an external
14 clock or an internal clock with either fixed frequency, variable
17 - "external"
18 - "internal-fixed"
19 - "internal-variable"
20 - "internal-programmable"
[all …]
/Zephyr-latest/dts/bindings/pwm/
Dtelink,b91-pwm.yaml2 # SPDX-License-Identifier: Apache-2.0
7 include: [pwm-controller.yaml, pinctrl-device.yaml, base.yaml]
9 compatible: "telink,b91-pwm"
13 pinctrl-0:
16 clock-frequency:
19 description: Default PWM Peripheral Clock frequency in Hz (is used if 32K Clock is disabled)
21 clk32k-ch0-enable:
23 description: Enable 32K Source Clock for PWM Channel 0
25 clk32k-ch1-enable:
27 description: Enable 32K Source Clock for PWM Channel 1
[all …]
Dmicrochip,xec-pwmbbled.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: [pwm-controller.yaml, base.yaml, pinctrl-device.yaml]
8 compatible: "microchip,xec-pwmbbled"
27 clock-select:
31 Clock source selection: 32 KHz is available in deep sleep.
32 - PWM_BBLED_CLK_AHB: Clock source is the PLL based AHB clock
33 - PWM_BBLED_CLK_32K: Clock source is the 32KHz domain
35 - "PWM_BBLED_CLK_32K"
36 - "PWM_BBLED_CLK_48M"
38 pinctrl-0:
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/Zephyr-latest/soc/nxp/imxrt/imxrt5xx/
DKconfig3 # SPDX-License-Identifier: Apache-2.0
38 …ENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")
59 prompt "Clock source for Flexcomm0"
63 bool "FRG is source of Flexcomm0 clock"
66 bool "FRO_DIV4 is source of Flexcomm0 clock"
71 prompt "Clock source for MIPI DPHY"
75 bool "AUX1_PLL is source of MIPI_DPHY clock"
78 bool "FRO 192/96M is source of MIPI_DPHY clock"
/Zephyr-latest/tests/subsys/usb/uac2/
Dapp.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <dt-bindings/usb/audio.h>
13 full-speed;
14 high-speed;
15 audio-function = <AUDIO_FUNCTION_HEADSET>;
18 compatible = "zephyr,uac2-clock-source";
19 clock-type = "internal-programmable";
20 frequency-control = "host-programmable";
21 sampling-frequencies = <48000>;
25 compatible = "zephyr,uac2-input-terminal";
[all …]
/Zephyr-latest/dts/bindings/timer/
Dambiq,stimer.yaml2 # SPDX-License-Identifier: Apache-2.0
17 clk-source:
21 clk-source specifies the clock source that used by the system timer.
23 0 - NOCLK : No clock enabled.
24 1 - HFRC_DIV16 : 3MHz from the HFRC clock divider.
25 2 - HFRC_DIV256 : 187.5KHz from the HFRC clock divider.
26 3 - XTAL_DIV1 : 32768Hz from the crystal oscillator.
27 4 - XTAL_DIV2 : 16384Hz from the crystal oscillator.
28 5 - XTAL_DIV32 : 1024Hz from the crystal oscillator.
29 6 - LFRC_DIV1 : Approximately 1KHz from the LFRC oscillator (uncalibrated).
[all …]
/Zephyr-latest/soc/atmel/sam0/common/
DKconfig.samd2x1 # SPDX-License-Identifier: Apache-2.0
16 This can then be selected as the main clock reference for the SOC.
22 This can then be selected as the main clock reference for the SOC.
25 bool "External 32.768 kHz clock source"
27 Enable the external 32.768 kHz clock source at startup.
28 This can then be selected as the main clock reference for the SOC.
31 bool "External 32.768 kHz clock is a crystal oscillator"
35 Enable the crystal oscillator (if disabled, expect a clock signal on
39 bool "External 0.4..32 MHz clock source"
41 Enable the external 0.4..32 MHz clock source at startup.
[all …]
/Zephyr-latest/drivers/rtc/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
5 bool "Real-Time Clock (RTC) drivers"
12 module-str = rtc
13 source "subsys/logging/Kconfig.template.log_config"
33 bool "RTC driver clock calibration support"
35 This is an option which enables driver support for RTC clock
44 source "drivers/rtc/Kconfig.am1805"
45 source "drivers/rtc/Kconfig.ambiq"
46 source "drivers/rtc/Kconfig.ds1307"
47 source "drivers/rtc/Kconfig.emul"
[all …]
/Zephyr-latest/soc/intel/intel_adsp/common/include/
Dadsp_clk.h4 * SPDX-License-Identifier: Apache-2.0
20 /** @brief Set cAVS clock frequency
22 * Set xtensa core clock speed.
24 * @param freq Clock frequency index to be set
26 * @return 0 on success, -EINVAL if freq_idx is not valid
30 /** @brief Get list of cAVS clock information
32 * Returns an array of clock information, one for each core.
34 * @return array with clock information
65 /* Clock sources used by dai */
84 /** @brief Check if clock source is supported
[all …]
/Zephyr-latest/samples/subsys/usb/uac2_implicit_feedback/
Dapp.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <dt-bindings/usb/audio.h>
13 full-speed;
14 audio-function = <AUDIO_FUNCTION_HEADSET>;
17 compatible = "zephyr,uac2-clock-source";
18 clock-type = "internal-programmable";
19 frequency-control = "host-programmable";
20 sampling-frequencies = <48000>;
24 compatible = "zephyr,uac2-input-terminal";
25 clock-source = <&uac_aclk>;
[all …]
/Zephyr-latest/dts/bindings/i2s/
Dnordic,nrf-i2s.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Nordic I2S (Inter-IC sound interface)
6 compatible: "nordic,nrf-i2s"
8 include: [i2s-controller.yaml, pinctrl-device.yaml]
17 pinctrl-0:
20 pinctrl-names:
23 clock-source:
27 Clock source to be used by the I2S peripheral for the master clock
30 - "PCLK32M": 32 MHz peripheral clock, synchronous to HFCLK
31 - "PCLK32M_HFXO": PCLK32M running off the 32 MHz crystal oscillator
[all …]
/Zephyr-latest/dts/bindings/phy/
Drenesas,ra-usbphyc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "renesas,ra-usbphyc"
8 include: phy-controller.yaml
11 clock:
14 Clock source for PHY clock in case internal clock is using
16 phys-clock-src:
19 - "internal"
20 - "xtal"
22 Select clock source for PHY clock as XTAL or use internal clock
24 "#phy-cells":
/Zephyr-latest/dts/bindings/audio/
Dnordic,nrf-pdm.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nordic,nrf-pdm"
8 include: ["base.yaml", "pinctrl-device.yaml", "memory-region.yaml", "nordic-clockpin.yaml"]
17 pinctrl-0:
20 pinctrl-names:
23 clock-source:
27 Clock source to be used by the PDM peripheral. The following options
29 - "PCLK32M": 32 MHz peripheral clock, synchronous to HFCLK
30 - "PCLK32M_HFXO": PCLK32M running off the 32 MHz crystal oscillator
31 (HFXO) for better clock accuracy and jitter performance
[all …]
/Zephyr-latest/samples/drivers/clock_control_xec/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
12 #include <zephyr/dt-bindings/pinctrl/mchp-xec-pinctrl.h>
24 uint32_t r = pcr->PWR_RST_STS; in pcr_clock_regs()
30 r = pcr->OSC_ID; in pcr_clock_regs()
33 r = pcr->PROC_CLK_CTRL; in pcr_clock_regs()
34 LOG_INF("PCR Processor Clock Control register = 0x%x", r); in pcr_clock_regs()
36 r = pcr->SLOW_CLK_CTRL; in pcr_clock_regs()
37 LOG_INF("PCR Slow Clock Control register = 0x%x", r); in pcr_clock_regs()
43 uint32_t cken = vbr->CLK32_EN; in vbat_clock_regs()
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