4  * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
12 #include <zephyr/dt-bindings/pinctrl/mchp-xec-pinctrl.h>
24 	uint32_t r = pcr->PWR_RST_STS;  in pcr_clock_regs()
30 	r = pcr->OSC_ID;  in pcr_clock_regs()
33 	r = pcr->PROC_CLK_CTRL;  in pcr_clock_regs()
34 	LOG_INF("PCR Processor Clock Control register = 0x%x", r);  in pcr_clock_regs()
36 	r = pcr->SLOW_CLK_CTRL;  in pcr_clock_regs()
37 	LOG_INF("PCR Slow Clock Control register = 0x%x", r);  in pcr_clock_regs()
43 	uint32_t cken = vbr->CLK32_EN;  in vbat_clock_regs()
45 	LOG_INF("MEC152x VBAT Clock registers");  in vbat_clock_regs()
48 		LOG_INF("32KHz clock source is XTAL");  in vbat_clock_regs()
50 			LOG_INF("XTAL configured for single-ended using XTAL2 pin"  in vbat_clock_regs()
57 		LOG_INF("32KHz clock source is the Internal Silicon 32KHz OSC");  in vbat_clock_regs()
60 		LOG_INF("32KHz clock domain uses the 32KHZ_IN pin(GPIO_0165 F1)");  in vbat_clock_regs()
62 		LOG_INF("32KHz clock domain uses the 32KHz clock source");  in vbat_clock_regs()
65 	LOG_INF("32KHz trim = 0x%08x", vbr->CKK32_TRIM);  in vbat_clock_regs()
71 	uint32_t pfrs = vbr->PFRS;  in vbat_power_fail()
73 	LOG_INF("MEC152x VBAT Power-Fail-Reset-Status = 0x%x", pfrs);  in vbat_power_fail()
76 		LOG_INF("WARNING: VBAT POR. Clock control register settings lost during"  in vbat_power_fail()
80 	vbr->PFRS = 0xffffffffU;  in vbat_power_fail()
88 		LOG_INF("PLL 32K clock source is Internal Silicon OSC(VTR)");  in print_pll_clock_src()
90 		LOG_INF("PLL 32K clock source is XTAL input(VTR)");  in print_pll_clock_src()
92 		LOG_INF("PLL 32K clock source is 32KHZ_IN pin(VTR)");  in print_pll_clock_src()
94 		LOG_INF("PLL 32K clock source is OFF. PLL disabled. Running on Ring OSC");  in print_pll_clock_src()
103 		LOG_INF("Periph 32K clock source is InternalOSC(VTR) and InternalOSC(VBAT)");  in print_periph_clock_src()
105 		LOG_INF("Periph 32K clock source is XTAL(VTR) and XTAL(VBAT)");  in print_periph_clock_src()
107 		LOG_INF("Periph 32K clock source is 32KHZ_PIN(VTR) and InternalOSC(VBAT)");  in print_periph_clock_src()
109 		LOG_INF("Periph 32K clock source is 32KHZ_PIN fallback to XTAL when VTR is off");  in print_periph_clock_src()
116 	uint32_t pcr_clk_src = pcr->CLK32K_SRC_VTR;  in pcr_clock_regs()
117 	uint32_t r = pcr->PWR_RST_STS;  in pcr_clock_regs()
125 	r = pcr->OSC_ID;  in pcr_clock_regs()
128 	r = pcr->PROC_CLK_CTRL;  in pcr_clock_regs()
129 	LOG_INF("PCR Processor Clock Control register = 0x%x", r);  in pcr_clock_regs()
131 	r = pcr->SLOW_CLK_CTRL;  in pcr_clock_regs()
132 	LOG_INF("PCR Slow Clock Control register = 0x%x", r);  in pcr_clock_regs()
134 	r = pcr->CNT32K_PER;  in pcr_clock_regs()
135 	LOG_INF("PCR 32KHz Clock Monitor Pulse High Count register = 0x%x", r);  in pcr_clock_regs()
137 	r = pcr->CNT32K_PER_MIN;  in pcr_clock_regs()
138 	LOG_INF("PCR 32KHz Clock Monitor Period Maximum Count register = 0x%x", r);  in pcr_clock_regs()
140 	r = pcr->CNT32K_DV;  in pcr_clock_regs()
141 	LOG_INF("PCR 32KHz Clock Monitor Duty Cycle Variation register = 0x%x", r);  in pcr_clock_regs()
143 	r = pcr->CNT32K_DV_MAX;  in pcr_clock_regs()
144 	LOG_INF("PCR 32KHz Clock Monitor Duty Cycle Variation Max register = 0x%x", r);  in pcr_clock_regs()
146 	r = pcr->CNT32K_VALID;  in pcr_clock_regs()
147 	LOG_INF("PCR 32KHz Clock Monitor Valid register = 0x%x", r);  in pcr_clock_regs()
149 	r = pcr->CNT32K_VALID_MIN;  in pcr_clock_regs()
150 	LOG_INF("PCR 32KHz Clock Monitor Valid Min register = 0x%x", r);  in pcr_clock_regs()
152 	r = pcr->CNT32K_CTRL;  in pcr_clock_regs()
153 	LOG_INF("PCR 32KHz Clock Monitor Control register = 0x%x", r);  in pcr_clock_regs()
155 	r = pcr->CLK32K_MON_ISTS;  in pcr_clock_regs()
156 	LOG_INF("PCR 32KHz Clock Monitor Control Status register = 0x%x", r);  in pcr_clock_regs()
162 	uint32_t vb_clk_src = vbr->CLK32_SRC;  in vbat_clock_regs()
170 	uint32_t pfrs = vbr->PFRS;  in vbat_power_fail()
172 	LOG_INF("MEC172x VBAT Power-Fail-Reset-Status = 0x%x", pfrs);  in vbat_power_fail()
175 		LOG_INF("WARNING: VBAT POR. Clock control register settings"  in vbat_power_fail()
180 	vbr->PFRS = 0xffffffffU;  in vbat_power_fail()
198 	{ .id = MCHP_XEC_PCR_CLK_PERIPH_FAST, .name = "Periph-fast" },
199 	{ .id = MCHP_XEC_PCR_CLK_PERIPH_SLOW, .name = "Periph-slow" },
209 	LOG_INF("XEC Clock control driver sample");  in main()
212 		LOG_ERR("XEC clock control driver is not ready!");  in main()
219 	r = gpio->CTRL[MCHP_XEC_PINCTRL_REG_IDX(0165)];  in main()