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/Zephyr-Core-3.5.0/samples/drivers/clock_control_litex/
DREADME.rst1 .. zephyr:code-sample:: clock-control-litex
2 :name: LiteX clock control driver
3 :relevant-api: clock_control_interface
5 Use LiteX clock control driver to generate multiple clock signals.
10 This sample is providing an overview of LiteX clock control driver capabilities.
11 The driver uses Mixed Mode Clock Manager (MMCM) module to generate up to 7 clocks with defined phas…
15 * LiteX-capable FPGA platform with MMCM modules (for example Digilent Arty A7 development board)
16 * SoC configuration with VexRiscv soft CPU and Xilinx 7-series MMCM interface in LiteX (S7MMCM modu…
17 * Optional: clock output signals redirected to output pins for testing
21 …guration of the driver, including default settings for clock outputs, is held in Device Tree clock…
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/Zephyr-Core-3.5.0/include/zephyr/drivers/clock_control/
Dclock_control_litex.h4 * SPDX-License-Identifier: Apache-2.0
9 * @brief LiteX Clock Control driver interface
16 * @brief LiteX Clock Control driver interface
17 * @defgroup clock_control_litex_interface LiteX Clock Control driver interface
18 * @brief LiteX Clock Control driver interface
29 * @brief Structure for interfacing with clock control API
31 * @param clkout_nr Number of clock output to be changed
33 * @param phase Phase offset in degrees
34 * @param duty Duty cycle of clock signal in percent
40 uint16_t phase; member
/Zephyr-Core-3.5.0/dts/bindings/clock/
Dlitex,clkout.yaml2 # SPDX-License-Identifier: Apache-2.0
7 LiteX Mixed Mode Clock Manager clock output binding
13 "#clock-cells":
17 Number of cells in a clock specifier;
18 Typically 0 for nodes with a single clock output
19 and 1 for nodes with multiple clock outputs.
22 clock-output-names:
26 string of clock output signal name.
28 litex,clock-frequency:
32 default frequency in Hz for clock output
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Dlitex,clk.yaml2 # SPDX-License-Identifier: Apache-2.0
4 include: [clock-controller.yaml, base.yaml]
7 LiteX Mixed Mode Clock Manager
8 Common clock driver with MMCM unit for dynamic reconfiguration
9 of up to 7 clock outputs with ability to change frequency, duty
10 cycle and phase offset
14 clock-cells:
15 - id
22 "#clock-cells":
26 clock-output-names:
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/Zephyr-Core-3.5.0/samples/drivers/clock_control_litex/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
13 /* Select clock outputs for tests [0-6] */
33 /* Values for phase test */
62 /* LiteX Common Clock Driver tests */
75 printf("CLKOUT%d: get_status: rate:%d phase:%d duty:%d\n", in litex_clk_test_getters()
76 i, setup.rate, setup.phase, setup.duty); in litex_clk_test_getters()
90 .phase = LITEX_TEST_SINGLE_PHASE_VAL in litex_clk_test_single()
96 .phase = LITEX_TEST_SINGLE_PHASE_VAL2, in litex_clk_test_single()
122 .phase = LITEX_TEST_FREQUENCY_PHASE_VAL in litex_clk_test_freq()
138 * specific clock output depends on devicetree config in litex_clk_test_freq()
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/Zephyr-Core-3.5.0/dts/bindings/memory-controllers/
Dst,stm32-fmc-nor-psram.yaml2 # SPDX-License-Identifier: Apache-2.0
11 - 8 bits
12 - 16 bits
13 - 32 bits
15 - Asynchronous mode
16 - Burst mode for synchronous accesses with configurable option to split burst
18 - Multiplexed or non-multiplexed
20 - Asynchronous mode
21 - Burst mode for synchronous accesses
22 - Multiplexed or non-multiplexed
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/Zephyr-Core-3.5.0/drivers/clock_control/
DKconfig.litex1 # LiteX SoC Builder clock control driver
4 # SPDX-License-Identifier: Apache-2.0
7 bool "LiteX MMCM clock control"
11 This option enables LiteX clock control driver.
12 It gives ability to change clock parameters
13 such as phase, duty cycle, frequency for up to 7
14 clock outputs
Dclock_control_litex.c4 * SPDX-License-Identifier: Apache-2.0
64 …* https://github.com/Digilent/Zybo-hdmi-out/blob/b991fff6e964420ae3c00c3dbee52f2ad748b3ba/sdk/disp…
211 return litex_clk_filter_table[glob_mul - 1]; in litex_clk_lookup_filter()
217 return litex_clk_lock_table[glob_mul - 1]; in litex_clk_lookup_lock()
232 int assert = (1 << (drp[reg].size * BITS_PER_BYTE)) - 1; in litex_clk_assert_reg()
249 timeout = ldev->timeout.lock; in litex_clk_wait()
251 timeout = ldev->timeout.drdy; in litex_clk_wait()
255 timeout--; in litex_clk_wait()
260 return -ETIME; in litex_clk_wait()
301 ldev->g_config.mul = 1; in litex_clk_update_global_config()
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Dclock_stm32f2_f4_f7.c5 * SPDX-License-Identifier: Apache-2.0
68 * locking phase since the system will be stalled during the switch in config_pll_sysclock()
69 * (ODSW) but the PLL clock system will be running during the locking in config_pll_sysclock()
70 * phase. See reference manual (RM0431) §4.1.4 Voltage regulator in config_pll_sysclock()
71 * Sub section: Entering Over-drive mode. in config_pll_sysclock()
88 * And start waiting for the PLL locking phase to complete. in config_pll_sysclock()
124 /* Power Interface clock enabled by default */ in config_enable_default_clocks()
Dclock_control_litex.h4 * SPDX-License-Identifier: Apache-2.0
65 lcko = &ldev->clkouts[N]; \
66 lcko->id = CLKOUT_ID(N); \
68 lcko->clkout_div = clkout_div; \
69 lcko->def.freq = CLKOUT_FREQ(N); \
70 lcko->def.phase = CLKOUT_PHASE(N); \
71 lcko->def.duty.num = CLKOUT_DUTY_NUM(N); \
72 lcko->def.duty.den = CLKOUT_DUTY_DEN(N); \
73 lcko->margin.m = CLKOUT_MARGIN(N); \
74 lcko->margin.exp = CLKOUT_MARGIN_EXP(N);
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/Zephyr-Core-3.5.0/dts/bindings/dsa/
Dmicrochip_dsa.yaml2 # SPDX-License-Identifier: Apache-2.0
7 include: [spi-device.yaml]
9 dsa-master-port:
12 dsa-slave-ports:
15 spi-cpha:
18 Set to indicate phase starts with asserted half-phase (CPHA=1).
20 spi-cpol:
23 Set to indicate clock leading edge is falling (CPOL=1).
25 reset-gpios:
26 type: phandle-array
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/Zephyr-Core-3.5.0/dts/bindings/pwm/
Dnxp,s32-emios-pwm.yaml2 # SPDX-License-Identifier: Apache-2.0
11 - Channel 0 for mode OPWFMB
12 - Channel 1 for mode OPWMB
13 - Channel 2 for mode OPWMCB with deadtime inserted at leading edge
14 - Channel 3 for mode SAIC, use internal timebase with input filter = 2 eMIOS clock
19 pwm-mode = "OPWFMB";
22 duty-cycle = <32768>;
28 master-bus = <&emios1_bus_a>;
29 pwm-mode = "OPWMB";
30 duty-cycle = <32768>;
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/Zephyr-Core-3.5.0/dts/bindings/mtd/
Dnordic,qspi-nor.yaml2 # SPDX-License-Identifier: Apache-2.0
7 compatible: "nordic,qspi-nor"
9 include: [base.yaml, "jedec,spi-nor-common.yaml"]
11 on-bus: qspi
17 jedec-id:
23 The size in bits. Set this or size-in-bytes, but not both.
25 size-in-bytes:
31 quad-enable-requirements:
37 - "fastread" # Single data line SPI, FAST_READ (0x0B)
38 - "read2o" # Dual data line SPI, READ2O (0x3B)
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/Zephyr-Core-3.5.0/include/zephyr/net/
Dgptp.h4 * SPDX-License-Identifier: Apache-2.0
96 /* Pre-calculated constants */
126 /** Clock identity of the port. */
180 /** Control value. Sync: 0, Follow-up: 2, Others: 5. */
191 (uscaled_ns_ptr)->low = \
193 (uscaled_ns_ptr)->high = 0; \
200 * @brief Define callback that is called after a phase discontinuity has been
218 * @brief Phase discontinuity callback structure.
220 * Stores the phase discontinuity callback information. Caller must make sure
229 /** Phase discontinuity callback. */
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Dnet_time.h4 * SPDX-License-Identifier: Apache-2.0
35 * clock that does not wrap during uptime and is - in a certain, well-defined
36 * sense - common to all local network interfaces, sometimes even to remote
44 * well-defined tolerances. Network uptime therefore differs from time
47 * frequencies, accuracy and precision. To co-operate, these hardware counters
48 * will have to be "syntonized" or "disciplined" (i.e. frequency and phase
51 * phase, they do not usually share the same epoch (zero-point).
60 * possible especially when referring to the kernel system clock or values of
64 * it only covers roughly +/- ~290 years. It also cannot be used to represent
67 * @ref timespec (C11, POSIX.1-2001), @ref timeval (POSIX.1-2001) or broken down
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/Zephyr-Core-3.5.0/dts/bindings/sdhc/
Dzephyr,sdhc-spi-slot.yaml3 compatible: "zephyr,sdhc-spi-slot"
5 include: [spi-device.yaml]
8 power-delay-ms:
16 spi-clock-mode-cpol:
19 Clock polarity to use for SPI SDHC. Some cards respond properly
20 only when the clock goes low when not active.
22 spi-clock-mode-cpha:
25 Clock phase: this dictates when is the data captured, and depends
26 on the clock's polarity. When mode-cpol is set and this option as well,
30 pwr-gpios:
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/Zephyr-Core-3.5.0/dts/bindings/qspi/
Dnxp,s32-qspi.yaml2 # SPDX-License-Identifier: Apache-2.0
10 compatible: "nxp,s32-qspi"
12 include: [base.yaml, pinctrl-device.yaml]
20 "#address-cells":
23 "#size-cells":
26 data-rate:
29 - SDR
30 - DDR
33 - Single Data Rate (SDR): sampling of incoming data occurs on single edges.
34 - Double Data Rate (DDR): sampling of incoming data occurs on both edges.
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/Zephyr-Core-3.5.0/dts/bindings/adc/
Datmel,sam-adc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "atmel,sam-adc"
8 include: [adc-controller.yaml, pinctrl-device.yaml]
23 description: CPU clock prescaler applied to get the ADC clock.
25 startup-time:
29 ADC startup time in ADC clock cycles.
32 settling-time:
36 ADC settling time in ADC clock cycles. When the gain, offset
39 settling time before starting the tracking phase.
42 tracking-time:
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/Zephyr-Core-3.5.0/dts/bindings/led_strip/
Dworldsemi,ws2812-spi.yaml2 # SPDX-License-Identifier: Apache-2.0
14 - spi-max-frequency
15 - spi-zero-frame
16 - spi-one-frame.
21 compatible: "worldsemi,ws2812-spi"
23 include: [spi-device.yaml, ws2812.yaml]
27 spi-cpol:
29 description: Set SPI clock polarity.
31 spi-cpha:
33 description: Set SPI clock phase.
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/Zephyr-Core-3.5.0/dts/bindings/sensor/
Dnxp,mcux-qdec.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,mcux-qdec"
8 include: [pinctrl-device.yaml, sensor-device.yaml]
17 counts-per-revolution:
24 single-phase-mode:
31 filter-count:
39 filter-sample-period:
42 The sampling period (in IPBus clock cycles) of the decoder input signals.
48 ((FILT_CNT + 3) * FILT_PER) FILT clock cycles + 2 IPBus clock periods.
/Zephyr-Core-3.5.0/drivers/usb/device/
Dusb_dc_sam_usbc.c4 * SPDX-License-Identifier: Apache-2.0
122 if (regs->UESTA[ep_idx] != dev_ep_sta_dbg[0][ep_idx]) { in usb_dc_sam_usbc_isr_sta_dbg()
123 dev_ep_sta_dbg[0][ep_idx] = regs->UESTA[ep_idx]; in usb_dc_sam_usbc_isr_sta_dbg()
128 regs->UDCON, regs->UDINT, regs->UDINTE, in usb_dc_sam_usbc_isr_sta_dbg()
129 regs->UECON[ep_idx], regs->UESTA[ep_idx], in usb_dc_sam_usbc_isr_sta_dbg()
136 regs->UDCON, regs->UDINT, regs->UDINTE, in usb_dc_sam_usbc_isr_sta_dbg()
137 regs->UECON[ep_idx], regs->UESTA[ep_idx]); in usb_dc_sam_usbc_isr_sta_dbg()
155 return USBC->USBCON & USBC_USBCON_FRZCLK; in usb_dc_sam_usbc_is_frozen_clk()
160 USBC->USBCON |= USBC_USBCON_FRZCLK; in usb_dc_sam_usbc_freeze_clk()
165 USBC->USBCON &= ~USBC_USBCON_FRZCLK; in usb_dc_sam_usbc_unfreeze_clk()
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/Zephyr-Core-3.5.0/dts/riscv/
Driscv32-litex-vexriscv.dtsi2 * Copyright (c) 2018 - 2020 Antmicro <www.antmicro.com>
4 * SPDX-License-Identifier: Apache-2.0
8 #address-cells = <1>;
9 #size-cells = <1>;
10 compatible = "litex,vexriscv", "litex-dev";
19 #address-cells = <1>;
20 #size-cells = <0>;
22 clock-frequency = <100000000>;
28 timebase-frequency = <32768>;
32 #address-cells = <1>;
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/Zephyr-Core-3.5.0/subsys/net/l2/ethernet/gptp/
Dgptp_data_set.h4 * SPDX-License-Identifier: Apache-2.0
43 #define GPTP_PORT_INDEX (port - GPTP_PORT_START)
53 (&gptp_domain.port_ds[port - GPTP_PORT_START])
55 (&gptp_domain.port_state[port - GPTP_PORT_START])
57 (&gptp_domain.port_bmca_data[port - GPTP_PORT_START])
59 gptp_domain.iface[port - GPTP_PORT_START]
63 (&gptp_domain.port_param_ds[port - GPTP_PORT_START])
67 (global_ds->reselect_array &= (~(1 << (port - 1))))
69 (global_ds->reselect_array |= (1 << (port - 1)))
71 (global_ds->selected_array &= (~(1 << (port - 1))))
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/Zephyr-Core-3.5.0/drivers/wifi/winc1500/
Dwifi_winc1500_config.h4 * SPDX-License-Identifier: Apache-2.0
11 ---------------------------------
12 ---------- PIN settings ---------
13 ---------------------------------
20 ---------------------------------
21 ---------- SPI settings ---------
22 ---------------------------------
50 /** Clock polarity & phase. */
54 /** SPI clock. */
58 ---------------------------------
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/Zephyr-Core-3.5.0/include/zephyr/drivers/
Dcan.h6 * SPDX-License-Identifier: Apache-2.0
38 * @brief Bit mask for a standard (11-bit) CAN identifier.
42 * @brief Maximum value for a standard (11-bit) CAN identifier.
46 * @brief Bit mask for an extended (29-bit) CAN identifier.
50 * @brief Maximum value for an extended (29-bit) CAN identifier.
58 * @brief Maximum data length code for CAN-FD.
92 /** Controller allows transmitting/receiving CAN-FD frames. */
117 /** Error-active state (RX/TX error count < 96). */
119 /** Error-warning state (RX/TX error count < 128). */
121 /** Error-passive state (RX/TX error count < 256). */
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